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381 Commits

Author SHA1 Message Date
nella 7f5b7aacb9 Count module output ports as consumers. 2026-08-12 10:00:30 +02:00
Lofty fd6367405e
Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8 
abc_ops_reintegrate: xaiger2 compatibility
 2026-08-10 13:14:40 +00:00
Miodrag Milanovic ebf286ab40 Code cleanup 2026-08-04 17:18:22 +02:00
Lofty 5e6fcf3b36 cleanup 2026-08-03 13:28:33 +01:00
Lofty 6d9f5d1b0c wip 2026-08-03 12:34:01 +01:00
Miodrag Milanovic 130e39b06d nexus: disable dsp test, takes very long 2026-07-30 17:46:25 +02:00
nella 511017acc1
Merge branch 'main' into nella/fuse-2 2026-07-24 12:20:35 +02:00
nella 5e59deecc3 Fix test desc. 2026-07-24 12:07:10 +02:00
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
Lofty 75286287c6
Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
nella f5809a7c2c
Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
Miodrag Milanovic 8ad4ffcdd1 Cleanup 2026-07-08 08:34:01 +02:00
Leo Moser e87d8e162e fabulous: update tests for new options 
Signed-off-by: Leo Moser <leomoser99@gmail.com>
 2026-07-01 13:38:44 +02:00
Leo Moser 655cb40d0f fabulous: add `--cells-map` option 
Signed-off-by: Leo Moser <leomoser99@gmail.com>
 2026-06-30 16:09:51 +02:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Miodrag Milanovic 3ac58b3ac1 Fixed line endings 2026-06-23 07:17:22 +02:00
nella 2b6214ad71 Add eq tests. 2026-06-22 14:25:43 +02:00
Lofty 091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
nella b3b1394cf1 Fixup level policy. 2026-06-18 18:00:51 +02:00
nella b2d688dbf9 Error out on latches. 2026-06-17 17:36:32 +02:00
nella d52670e58b Replace suitable (2^k-1)-x with ~x. 2026-06-10 11:29:55 +02:00
nella 5328762fe5 Add regtype checks to tests. 2026-06-03 12:51:57 +02:00
nella 3948e7f94c Use Nexus DSP pipelined registers. 2026-06-03 12:46:26 +02:00
nella d6106f141c Add matching for fused mac operations for Nexus (fix #5906). 2026-05-28 09:58:18 +02:00
Miodrag Milanovic c0779f488a Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
Miodrag Milanovic 7fe32137bd Revert "Fix tests due to ABC improvements" 
This reverts commit 417e871b06.
 2026-05-11 14:47:08 +02:00
Lofty fecea911ff synth_gatemate: add -abc_new option 2026-05-06 14:02:48 +01:00
Miodrag Milanovic 5737d2db35 Cleanup 2026-04-16 11:00:44 +02:00
Miodrag Milanovic a490f1c3c4 Move output redirect to one place 2026-04-16 11:00:44 +02:00
Miodrag Milanovic f42800d4d3 Convert arch 2026-04-16 11:00:44 +02:00
Miodrag Milanovic ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 999255e40c Clean some seed-tests outputs 2026-04-16 11:00:44 +02:00
Miodrag Milanovic 417e871b06 Fix tests due to ABC improvements 2026-03-30 15:23:27 +01:00
Miodrag Milanović cc915b4c76
Merge pull request #5717 from zaun/latch-support 
gowin: add hardware latch support (DL/DLN/DLC/DLP variants)
 2026-03-23 16:51:30 +00:00
Miodrag Milanovic 602f3fd1a5 Add missing EOL 2026-03-06 09:10:55 +01:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Justin Zaun 9288889e20 gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 
Add simulation models, techmap, and dfflegalize rules for Gowin
DL-series latch primitives. Latches use the same physical BEL as
DFFs with REGMODE set to LATCH. All 12 variants are supported:
DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
 2026-03-05 16:04:23 +01:00
Lofty cd60dd4912 synth_analogdevices: update timing model and tests 2026-03-05 05:37:13 +00:00
Krystine Sherwin 5d3ed5a418 analogdevices: Extra tests 
`mem_gen.py` based on quicklogic tests.
Remove BUFG from `lutram.ys`.
Extra `sync_ram_sp` models in `arch/common/blockram.v`.
Add analogdevices to main makefile tests.
Not all the other tests are passing, but that's fine for now.
 2026-03-05 05:37:13 +00:00
Lofty 39cb61615f analogdevices: DSP inference 2026-03-05 05:37:12 +00:00
Krystine Sherwin 9be3cfb3f9 analogdevices: Update lutram.ys test 2026-03-05 05:37:12 +00:00
Lofty 6f205b41f5 test suite 2026-03-05 05:37:12 +00:00
Andrew Pullin 5970be33fb abc9: preserve topological-loop asserts with targeted SCC fallback 
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.

Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).

To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.

Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
 2026-02-26 22:30:32 -08:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Krystine Sherwin fd311c5501 tests/arch/gowin: Add wr_en test 2026-02-22 09:00:37 +01:00
Miodrag Milanović e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Maxim Kudinov b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Gus Smith b04948a8cd Simplify test 2026-02-09 09:38:45 -08:00
Gus Smith 3f01d7a33a Add test 2026-02-03 14:41:08 -08:00