mirror of https://github.com/YosysHQ/yosys.git
Add matching for fused mac operations for Nexus (fix #5906).
This commit is contained in:
nella
nella
parent
94ec78b6e8
commit
d6106f141c
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@ -1,6 +1,7 @@
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OBJS += techlibs/lattice/synth_lattice.o
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OBJS += techlibs/lattice/lattice_gsr.o
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OBJS += techlibs/lattice/lattice_dsp_nexus.o
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh))
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$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh))
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@ -50,3 +51,10 @@ $(eval $(call add_share_file_and_rename,share/ecp5,techlibs/lattice/cells_bb_ecp
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$(eval $(call add_share_file,share/nexus,techlibs/lattice/parse_init.vh))
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$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_sim_nexus.v,cells_sim.v))
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$(eval $(call add_share_file_and_rename,share/nexus,techlibs/lattice/cells_bb_nexus.v,cells_xtra.v))
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techlibs/lattice/%_pm.h: passes/pmgen/pmgen.py techlibs/lattice/%.pmg
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(notdir $*) $(filter-out $<,$^)
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GENFILES += techlibs/lattice/lattice_dsp_nexus_pm.h
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techlibs/lattice/lattice_dsp_nexus.o: techlibs/lattice/lattice_dsp_nexus_pm.h
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$(eval $(call add_extra_objs,techlibs/lattice/lattice_dsp_nexus_pm.h))
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@ -77,3 +77,92 @@ module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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.Z(Y)
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);
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endmodule
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module \$__NX_MAC18X18 (A, B, C, Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter C_WIDTH = 48;
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parameter Y_WIDTH = 48;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter SUBTRACT = 0;
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input [17:0] A;
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input [17:0] B;
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input [47:0] C;
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output [47:0] Y;
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wire [53:0] Z_out;
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assign Y = Z_out[47:0];
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MULTADDSUB18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGINPUTC("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.C({6'b0, C}),
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.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
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.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
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.Z(Z_out)
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);
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endmodule
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module \$__NX_PREADD18X18 (A, B, C, Y, CLK);
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parameter PIPELINED = 0;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter C_SIGNED = 0;
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input [17:0] A;
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input [17:0] B;
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input [17:0] C;
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input CLK;
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output [47:0] Y;
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wire [35:0] Z_out;
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assign Y = A_SIGNED ? {{12{Z_out[35]}}, Z_out} : {12'b0, Z_out};
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MULTPREADD18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGINPUTC("BYPASS"),
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.REGOUTPUT(PIPELINED ? "REGISTER" : "BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.C(C),
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.CLK(CLK),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDC(C_SIGNED ? 1'b1 : 1'b0),
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.Z(Z_out)
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);
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endmodule
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module \$__NX_MAC9X9WIDE_4LANE (A0, B0, A1, B1, A2, B2, A3, B3, Y);
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parameter SIGNED = 0;
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input [8:0] A0, B0, A1, B1, A2, B2, A3, B3;
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output [47:0] Y;
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wire [53:0] Z_out;
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assign Y = Z_out[47:0];
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MULTADDSUB9X9WIDE #(
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.REGINPUTAB0("BYPASS"),
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.REGINPUTAB1("BYPASS"),
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.REGINPUTAB2("BYPASS"),
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.REGINPUTAB3("BYPASS"),
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.REGINPUTC("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A0(A0), .B0(B0),
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.A1(A1), .B1(B1),
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.A2(A2), .B2(B2),
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.A3(A3), .B3(B3),
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.C(54'b0),
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.SIGNED(SIGNED ? 1'b1 : 1'b0),
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.ADDSUB(4'b0000),
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.Z(Z_out)
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);
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endmodule
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@ -0,0 +1,36 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "techlibs/lattice/lattice_dsp_nexus_pm.h"
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struct LatticeDspNexusPass : public Pass {
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LatticeDspNexusPass() : Pass("lattice_dsp_nexus", "Lattice Nexus DSP inference") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" lattice_dsp_nexus [options] [selection]\n");
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log("\n");
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log("Infer Lattice Nexus sysDSP macrocells (MULTADDSUB18X18, MULTPREADD18X18,\n");
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log("MULTADDSUB9X9WIDE) from MAC and dot-product patterns.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing LATTICE_DSP_NEXUS pass.\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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lattice_dsp_nexus_pm pm(module, module->cells());
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pm.run_nexus_mac9_4lane();
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pm.run_nexus_mac18();
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pm.run_nexus_preadd18();
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}
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}
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} LatticeDspNexusPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,165 @@
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pattern nexus_mac18
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match mul
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select mul->type.in($mul)
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select GetSize(port(mul, \A)) <= 18
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select GetSize(port(mul, \B)) <= 18
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select GetSize(port(mul, \Y)) <= 48
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endmatch
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match add
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select add->type.in($add, $sub)
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select GetSize(port(add, \Y)) <= 48
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choice <IdString> AB {\A, \B}
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index <SigBit> port(add, AB)[0] === port(mul, \Y)[0]
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endmatch
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code
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SigSpec mul_out = port(mul, \Y);
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IdString add_AB;
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Cell *mac = module->addCell(NEW_ID, "$__NX_MAC18X18");
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IdString add_C = (add_AB == \A) ? \B : \A;
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mac->setPort(\A, port(mul, \A));
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mac->setPort(\B, port(mul, \B));
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mac->setPort(\C, port(add, add_C));
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mac->setPort(\Y, port(add, \Y));
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mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
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mac->setParam(\B_SIGNED, mul->getParam(\B_SIGNED));
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mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
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autoremove(mul);
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autoremove(add);
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accept;
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endcode
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pattern nexus_preadd18
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match preadd
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select preadd->type.in($add, $sub)
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select GetSize(port(preadd, \Y)) <= 19
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endmatch
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match mul
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select mul->type.in($mul)
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select GetSize(port(mul, \Y)) <= 48
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choice <IdString> mul_AB {\A, \B}
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index <SigBit> port(mul, mul_AB)[0] === port(preadd, \Y)[0]
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endmatch
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match pipe_ff
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select pipe_ff->type.in($dff, $dffe, $sdff, $sdffe)
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index <SigBit> port(pipe_ff, \D)[0] === port(mul, \Y)[0]
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optional
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endmatch
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code
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SigSpec preadd_out = port(preadd, \Y);
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IdString actual_mul_AB;
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Cell *mac = module->addCell(NEW_ID, "$__NX_PREADD18X18");
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IdString mul_other = (actual_mul_AB == \A) ? \B : \A;
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IdString sgn_AC = (mul_other == \A) ? \B_SIGNED : \A_SIGNED;
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IdString sgn_B = (mul_other == \A) ? \A_SIGNED : \B_SIGNED;
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SigSpec sig_A = port(preadd, \A);
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SigSpec sig_C = port(preadd, \B);
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SigSpec sig_B = port(mul, mul_other);
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sig_A.extend_u0(18, false);
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sig_C.extend_u0(18, false);
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sig_B.extend_u0(18, false);
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mac->setPort(\A, sig_A.extract(0, 18));
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mac->setPort(\C, sig_C.extract(0, 18));
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mac->setPort(\B, sig_B.extract(0, 18));
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if (pipe_ff) {
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mac->setPort(\Y, port(pipe_ff, \Q));
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mac->setPort(\CLK, port(pipe_ff, \CLK));
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mac->setParam(\PIPELINED, State::S1);
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} else {
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mac->setPort(\Y, port(mul, \Y));
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mac->setPort(\CLK, State::S0);
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mac->setParam(\PIPELINED, State::S0);
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}
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mac->setParam(\A_SIGNED, mul->getParam(sgn_AC));
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mac->setParam(\B_SIGNED, mul->getParam(sgn_B));
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mac->setParam(\C_SIGNED, mul->getParam(sgn_AC));
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if (pipe_ff) autoremove(pipe_ff);
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autoremove(mul);
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autoremove(preadd);
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accept;
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endcode
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pattern nexus_mac9_4lane
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match add_top
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select add_top->type == $add
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endmatch
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match add_mid
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select add_mid->type == $add
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index <SigBit> port(add_mid, \Y)[0] === port(add_top, \A)[0]
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endmatch
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match add_bot
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select add_bot->type == $add
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index <SigBit> port(add_bot, \Y)[0] === port(add_mid, \A)[0]
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endmatch
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match mul3
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select mul3->type == $mul
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select GetSize(port(mul3, \A)) <= 9 && GetSize(port(mul3, \B)) <= 9
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index <SigBit> port(mul3, \Y)[0] === port(add_top, \B)[0]
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endmatch
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match mul2
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select mul2->type == $mul
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select GetSize(port(mul2, \A)) <= 9 && GetSize(port(mul2, \B)) <= 9
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index <SigBit> port(mul2, \Y)[0] === port(add_mid, \B)[0]
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endmatch
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match mul1
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select mul1->type == $mul
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select GetSize(port(mul1, \A)) <= 9 && GetSize(port(mul1, \B)) <= 9
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index <SigBit> port(mul1, \Y)[0] === port(add_bot, \B)[0]
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endmatch
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match mul0
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select mul0->type == $mul
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select GetSize(port(mul0, \A)) <= 9 && GetSize(port(mul0, \B)) <= 9
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index <SigBit> port(mul0, \Y)[0] === port(add_bot, \A)[0]
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endmatch
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code
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Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
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bool is_signed = mul0->getParam(\A_SIGNED).as_bool();
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auto ext9 = [&](SigSpec s) {
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s.extend_u0(9, is_signed);
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return s;
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};
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mac->setPort(\A0, ext9(port(mul0, \A)));
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mac->setPort(\B0, ext9(port(mul0, \B)));
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mac->setPort(\A1, ext9(port(mul1, \A)));
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mac->setPort(\B1, ext9(port(mul1, \B)));
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mac->setPort(\A2, ext9(port(mul2, \A)));
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mac->setPort(\B2, ext9(port(mul2, \B)));
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mac->setPort(\A3, ext9(port(mul3, \A)));
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mac->setPort(\B3, ext9(port(mul3, \B)));
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mac->setPort(\Y, port(add_top, \Y));
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mac->setParam(\SIGNED, mul0->getParam(\A_SIGNED));
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autoremove(add_top);
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autoremove(add_mid);
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autoremove(add_bot);
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autoremove(mul0);
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autoremove(mul1);
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autoremove(mul2);
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autoremove(mul3);
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accept;
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endcode
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@ -425,9 +425,12 @@ struct SynthLatticePass : public ScriptPass
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run("opt_clean");
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if (help_mode) {
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run("lattice_dsp_nexus", "(only if -family lifcl/lfd2nx and unless -nodsp)");
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
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run("techmap -map +/lattice/dsp_map" + dsp_map + ".v", "(unless -nodsp)");
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} else if (have_dsp && !nodsp) {
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if (is_nexus)
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run("lattice_dsp_nexus");
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for (const auto &rule : dsp_rules) {
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run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
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rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim));
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@ -0,0 +1,76 @@
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// https://github.com/YosysHQ/yosys/issues/5906
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module mac (
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input bit clk, rst,
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input bit [17:0] a, b,
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input bit clear,
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output bit [47:0] p
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);
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bit [17:0] a_r, b_r; bit clear_r; bit [47:0] p_r;
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always_ff @(posedge clk) begin
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if (rst) begin a_r<=0; b_r<=0; clear_r<=0; p_r<=0; end
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else begin
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a_r<=a; b_r<=b; clear_r<=clear;
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p_r <= clear_r ? 48'(a_r*b_r) : 48'(p_r + 48'(a_r*b_r));
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end
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end
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assign p = p_r;
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endmodule
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module madd_pre (
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input bit clk, rst,
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input bit [17:0] a, b, c, d,
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output bit [47:0] p
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);
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bit [17:0] a_r, b_r, c_r, d_r; bit [47:0] m_r, p_r;
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always_ff @(posedge clk) begin
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if (rst) begin a_r<=0; b_r<=0; c_r<=0; d_r<=0; m_r<=0; p_r<=0; end
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else begin
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a_r<=a; b_r<=b; c_r<=c; d_r<=d;
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m_r <= 48'((a_r - d_r) * b_r);
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p_r <= 48'(m_r + 48'(c_r));
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end
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end
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assign p = p_r;
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endmodule
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module dot4 (
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input bit clk, rst,
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input bit [8:0] a0, b0, a1, b1, a2, b2, a3, b3,
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output bit [19:0] p
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);
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bit [8:0] a0_r, b0_r, a1_r, b1_r, a2_r, b2_r, a3_r, b3_r;
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bit [19:0] p_r;
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always_ff @(posedge clk) begin
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if (rst) begin
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a0_r<=0; b0_r<=0; a1_r<=0; b1_r<=0;
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a2_r<=0; b2_r<=0; a3_r<=0; b3_r<=0;
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p_r<=0;
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end else begin
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a0_r<=a0; b0_r<=b0; a1_r<=a1; b1_r<=b1;
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a2_r<=a2; b2_r<=b2; a3_r<=a3; b3_r<=b3;
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p_r <= 20'(20'(a0_r*b0_r) + 20'(a1_r*b1_r) + 20'(a2_r*b2_r) + 20'(a3_r*b3_r));
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end
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end
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assign p = p_r;
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endmodule
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// Oversized 24x24 MAC
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module neg_mac24 (input clk, clear, input [23:0] a, b, output [47:0] p);
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reg [23:0] a_r, b_r; reg [47:0] p_r; reg clear_r;
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always_ff @(posedge clk) begin
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a_r <= a; b_r <= b; clear_r <= clear;
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p_r <= clear_r ? 48'(a_r*b_r) : 48'(p_r + 48'(a_r*b_r));
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end
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assign p = p_r;
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endmodule
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// Dot product with mixed 9x9 and 18x18 lanes
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module neg_dot_mixed (input clk, input [8:0] a0,b0,a1,b1, input [17:0] a2, b2, output [35:0] p);
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reg [8:0] a0_r,b0_r,a1_r,b1_r; reg [17:0] a2_r, b2_r; reg [35:0] p_r;
|
||||
always_ff @(posedge clk) begin
|
||||
a0_r<=a0; b0_r<=b0; a1_r<=a1; b1_r<=b1; a2_r<=a2; b2_r<=b2;
|
||||
p_r <= 36'(36'(a0_r*b0_r) + 36'(a1_r*b1_r) + 36'(a2_r*b2_r));
|
||||
end
|
||||
assign p = p_r;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
read_verilog -sv fuse_mac.sv
|
||||
|
||||
design -save pristine
|
||||
|
||||
# 18x18 MAC
|
||||
design -load pristine
|
||||
hierarchy -top mac;
|
||||
synth_nexus -family lifcl -top mac
|
||||
select -assert-count 1 t:MULTADDSUB18X18
|
||||
select -assert-count 0 t:CCU2
|
||||
|
||||
# 18x18 pre-add MAC
|
||||
design -load pristine
|
||||
hierarchy -top madd_pre;
|
||||
synth_nexus -family lifcl -top madd_pre
|
||||
select -assert-count 1 t:MULTPREADD18X18
|
||||
|
||||
# 4-lane 9x9 dot product
|
||||
design -load pristine
|
||||
hierarchy -top dot4;
|
||||
synth_nexus -family lifcl -top dot4
|
||||
select -assert-count 1 t:MULTADDSUB9X9WIDE
|
||||
|
||||
# 24x24 MAC
|
||||
design -load pristine
|
||||
hierarchy -top neg_mac24;
|
||||
synth_nexus -family lifcl -top neg_mac24
|
||||
select -assert-count 0 t:MULTADDSUB18X18
|
||||
|
||||
# mixed
|
||||
design -load pristine
|
||||
hierarchy -top neg_dot_mixed;
|
||||
synth_nexus -family lifcl -top neg_dot_mixed
|
||||
select -assert-count 0 t:MULTADDSUB9X9WIDE
|
||||
select -assert-count 2 t:MULTADDSUB18X18
|
||||
Loading…
Reference in New Issue