Emil J. Tywoniak
49f45cf21f
abc_new: error handling when sketchy scripts are used
2026-09-30 12:19:21 +02:00
nella
57ab8ef2c6
Merge remote-tracking branch 'origin/main' into nella/latch-diagnostics-2
2026-09-22 16:49:41 +02:00
nella
d4f0028e7f
Merge pull request #6178 from YosysHQ/nella/muladd-reassoc
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canonicalize $macc unmapping for better DSP inference [sc-814]
2026-09-22 13:04:16 +00:00
nella
ec2b287c1e
Merge pull request #6150 from YosysHQ/nella/rm-unused-ports
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rmports: remove output ports unused by all instances [sc-799]
2026-09-22 13:01:17 +00:00
nella
90e281a964
Reject abc9 boxes without an input or an output.
2026-09-21 16:58:03 +02:00
nella
5726f981fa
Keep keep wires in abc.
2026-09-21 16:57:41 +02:00
nella
859b245eb5
Don't divide by zero with zero delays.
2026-09-21 16:57:41 +02:00
nella
e7dd15a4b8
Clear options per invocation.
2026-09-21 16:57:26 +02:00
Emil J
150c32b03e
Merge pull request #6154 from YosysHQ/emil/liberty-filter
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liberty: add filtering for things we need
2026-09-16 16:44:09 +00:00
Emil J. Tywoniak
91ac95c2b4
libparse: overwrite cache whenever old filter doesn't cover new filter
2026-09-16 18:21:46 +02:00
nella
5c338c559a
Reassociate sums of products via $macc.
2026-09-16 14:26:07 +02:00
nella
e2051bddb3
Revert.
2026-09-16 14:26:07 +02:00
nella
4ef51514f1
Add muladd rule.
2026-09-16 14:26:07 +02:00
nella
0edda7a3ab
Merge pull request #6201 from YosysHQ/nella/check-internal-celltypes
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check: reject unknown internal cell types [sc-915]
2026-09-15 11:52:15 +00:00
Lofty
d85872386a
Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16
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abc9: migrate to write_xaiger2
2026-09-14 16:25:07 +00:00
nella
76213a5d4c
Reject unknown internal cell types in check and hierarchy -check.
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A $-prefixed cell type must be a known cell type or a module in the
design. check reports it as a problem, hierarchy -check errors.
2026-09-14 13:50:09 +02:00
Emil J. Tywoniak and Jakub Michalski
72b30b1820
abc: dispatch modules in cell count order
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Co-authored-by: Jakub Michalski <[email protected]
2026-09-14 12:52:10 +02:00
nella
333d4b8bb0
rmports: only rely on top attr.
2026-09-14 10:21:17 +02:00
Emil J. Tywoniak
5a81ce51c0
fixup! abc: finish the submitted runs before propagating an error
2026-09-11 10:08:28 +02:00
Emil J. Tywoniak
bc92c9d9bf
abc: finish the submitted runs before propagating an error
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
5c6c0f66e3
abc: re-isolate autoidx churn
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
fa61f1732e
abc: clock domain parallelism is module parallelism
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
2a1c20dbbe
liberty: add filtering for things we need
2026-09-10 16:12:49 +02:00
Miodrag Milanović
ae86bbb130
Revert "Temporarily revert #6101 and #6077 "
2026-09-10 09:09:13 +02:00
Emil J
370a53acf8
Merge pull request #6169 from YosysHQ/emil/check-process-conflicts
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check: detect process-driver conflicts
2026-09-09 16:52:20 +00:00
Miodrag Milanović
f1442ce42e
Merge pull request #6182 from YosysHQ/lofty/revert-read_xaiger2
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Temporarily revert #6101 and #6077
2026-09-08 04:53:08 +00:00
Lofty
51583d854a
Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8"
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This reverts commit fd6367405e0f2bcb94b7
2026-09-07 17:29:08 +01:00
nella
7c26ff16c6
Merge pull request #6162 from YosysHQ/nella/scl-cache-dir
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liberty_cache: per user SCL cache directory [sc-843]
2026-09-07 14:52:21 +00:00
nella
dbef3ec8a5
Merge branch 'main' into nella/cell-rank
2026-09-04 16:06:21 -07:00
nella
cdf2832f47
Merge branch 'main' into nella/opt-dff-quadratics
2026-09-04 10:17:32 -07:00
nella
3be4154275
Sigmap single port bits in mux tree feedback search.
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find_muxtree_feedback_patterns sigmapped the whole A/B/S ports of every
visited $pmux, which is O(port width) per visited bit and makes wide mux
trees quadratic. Sigmap only the single bit that is needed, via a new
port_bit() helper, and factor the repeated Sx port writes into
break_feedback(). Output is unchanged.
2026-09-04 17:39:15 +02:00
Emil J
edb882e874
Merge pull request #6177 from YosysHQ/emil/abc-prepare-extract-sequence-determinism-2
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abc: isolate state mutation in prepare and extract for multi-threaded determinism
2026-09-04 13:09:37 +00:00
nella
82b95b2669
Use <=>.
2026-09-04 13:29:31 +02:00
Lofty
c53d452134
Revert "Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10"
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This reverts commit 621d943ac8598862f45b
2026-09-04 11:16:11 +01:00
Emil J. Tywoniak
e74a81c639
abc: cleanup
2026-09-04 12:01:35 +02:00
Emil J. Tywoniak
cdbf2948bb
abc: defer cell removal from prepare until extract for multi-threaded determinism
2026-09-04 11:38:26 +02:00
nella
c4b6c19580
Rank cells on tuple.
2026-09-04 11:16:24 +02:00
Emil J. Tywoniak
74ff7c407b
abc: per-clock-domain autoidx mechanism for multi-threaded determinism
2026-09-04 11:12:33 +02:00
Emil J. Tywoniak
4a51ae1f2c
abc: don't bump assign_map in extract
2026-09-04 10:37:35 +02:00
nella
ad5f80bf0d
Drop replaced box.
2026-09-03 14:16:31 +02:00
Emil J. Tywoniak
d8a4bf0c82
check: detect process-driver conflicts
2026-09-02 15:28:01 +02:00
Miodrag Milanović
28b7a17675
Merge pull request #6115 from YosysHQ/log-sink
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log rewrite [sc-748]
2026-09-02 13:03:29 +00:00
nella
9eb4619a30
Only remove if clear top module exists.
2026-09-01 05:46:35 -07:00
nella
dd51234178
Remove unused ports.
2026-09-01 05:46:35 -07:00
nella
9c2e1a8338
Add scl cache dir option.
2026-09-01 14:29:02 +02:00
Lofty
3f71c16f1b
punt xaiger2 -dff to another PR
2026-09-01 12:47:01 +01:00
Lofty
4c4d85e0d4
scratchpad option for xaiger1
2026-09-01 12:47:01 +01:00
Lofty
66b8e7e34a
no need to aigmap anymore
2026-09-01 12:47:01 +01:00
nella
9a86e65d80
Order carry ports last.
2026-09-01 12:47:01 +01:00
Lofty
184ff2d0de
abc9: migrate to write_xaiger2
2026-09-01 12:47:01 +01:00
Emil J. Tywoniak
nella
nella
Emil J
Lofty
Miodrag Milanović
Lofty