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1670 Commits
Author SHA1 Message Date
Emil J. Tywoniak 7a09c32040 signorm: disable passes that use rewrite_sigspecs 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak 6c048fdfb9 signorm: disable in passes that use swap_names 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak e6b7a50b30 techmap: disable signorm more 2026-09-17 14:13:57 +02:00
Emil J. Tywoniak e4b62727bd techmap: disable signorm 2026-09-17 14:13:57 +02:00
Jannis Harder 52ec5579fb WIP half broken snapshot 2026-09-17 14:12:36 +02:00
Miodrag Milanović f1442ce42e Merge pull request #6182 from YosysHQ/lofty/revert-read_xaiger2 
Temporarily revert #6101 and #6077
 2026-09-08 04:53:08 +00:00
Lofty 51583d854a Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8" 
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
 2026-09-07 17:29:08 +01:00
nella 7c26ff16c6 Merge pull request #6162 from YosysHQ/nella/scl-cache-dir 
liberty_cache: per user SCL cache directory [sc-843]
 2026-09-07 14:52:21 +00:00
nella dbef3ec8a5 Merge branch 'main' into nella/cell-rank 2026-09-04 16:06:21 -07:00
Emil J edb882e874 Merge pull request #6177 from YosysHQ/emil/abc-prepare-extract-sequence-determinism-2 
abc: isolate state mutation in prepare and extract for multi-threaded determinism
 2026-09-04 13:09:37 +00:00
nella 82b95b2669 Use <=>. 2026-09-04 13:29:31 +02:00
Lofty c53d452134 Revert "Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10" 
This reverts commit 621d943ac8, reversing
changes made to 598862f45b.
 2026-09-04 11:16:11 +01:00
Emil J. Tywoniak e74a81c639 abc: cleanup 2026-09-04 12:01:35 +02:00
Emil J. Tywoniak cdbf2948bb abc: defer cell removal from prepare until extract for multi-threaded determinism 2026-09-04 11:38:26 +02:00
nella c4b6c19580 Rank cells on tuple. 2026-09-04 11:16:24 +02:00
Emil J. Tywoniak 74ff7c407b abc: per-clock-domain autoidx mechanism for multi-threaded determinism 2026-09-04 11:12:33 +02:00
Emil J. Tywoniak 4a51ae1f2c abc: don't bump assign_map in extract 2026-09-04 10:37:35 +02:00
Miodrag Milanović 28b7a17675 Merge pull request #6115 from YosysHQ/log-sink 
log rewrite [sc-748]
 2026-09-02 13:03:29 +00:00
nella 9c2e1a8338 Add scl cache dir option. 2026-09-01 14:29:02 +02:00
Miodrag Milanovic 726aff678f log: remove log_ prefix and unified some namings 2026-08-31 11:20:21 +02:00
Emil J dd83bbad28 Merge pull request #6116 from antmicro/mgan/hdlname-fix 
Fix ignored `hdlname` attribute in `dfflibmap` pass
 2026-08-24 11:36:17 +00:00
Miodrag Milanović 2fd290ad47 Merge pull request #6134 from SimonEbner/main 
Retry read operations interrupted by EINTR
 2026-08-20 16:24:26 +00:00
Lofty be69f88e55 Merge pull request #6135 from YosysHQ/lofty/abc-refactor-13 
abc: remove -sop
 2026-08-20 09:34:26 +00:00
nella 59a3826bbd Merge pull request #6130 from DanielMBouyou/arith-tree-narrow-link 
arith_tree: do not flatten a chain link narrower than its consumer
 2026-08-20 08:40:25 +00:00
Miodrag Milanovic 2e113f5eff log: create LogManager singleton and move implementation 2026-08-19 15:59:46 +02:00
Lofty caceaaa2bb abc: remove -sop 2026-08-19 12:52:10 +01:00
Simon Bucher b98d7b6853 Gracefully handle EINTR during read. 
EINTR should be retried.
 2026-08-19 10:46:41 +00:00
Lofty edb411a622 synth_greenpak4, nlutmap: remove 2026-08-19 10:56:16 +01:00
Daniel M Bouyou e5c56c6400 arith_tree: do not flatten a chain link narrower than its consumer 
sole_chainable_consumer folded a cell into its consumer without ever
comparing widths. A link truncates its result at its own Y width, and that
truncation is invisible only when the consumer truncates at least as hard,
since (x % 2**link) % 2**parent == x % 2**parent holds only when
parent <= link. When the consumer is wider, the carry the link discards
becomes observable, and flattening the chain silently recovers it.

For

  module top(input [7:0] a, b, c, output [8:0] o);
    wire [7:0] t = a + b;
    assign o = t + c;
  endmodule

synth -arith_tree computes a + b + c where the design specifies
((a + b) % 256) + c. The two differ by 256 whenever a + b overflows,
for example at a=169 b=135 c=7.

alumacc already guards the structurally identical $macc merge using
macc_may_overflow(); arith_tree carried no equivalent check.

Add two cases to tests/arith_tree/arith_tree_equiv.ys: equiv_double_neg
widened to a 5 bit result, and a dedicated equiv_narrow_intermediate.
 2026-08-18 12:06:48 +02:00
nellaandMike Inouye 38b6e5e76c fix WASI, harden scl cache locking. 
Co-authored-by: Mike Inouye <[email protected]>
 2026-08-18 11:31:57 +02:00
Mike Inouye 977e55315d fix macOS build 
Signed-off-by: Mike Inouye <[email protected]>
 2026-08-17 22:05:09 +00:00
Mike Inouye 7c3becfbcd add file lock on liberty scl cache 
Signed-off-by: Mike Inouye <[email protected]>
 2026-08-17 21:18:34 +00:00
Lofty 621d943ac8 Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10 
read_xaiger2: remove
 2026-08-17 17:42:25 +00:00
nella 027677d43b Move scl cache args to libcache, fix -disable. 2026-08-17 12:37:49 +02:00
nella 5efa8187ad Add control over scl cache. 2026-08-17 10:49:45 +02:00
Emin b564fa2e71 liberty_cache: key SCL cache on ABC executable mtime and size 
The SCL format is written/read by ABC and can change between ABC builds,
so a cache entry created with a different ABC binary must not be reused.
 2026-08-15 23:16:31 +04:00
Mateusz Gancarz 1c1c56dfad dfflibmap: move all attributes to new cells 2026-08-13 15:56:43 +02:00
nella b8959e70ba Merge pull request #6072 from YosysHQ/nella/dlatchlibmap-cleanup 
Update to `dfflibmap` to be able to map LATCHes (clean up of #5976)
 2026-08-13 08:38:19 +00:00
Lofty 1dce7895e0 read_xaiger2: remove 2026-08-11 08:56:55 +01:00
Lofty fd6367405e Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8 
abc_ops_reintegrate: xaiger2 compatibility
 2026-08-10 13:14:40 +00:00
nella a03e5ec2ca Style fixups. 2026-08-10 10:59:03 +02:00
nellaandIztok Jeras e75e42c5d7 Pick first cell of smallest area. 
Co-authored-by: Iztok Jeras <[email protected]>
 2026-08-10 10:59:03 +02:00
nellaandIztok Jeras 011c3fc8c3 Add latch mapping. 
Co-authored-by: Iztok Jeras <[email protected]>
 2026-08-10 10:59:03 +02:00
nellaandIztok Jeras c590157cd3 Deduplicate FF cell finders. 
Co-authored-by: Iztok Jeras <[email protected]>
 2026-08-10 10:59:03 +02:00
Catherine 1277640bdf CMake: add missing dependency edges for synth_* passes. 2026-08-06 14:48:56 +00:00
Lofty 5e6fcf3b36 cleanup 2026-08-03 13:28:33 +01:00
Emil J. Tywoniak 89a5cbbaa6 abc_ops_reintegrate: xaiger2 compatibility 2026-08-03 12:34:01 +01:00
Lofty 6d9f5d1b0c wip 2026-08-03 12:34:01 +01:00
Krystine Sherwin 2f8cf84882 alumacc: cmp_mergeable function 
Replace all the existing mergeable checks with a call to a single function.
Fix remaining discrepencies (undersized output and mismatched signed inputs).
 2026-07-31 16:59:57 +12:00
Krystine SherwinandLofty bb49b0be32 alumacc: Fix get_lt for oversized output 
Current behavior uses the output width to determine the MSb(s), however this is not correct if the output is larger than the inputs (which doesn't happen when creating an `$alu` for a compare op, but does when folding a compare op into an arithmetic `$alu`).

Co-authored-by: Lofty <[email protected]>
 2026-07-31 16:59:56 +12:00