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2306 Commits

Author SHA1 Message Date
Stan Lee 48329bd36a change to string for consistency 2026-04-28 16:20:00 -07:00
Stan Lee 6f5b52807c whitespace 2026-04-28 16:18:36 -07:00
Stan Lee dd6e440937 rename and clean 2026-04-28 16:16:57 -07:00
Stan Lee e801ea4fdb delete module frontend 2026-04-28 15:12:50 -07:00
Akash Levy bf40364bd0 No operator optimization, but it passes all tests 2026-04-22 03:12:26 -07:00
Akash Levy 89d56882ba Pullup/pulldown primitives 2026-04-15 12:37:18 -07:00
Abhinav Tondapu 0f641f70b2 adding comments 2026-04-02 15:30:45 -07:00
Abhinav Tondapu 1f96d3209b [ENG-1842] adding file dump from verific 2026-04-02 09:54:26 -07:00
Abhinav Tondapu d5122ed2fa [ENG-1827] ignore placeholder/empty ports from verific 2026-03-27 15:20:12 -07:00
Akash Levy bf4ce9d6f7 Import uniquify fix 2026-02-19 00:24:32 -08:00
Akash Levy b7098e8383
Merge branch 'YosysHQ:main' into main 2026-02-18 09:44:25 -08:00
Emil J 33a2de9635
Merge pull request #5681 from YosysHQ/emil/blifparse-bounds-check 
blifparse: add bounds check
 2026-02-18 12:18:05 +01:00
Akash Levy 2b247d165b Merge from main 2026-02-13 04:14:08 -08:00
Gus Smith 12ace45b89 Support param. default values in JSON FE and SV BE 2026-02-11 08:10:55 -08:00
Emil J. Tywoniak 3f1fbfdaee blifparse: add bounds check 2026-02-11 12:16:02 +01:00
AdvaySingh1 8d22f6d7e1 Merged with main 2026-02-04 13:00:22 -08:00
Akash Levy 807df40422 Undo the weird abc changes 2026-02-03 23:21:48 -08:00
AdvaySingh1 0b96050933 Added tabbing in blifparse to match sorroundings 2026-02-03 08:44:16 -08:00
Akash Levy 8e5d24aa6b Bump yosys to latest 2026-02-03 06:08:36 -08:00
Sean Luchen 224549fb88 Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. 
Signed-off-by: Sean Luchen <seanluchen@google.com>
 2026-02-02 15:26:03 -08:00
AdvaySingh1 47469c2490 Added re-added gateinit logic previously deleted 2026-02-02 10:32:32 -08:00
AdvaySingh1 b005f69e27 Added comments in blifparse.cc 2026-02-02 10:15:59 -08:00
AdvaySingh1 b6c1d2fd27 Merge branch 'main' into nr_cleanup 2026-02-02 09:43:42 -08:00
Akash Levy 7c70026610 Fix verific issue 2026-02-01 00:16:10 -08:00
Akash Levy bdc9ad9f53 Bump version 2026-01-30 19:29:00 -08:00
Akash Levy 462caedc1c Merge fixups 2026-01-30 18:35:53 -08:00
AdvaySingh1 d7aca59e27 Updated abc.cc and blifparse.cc 2026-01-30 11:22:00 -08:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
Miodrag Milanovic b70f527c67 verific: fixed -sv2017 option and added ability to set VHDL standard if applicable 2026-01-29 10:32:30 +01:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Natalia 8d504ecb48 verific: use MFCU for SV file list 2026-01-29 00:03:28 -08:00
Natalia 188082551a verific: only use MFCU when VHDL present 2026-01-28 03:37:08 -08:00
Akash Levy 26f5ff3d74 Merge from upstream 2026-01-26 22:16:11 -08:00
Gus Smith 09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J 5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main 
Add gatesi_mode to init gates under gates_mode in BLIF format
 2026-01-26 23:30:11 +01:00
nataliakokoromyti f3c87610f5 verific: allow mixed SV/VHDL in -f files 2026-01-24 23:46:45 -08:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Miodrag Milanovic d0fa4781c6 verific: Fix -sv2017 message and formatting 2026-01-20 08:07:26 +01:00
Martin Povišer f67d4bcfa4 verilog: Do not set `module_not_derived` on internal cells 2026-01-19 16:48:13 -08:00
Miodrag Milanovic cc3038f468 verific: Fix -sv2017 message 2026-01-19 16:32:46 +01:00
Miodrag Milanovic d095d2c405 verific: add explicit System Verilog 2017 option 2026-01-16 07:56:53 +01:00
kamay e0077b188d Add gatesi_mode in BLIF format 2026-01-14 21:41:56 +01:00
Akash Levy a121255f47
Merge branch 'YosysHQ:main' into main 2026-01-13 11:28:34 -08:00
Emil J 71feb2a2a1
Merge pull request #5604 from YosysHQ/emil/read_verilog-remove-log 
read_verilog: remove log I left behind by accident
 2026-01-13 17:48:30 +00:00
Emil J. Tywoniak 83c1364eeb read_verilog: remove log I left behind by accident 2026-01-13 18:47:23 +01:00
Emil J 5ba0e9cae3
Merge pull request #4235 from ylm/genblk_wire 
Add autowires in genblk/for expension
 2026-01-13 16:40:22 +01:00
Akash Levy e332ba807d
Merge branch 'YosysHQ:main' into main 2026-01-07 12:40:39 -08:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Akash Levy 1941e8f042 Bump yosys and abc to latest 2025-12-25 03:46:16 -05:00
N. Engelhardt d5b38af4a7
Merge pull request #5550 from YosysHQ/nak/dont_merge_properties 2025-12-22 16:54:43 +01:00