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17596 Commits

Author SHA1 Message Date
Catherine 41a4b5a039
Merge pull request #6074 from YosysHQ/mmicko/fmt_update 
Updated vendored fmt to 12.2.1
 2026-08-01 11:47:36 +00:00
Miodrag Milanovic bb1c83b86e Updated vendored fmt to 12.2.1 2026-08-01 13:25:27 +02:00
nella ac59103097
Merge pull request #6045 from YosysHQ/emil/constparse-fix-error-crash 
const2ast: handle constant parsing from the command-line again
 2026-07-31 09:00:50 +00:00
nella 4baff94575 Add nesting test. 2026-07-31 10:31:44 +02:00
nella 250a467518 Attr file:line. 2026-07-31 10:31:44 +02:00
nella 2b5755178f Clean up diagnostics. 2026-07-31 10:31:44 +02:00
Emil J. Tywoniak dfa887637a const2ast: handle constant parsing from the command-line again 2026-07-31 10:31:44 +02:00
Krystine Dawn Sherwin 6c4d54a984
Merge pull request #6064 from YosysHQ/krys/alumacc_widths 
Fix merging comparisons with oversized unsigned subtraction in `alumacc`
 2026-07-31 06:03:08 +00:00
Krystine Sherwin bafaa2e95c
tests/alumacc: Use assert-max 2026-07-31 16:59:58 +12:00
Krystine Sherwin 9edae972af
tests/alumacc: Add broad merge test 
Mixes input cells, signedness, input width, output width.
Within the things that are `random.choice`, they *should* always be equivalent, but add a seed arg anyway just in case one day they're not.
 2026-07-31 16:59:58 +12:00
Krystine Sherwin 2f8cf84882
alumacc: cmp_mergeable function 
Replace all the existing mergeable checks with a call to a single function.
Fix remaining discrepencies (undersized output and mismatched signed inputs).
 2026-07-31 16:59:57 +12:00
Krystine Sherwin fb560a560f
tests/alumacc: Minor optimizations 2026-07-31 16:59:57 +12:00
Krystine Sherwin 1b9caf4f2c
tests/alumacc: Move opt/temp/alumacc 
Because apparently there's a whole `tests/alumacc` folder.
 2026-07-31 16:59:57 +12:00
Krystine Sherwin bb49b0be32
alumacc: Fix get_lt for oversized output 
Current behavior uses the output width to determine the MSb(s), however this is not correct if the output is larger than the inputs (which doesn't happen when creating an `$alu` for a compare op, but does when folding a compare op into an arithmetic `$alu`).

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2026-07-31 16:59:56 +12:00
Krystine Sherwin b49f321923
tests/opt: Add extra alumacc test 
Checks equivalence when folding an `$lt` (or equivalently a `$gt`) into a `$sub`.
Currently failing, fix incoming.
 2026-07-31 16:59:56 +12:00
Miodrag Milanović 9bc23d383f
Merge pull request #6070 from YosysHQ/update_abc 
Update ABC as per 2026-07-30
 2026-07-30 17:05:48 +00:00
Miodrag Milanović 5c15b0b5a1
Merge pull request #6071 from YosysHQ/mmicko/test_disable 
nexus: disable dsp test, takes very long
 2026-07-30 16:34:15 +00:00
Miodrag Milanovic 130e39b06d nexus: disable dsp test, takes very long 2026-07-30 17:46:25 +02:00
Emil J c03bbc3309
Merge pull request #6069 from YosysHQ/emil/liberty-flop-fix-polarity 
read_liberty: fix set&reset polarity
 2026-07-30 15:34:24 +00:00
Miodrag Milanovic c3b5607d05 Update ABC as per 2026-07-30 2026-07-30 17:02:50 +02:00
Emil J. Tywoniak 5f5f8b99b1 liberty: cleanup 2026-07-30 16:44:12 +02:00
nella 4821ed17b4
Merge pull request #5929 from YosysHQ/nella/fuse-2 
Add register absorption for MULT* for Nexus (fix #5917).
 2026-07-29 00:29:16 +00:00
nella c1377426c9
Merge branch 'main' into nella/fuse-2 2026-07-29 01:41:37 +02:00
Emil J. Tywoniak ef69127001 liberty: refactor out constant bools 2026-07-28 16:39:08 +02:00
Emil J 07a615a283
Merge pull request #6068 from YosysHQ/emil/aigmap-remove-unused-cache 
aigmap: remove unused and_cache
 2026-07-27 20:40:51 +00:00
Emil J. Tywoniak 82914a0204 dfflibmap: error on wide registers in design 2026-07-27 22:24:28 +02:00
Emil J. Tywoniak db2b3a22e9 liberty: remove optimization to simplify control flow, fixing polarities in set&reset behavior modeling 2026-07-27 22:09:57 +02:00
Emil J. Tywoniak c50290fdab dfflibmap: fix formal verilog test so that it actually maps all flops 2026-07-27 22:08:39 +02:00
Emil J. Tywoniak 1a1d9494da dfflibmap: check formal verilog test actually maps all flops 2026-07-27 22:06:22 +02:00
Emil J. Tywoniak 6585661740 aigmap: remove unused and_cache 2026-07-27 16:50:38 +02:00
Miodrag Milanović 2c28591b8e
Merge pull request #6067 from donn/force_static_ffi 
wheels: force static libffi in build
 2026-07-27 13:11:49 +00:00
Mohamed Gaber a216efad1c
wheels: force static libffi in build 
- only build static libffi
- improve resilience of cibw environment variables
 2026-07-27 15:40:23 +03:00
Emil J 5d2fbf8187
Merge pull request #5961 from YosysHQ/emil/opt_muxtree-fix-reconvergence 
opt_muxtree: fix reconvergence
 2026-07-27 09:08:13 +00:00
nella 511017acc1
Merge branch 'main' into nella/fuse-2 2026-07-24 12:20:35 +02:00
nella 526ab7aab3 Use Nexus DSP pipelined registers. 2026-07-24 12:10:07 +02:00
nella 5e59deecc3 Fix test desc. 2026-07-24 12:07:10 +02:00
nella 7defa51862
Merge pull request #6007 from YosysHQ/nella/fix-shift-fold 
Fix wide shift count folded as truncated/signed negative count
 2026-07-24 08:17:11 +00:00
Krystine Sherwin 29a6295d7c
tests/opt: Fix comments 2026-07-23 14:59:12 +12:00
Lofty 30fe16c7f1
Merge pull request #6061 from YosysHQ/lofty/remove-flowmap 
flowmap: remove
 2026-07-22 13:57:19 +00:00
Miodrag Milanović bc14cd7d18
Merge pull request #6062 from YosysHQ/mmicko/tests_only 
Add dependencies to gtests
 2026-07-22 13:39:05 +00:00
Miodrag Milanovic 5574994453 Add dependencies to gtests 2026-07-22 15:03:12 +02:00
Lofty f0b5225134 flowmap: remove 2026-07-22 13:50:33 +01:00
Lofty f9023e92b4
Merge pull request #6059 from drewbabel/fix-xilinx-srl-fdre-enable 
xilinx_srl: keep the clock enable on FDRE shift registers
 2026-07-22 10:33:29 +00:00
Lofty b914a7802e
Merge pull request #5782 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast (again)
 2026-07-21 09:26:10 +00:00
Lofty 45e1de36b4 abc: remove -fast (again) 2026-07-21 09:50:14 +01:00
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
 2026-07-20 23:59:40 -07:00
Miodrag Milanović e2c27aaafa
Merge pull request #6042 from YosysHQ/krys/symfpu 
Add `symfpu` pass
 2026-07-20 10:20:23 +00:00
Miodrag Milanovic cfd80cb48e Update constids to fix leaks 2026-07-20 11:53:55 +02:00
Miodrag Milanovic a7cfabd405 Fix gcc compile errors 2026-07-20 10:29:41 +02:00
Miodrag Milanović 3ce3196265
Merge pull request #6056 from YosysHQ/mmicko/ci_skip_update 
CI: back to using official action
 2026-07-20 07:08:47 +00:00