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2298 Commits

Author SHA1 Message Date
Miodrag Milanovic 8d2b63bb8a Set VHDL assert condition initial state if fed by FF 2024-10-11 16:32:21 +02:00
Akash Levy 48cb802599 Undo bound removal 2024-10-10 13:34:18 -07:00
Akash Levy fdc4c54c66
Merge branch 'YosysHQ:main' into main 2024-10-07 07:27:27 -10:00
Martin Povišer 0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay 
read_liberty: Optionally import unit delay arcs
 2024-10-07 16:11:51 +02:00
Martin Povišer 74e92d10e8
Merge pull request #4593 from povik/aiger2 
New aiger backend
 2024-10-07 16:11:25 +02:00
Martin Povišer 7989d53c58 read_xaiger2: Add help 2024-10-07 14:19:49 +02:00
Martin Povišer f44a418212 read_xaiger2: Add casts to silence warnings 2024-10-07 12:27:54 +02:00
Martin Povišer 8d12492610 read_xaiger2: Fix detecting the end of extensions 2024-10-07 12:03:48 +02:00
Martin Povišer 2b1b5652f1 Adjust `read_xaiger2` prints 2024-10-07 12:03:48 +02:00
Akash Levy f76cb43ac7 Add bundle support 2024-10-05 01:35:03 -10:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy 5038bfa2af Fix minor whitespace thing 2024-10-03 00:29:16 -07:00
Akash Levy ec296736f5 Simplify multiport 2024-10-02 22:19:09 -07:00
Akash Levy 400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy 8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Akash Levy ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy ee0b083a1e
Merge branch 'YosysHQ:main' into main 2024-09-30 02:43:09 -07:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Akash Levy 0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy 5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy 0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy 0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy 69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy 89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy 7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy 4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy 7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy 2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Martin Povišer f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer 1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer 4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
Akash Levy 44789c9f6c Move ram opt around 2024-09-16 18:56:48 -07:00
Akash Levy 285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Akash Levy 985de62d3c
Merge branch 'YosysHQ:main' into main 2024-09-11 16:01:37 -07:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Akash Levy ce95ec1f9e Add VHDL support via GHDL call 2024-09-05 13:24:38 -07:00
Akash Levy 57446f3f93
Merge branch 'YosysHQ:main' into master 2024-08-21 18:52:38 -07:00
Akash Levy 6e46a56720 Fix Verific warning 2024-08-21 16:55:44 -07:00
Roland Coeurjoly 27c1432253 Remove log 2024-08-21 14:28:42 +01:00
Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Akash Levy dba9a26cf3 Make default macros optional 2024-08-21 00:50:10 -07:00
Akash Levy 34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Martin Povišer ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer 309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Akash Levy 68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Miodrag Milanović 3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Miodrag Milanovic 405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
Akash Levy f790b75c19 Don't preserve user nets and update Verific tree balancing 2024-07-25 06:01:06 -07:00
Miodrag Milanovic 9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Akash Levy f1114cc98c Simplify ignores 2024-07-24 02:14:11 -07:00
Akash Levy ebc9f96f85
Merge branch 'YosysHQ:main' into master 2024-07-23 15:01:54 -07:00
Miodrag Milanovic c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00
Emil J. Tywoniak 72a0380da8 ast: don't suggest use in external projects 2024-07-18 16:37:14 +02:00
Akash Levy f18ddb5db2 Remove wide operator control 2024-07-10 12:53:59 -07:00
Akash Levy 8f4b66ae77 Set db_infer_wide_operators externally 2024-07-08 08:32:34 -07:00
Akash Levy 70016a08b8 Disable debug 2024-07-03 06:55:53 -07:00
Akash Levy 30241e07eb Fix segfault 2024-07-03 02:29:48 -07:00
Akash Levy fcd073ab51 Smallfix 2024-07-02 15:13:58 -07:00
Akash Levy 0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Akash Levy dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
gatecat 22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy 719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Akash Levy a0c0384683 Preserve instances 2024-06-16 20:20:10 -07:00
Akash Levy e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00
Akash Levy 2337d97977 Sub1 fix 2024-06-13 15:33:17 -07:00
Akash Levy ac0a9e7366 Updates 2024-06-10 20:52:11 -07:00
Akash Levy b9b776d211 Update for no preservation of user nets 2024-06-10 20:33:05 -07:00
Martin Povišer b593f5c01c Update the overview comment in `ast.h` 2024-06-10 16:38:39 +02:00
Akash Levy d930310599 Enable more updates 2024-06-09 13:54:34 -07:00
Mike Inouye b0ab1cf8c3 Fix memory leak in verific file parsing. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-06-07 22:51:28 +00:00
Akash Levy 8499d31cf2 Revert veri_break_loops setting 2024-06-07 00:09:01 -07:00
Akash Levy c8f7441a4a Fix skip default value 2024-06-05 09:33:03 -07:00
Akash Levy c59a997255 Ignore files properly 2024-06-05 07:53:21 -07:00
Akash Levy 4d44099d09 Support for ignoring translate_off and ignoring files 2024-06-05 05:00:05 -07:00
Akash Levy 5dc62bec0b Support .inc files and readmemh missing file 2024-06-03 20:05:30 -07:00
Akash Levy 92e44cc9a3 Minor fix to ignore files 2024-06-03 18:17:50 -07:00
Akash Levy 4339b3681a Elaborate top level modules undo 2024-06-03 16:17:51 -07:00
Akash Levy a692bf17d7 Improper ignore translates 2024-06-03 11:23:16 -07:00
Akash Levy 783c0a593a Actually optimize with Verific now 2024-06-03 04:55:47 -07:00
Akash Levy 4475b50ffa Undo some ugly stuff and make more attempted fixes 2024-06-02 23:33:23 -07:00
Akash Levy 2585636d18 Use ability to get/set IMPORT runtime flags 2024-06-02 22:24:29 -07:00
Akash Levy 28a03380b7 Priority selector fixes (opt order), relaxed checking, warning if using Yosys case statements 2024-06-02 18:45:31 -07:00
Akash Levy 85cbd05bb1 Update some runtime flags to fix some potential issues 2024-06-02 01:12:43 -07:00
Akash Levy 5bc23b272a Add blackboxes a little later and use ignore files rather than ignore modules 2024-05-30 14:17:10 -07:00
Akash Levy 8b93aa10cb Add leakage power unit support 2024-05-29 23:43:47 -07:00
Akash Levy a55a4d461e Infer wide operators pre elaboration (post does not work as well!) 2024-05-28 04:39:29 -07:00
Akash Levy 4062825a9e Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser 2024-05-28 01:47:46 -07:00
Akash Levy b90c20cd14 Update Verific, add opt to hierarchy pass, make opt run a bunch of Verific optimizations, update some Verific runtime flags 2024-05-27 21:56:08 -07:00
Akash Levy a98fcbd48b Revert Verific flags 2024-05-25 23:21:31 -07:00
Akash Levy 60ce37c2bd Don't reenable verific, move to c_cpp_properties.json in .vscode 2024-05-24 01:49:54 -07:00
Akash Levy 22bdf4035a Verific to handle all RAMs 2024-05-24 01:08:37 -07:00
Akash Levy 6300c491ea Update Yosys runtime flags for Verific to remove multi-port memory support 2024-05-24 00:26:37 -07:00
Akash Levy 66eabb1d2c Define SYNTH and OVL_SVA by default 2024-05-23 21:05:57 -07:00
Akash Levy 187737b86a Don't adjust naming on imported cells. Add $ for each pass 2024-05-19 15:02:40 -07:00
Akash Levy 60e598b9c8 Define SYNTHESIS earlier and in both, support ignored module specification 2024-05-17 04:46:28 -07:00
Akash Levy 375f73bbce Update for Amba support 2024-05-15 15:37:14 -07:00
Akash Levy ed42470d45 Move ignore translate up here and update verificc 2024-05-14 16:02:33 -07:00
Akash Levy 81b542fd31 Updated to support Amba comments and .h files 2024-05-14 13:25:43 -07:00
Akash Levy 667c3375e8 Macro defines don't pass or succeed the same way 2024-05-13 15:53:54 -07:00
Akash Levy fb182d10d6 Update formats to include .svh 2024-05-13 00:00:49 -07:00
Akash Levy ba5b12ae0c Don't include source in name 2024-05-11 23:14:39 -07:00
Akash Levy 36f9c50c03 Add mode for nested capital F file 2024-05-11 12:53:33 -07:00
Akash Levy a7e1dcef12 Move register file to after registering directories, also rename to AUTO-DISCOVER 2024-05-10 12:44:36 -07:00
Akash Levy fb55287a3b Add SVP extension, log auto-discovery, support gzip in verific 2024-05-10 11:09:22 -07:00
Akash Levy c7f66737aa Fix Yosys to allow SV again 2024-05-09 06:36:02 -07:00
Akash Levy da8c1955af Updates from YosysHQ 2024-05-09 05:10:44 -07:00
Akash Levy 8841cc4d76 Copy all info from .f file to hdl_file_sort for better auto-discovery 2024-05-09 04:54:57 -07:00
Akash Levy b5af9b9a8a Fix SystemVerilog support for .v files 2024-05-09 04:54:00 -07:00
Miodrag Milanović 1a54e8d47b
Merge pull request #4379 from QuantamHD/fix_verific 
frontend: Fixes verific import around range order
 2024-05-09 11:52:34 +02:00
Ethan Mahintorabi 82a4a87c97
Fixes error with vector indicies of the form [2:7] [-12:7] 
Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 20:29:47 +00:00
Akash Levy 47b6738124 Add -auto_discover to import 2024-05-08 04:21:30 -07:00
Akash Levy 2e21078a83
Merge branch 'YosysHQ:main' into master 2024-05-07 18:21:19 -07:00
Ethan Mahintorabi c039da2ec1
renames variables for more code clairty 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:09:52 +00:00
Ethan Mahintorabi a2c1b268d9
frontend: Fixes verific import around range order 
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:00:06 +00:00
Krystine Sherwin df95ea824b read_verilog: Add missing defaults for flags 
Fix for YosysHQ/sby#103
 2024-05-07 20:25:36 +02:00
Akash Levy 8c330c0e4b
Merge branch 'YosysHQ:main' into master 2024-04-29 22:22:47 -07:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
Akash Levy 45b723d6f3
Merge branch 'YosysHQ:main' into master 2024-04-25 06:24:57 -07:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Akash Levy 3945e6ecff
Merge branch 'YosysHQ:main' into master 2024-04-16 10:59:45 -07:00
Miodrag Milanovic af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
Akash Levy 6a3bb58d5d Updates from yosys 2024-04-14 18:53:44 -07:00
N. Engelhardt 3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019 
Verific support for VHDL 2019
 2024-04-09 18:25:05 +02:00
N. Engelhardt 18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params 
verific: Improve import VHDL constants
 2024-04-09 18:01:41 +02:00
Akash Levy 29e9d3ea92 Updates for hiding verific 2024-04-09 07:16:22 -07:00
akash 840cdb415b Update Verific, add to gitmodules, remove unused/GPL features from Makefile 2024-04-08 12:36:08 -07:00
Akash Levy e3f633fae6
Merge branch 'YosysHQ:main' into master 2024-04-08 12:26:40 -07:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`. 
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
 2024-04-02 12:13:22 +02:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Akash Levy dd35d2da23 Modifications 2024-03-21 11:31:43 -07:00
Miodrag Milanovic 4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
Miodrag Milanovic 9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Miodrag Milanovic 7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Martin Povišer b16f4900fd ast/simplify: Interpret hdlname w/o expecting backslash 2024-02-13 21:38:41 +01:00
Catherine d8ce26a5ba read_verilog: correctly format `hdlname` attribute value. 
The leading slash is not a part of the attribute as it only concerns
public values.
 2024-02-13 18:41:53 +00:00
Miodrag Milanovic ae7daf99f4 Verific: Add attributes to module instantiation 2024-02-12 09:53:47 +01:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem 03f35c3def Resolve multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem 88d9e213cb Decoding of a few more AST nodes in dumpVlog 2024-02-11 11:26:52 -05:00
Dag Lem 39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Catherine 1236bb65b6 read_verilog: don't include empty `opt_sva_label` in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00
Miodrag Milanović 5d3e4c5c7a
Merge pull request #4182 from QuantamHD/fix_aldff 
verific: Improves aldff inference in verific importer
 2024-02-06 08:19:43 +01:00
N. Engelhardt 2422dd6845
Merge pull request #4153 from Coloquinte/blif_delay_constraints 
Issue a warning instead of a syntax error for blif delay constraints
 2024-02-05 15:14:05 +01:00
Ethan Mahintorabi ff578ecabd
fix formatting 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:23:04 +00:00
Ethan Mahintorabi bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer 
The following SV module at HEAD imported with verific,

```systemverilog
    module my_module(
      input logic [4:0] a,
      input logic clk,
      input logic enable,
      output logic [4:0] z
    );

    reg [4:0] pipeline_register;
    always @(posedge clk) begin
      pipeline_register <= enable ? a : pipeline_register;
    end
    assign z = pipeline_register;

    endmodule : my_module

```

results in the following output verilog

```systemverilog
/* Generated by 0.36 */

(* top =  1  *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
  wire [4:0] _0_;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
  input [4:0] a;
  wire [4:0] a;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
  input clk;
  wire clk;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
  input enable;
  wire enable;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
  output [4:0] z;
  wire [4:0] z;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
  \$aldff  #(
    .ALOAD_POLARITY(32'd1),
    .CLK_POLARITY(32'd1),
    .WIDTH(32'd5)
  ) _1_ (
    .AD(5'hxx),
    .ALOAD(1'h0),
    .CLK(clk),
    .D(_0_),
    .Q(z)
  );
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
  \$mux  #(
    .WIDTH(32'd5)
  ) _2_ (
    .A(z),
    .B(a),
    .S(enable),
    .Y(_0_)
  );
endmodule
```

Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.

My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:10:25 +00:00
Catherine c7bf0e3b8f Add new `$check` cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
Miodrag Milanovic db1de5fe5d verific: add option to skip simplifying complex ports 2024-01-30 16:33:44 +01:00
Gabriel Gouvine c634d59c18 Issue a warning instead of a syntax error for blif delay constraints 2024-01-23 16:25:16 +00:00
Miodrag Milanovic 1764c0ee3c Fix verific clocking when no driver exist 2024-01-18 08:47:04 +01:00
Martin Povišer 149bcd88ad
Merge pull request #4026 from uis246/fix-format 
Fix printf formats
 2024-01-15 16:04:11 +01:00
uis 5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
Catherine 1159e48721 write_verilog: emit `initial $display` correctly. 2024-01-11 13:13:04 +01:00
Dag Lem 3ed9030eb4 Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00
Jannis Harder 510d137996 fmt: Allow non-constant $display calls in initial blocks 
These are useful for formal verification with SBY where they can be used
to display solver chosen `rand const reg` signals and signals derived
from those.

The previous error message for non-constant initial $display statements
is downgraded to a log message. Constant initial $display statements
will be shown both during elaboration and become part of the RTLIL so
that the `sim` output is complete.
 2024-01-11 13:01:28 +01:00
Dag Lem 23cd23efc5 Simplify and correct AST for array slice assignment 
Corrects sign extension of the right hand side, and hopefully
makes the code simpler to understand.

Fixes #4064
 2024-01-10 21:15:00 +01:00
Dag Lem 1a2b4759e8 Assign from rvalue via temporary register in nowrshmsk CASE 
Avoid repeating complex rvalue expressions for each condition.
 2024-01-10 20:40:01 +01:00
Dag Lem 2cab4ff173 Correction and optimization of nowrshmsk 
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.

Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.

Also uses less confusing variable names for indexing of lhs wires.
 2024-01-10 20:28:36 +01:00
Martin Povišer 6f7f71fe03 read_blif: Represent sequential elements with gate cells 
When reading the BLIF input, represent the native sequential elements
with fine-grained cells like `$_FF_` instead of the coarse-grained cells
like `$ff` which we were using up to now.

There are two reasons for this:

 * The sequential elements in BLIF are always single-bit, so the gate
   cells are a better fit.

 * This makes it symmetrical to the BLIF backend which only understands
   the fine-grained cells, and only translates those to the native BLIF
   features.
 2024-01-09 19:31:44 +01:00
Dag Lem 1bbea13f80 Correct hierarchical path names for structs and unions 2024-01-04 17:22:07 +01:00
Martin Povišer 320e75a3e3
Merge pull request #4065 from daglem/fix-AST_SHIFT-AST_SHIFTX 
Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX
 2023-12-12 11:47:29 +01:00
Dag Lem 655921e851 Uncloak array expressions generated by read_verilog -dump_vlog2 
Explicit conversion of AST_TO_SIGNED, AST_TO_UNSIGNED, and AST_CAST_SIZE
makes it possible to reason about simplified array expressions.
 2023-12-11 19:12:35 +01:00
Dag Lem cda470d63e Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX 
The $shift and $shiftx cells perform a left logical shift if the second
operand is negative. This change passes the sign of the second operand
of AST_SHIFT and AST_SHIFTX into $shift and $shiftx cells, respectively.
 2023-12-11 18:58:34 +01:00
Miodrag Milanovic 96fecf0716 Revert "Add attributes to module instantiation" 
This reverts commit 8f207eed1b.
 2023-12-04 16:37:01 +01:00
Miodrag Milanovic 8f207eed1b Add attributes to module instantiation 2023-11-23 11:01:49 +01:00
N. Engelhardt 5fb1264db5 verific: don't try to import attributes from nullptr 2023-11-14 15:05:24 +01:00
N. Engelhardt 93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr 
memory_libmap: look for ram_style attributes on surrounding signals
 2023-11-06 16:25:38 +01:00
Miodrag Milanovic f06d56d224 Handling non-existing location in verific logs 2023-11-03 08:06:16 +01:00
Miodrag Milanovic 4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
N. Engelhardt 833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
Miodrag Milanovic d473a207a1 Preserve VHDL architecture name in attribute 2023-10-12 09:17:06 +02:00
Jannis Harder 4ed708836a verific: Use CellBaseName to identify top modules 2023-10-10 11:51:16 +02:00
Martin Povišer 8367f06188 ast/simplify: Remove unused in_param code 2023-10-05 22:42:36 -04:00
Miodrag Milanović a54e6f2d1f
Merge pull request #3984 from YosysHQ/module_hdlname 
verific: save original module name
 2023-10-05 19:41:00 +02:00
Jannis Harder 47a4b790f8 verific: Pass top modules to static elaboration when using hierarchy 2023-10-05 16:51:49 +02:00
Jannis Harder 23b9e61c47 verific: Pass list of top modules to static elaboration 2023-10-05 16:51:49 +02:00
Miodrag Milanovic 268fe92d22 verific: save original module name 2023-10-05 11:22:40 +02:00
Jannis Harder 563a56d9ff verific: Improve interaction between -L, -work and bind statements 2023-10-03 15:52:01 +02:00
Jannis Harder cc843d414f simplify: Avoid calling fixup_hierarchy_flags on nullptr 
Compiling on GCC hid this bug as it optimized the nullptr call away as
undefined behavior, but running the SBY tests with a clang build hits
this error.
 2023-09-29 12:28:50 +02:00
Martin Povišer 20024900d9
Merge pull request #3813 from povik/ast-simplify-work-vol2 
ast/simplify: Remove in_lvalue/in_param simplify() parameters
 2023-09-28 11:57:58 +02:00
Miodrag Milanovic f193ebdded Verific: add default parameters to modules 2023-09-27 16:57:18 +02:00
Martin Povišer a511976b48 ast/simplify: Retire in_lvalue/in_param arguments to simplify 2023-09-26 13:32:15 +02:00
Martin Povišer 22b99413e8 ast/simplify: Make in_lvalue/in_param into props of AST nodes 
Instead of passing around in_lvalue/in_param flags to simplify, we make
the flags into properties of the AST nodes themselves. After the tree
is first parsed, we once do

  ast->fixup_hierarchy_flags(true)

to walk the full hierarchy and set the flags to their initial correct
values. Then as long as one is using ->clone(), ->cloneInto() and the
AstNode constructor (with children passed to it) to modify the tree, the
flags will be kept in sync automatically. On the other hand if we are
modifying the children list of an existing node, we may need to call

  node->fixup_hierarchy_flags()

to do a localized fixup. That fixup will update the flags on the node's
children, and will propagate the change down the tree if necessary.

clone() doesn't always retain the flags of the subtree being cloned. It
will produce a tree with a consistent setting of the flags, but the
root doesn't have in_param/in_lvalue set unless it's intrinsic to the
type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make
sure the cloned subtree has the flags consistent with the new placement
in a hierarchy.

Add asserts to make sure the old and new way of determining the flags
agree.
 2023-09-26 13:32:15 +02:00
Martin Povišer 10d0e69588 ast/simplify: Make tweaks in advance of big in_lvalue/in_param change 
The following commit will replace the way in_lvalue/in_param is being
tracked in the simplify code. Make tweaks in advance so that it will
be easier to make the old way and the new way agree.

These changes all should be innocuous.
 2023-09-26 13:31:59 +02:00
Martin Povišer 99a5773911
Merge pull request #3920 from zachjs/asgn-expr 
sv: support assignments within expressions
 2023-09-20 11:30:14 +02:00
Miodrag Milanovic 18855f23ce Set src attribute for verific with full info 2023-09-19 12:00:10 +02:00
Zachary Snow 28e99f2b8c fix width of post-increment/decrement expressions 2023-09-18 23:46:06 -04:00
Zachary Snow 7d07615dee allow attributes in front of ++/-- statements 2023-09-18 23:46:02 -04:00
Jannis Harder 0e8a4adb59 verific: Update YOSYSHQ_VERIFIC_API_VERSION 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 9c255c98b1 unescape string tag attribute 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 7b134c2a8c verific - respect order of read and write for rams 2023-09-12 11:56:15 +02:00
Zachary Snow 4edb1a1921 sv: support assignments within expressions 
- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.
 2023-09-05 22:27:55 -04:00
Martin Povišer 2d0fc040cf ast: Substitute rvalues when parsing out print arguments 
Apply the local substitutions stemming from process context when parsing
out format arguments to `$display` or other statements.
 2023-09-05 21:40:39 +02:00
Charlotte f9d38253c5 ast: add `PRIORITY` to `$print` cells 2023-08-11 04:46:52 +02:00
Charlotte 992a728ec7 tests: CXX may be e.g. gcc, so use CC and link stdc++ explicitly 2023-08-11 04:46:52 +02:00
Charlotte 9f9561379b fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
Charlotte c382d7d3ac fmt: %t/$time support 2023-08-11 04:46:52 +02:00
whitequark d5c9953c09 ast: translate $display/$write tasks in always blocks to new $print cell. 2023-08-11 04:46:52 +02:00
whitequark 9f8e039a4b ast: use new format string helpers. 2023-08-11 04:46:52 +02:00
whitequark f8e2c955fc read_verilog: set location of AST_TCALL. 
Useful for error reporting of $display() arguments, etc.
 2023-08-11 04:46:52 +02:00
Miodrag Milanovic 19d5293657 when blackboxing no need to know missing modules 2023-07-31 09:18:54 +02:00
Miodrag Milanovic 372760af57 spaces to tabs 2023-07-25 09:40:30 +02:00
Miodrag Milanovic 3989181cd6 Add ability to blackbox modules/units from file while reading with verific 2023-07-25 09:40:30 +02:00
Zachary Snow d5d2bf815a Fix semantic merge conflict in previous two merged PRs 2023-07-21 00:08:10 -04:00
Martin Povišer 72a4022a10 ast/simplify: Retire 'at_zero' flag 
Now that all the callsites pass in 'false' for the flag (or propagate
the flag on recursion), we can retire it.
 2023-07-20 23:40:19 -04:00
Martin Povišer 4fceeb3b32 ast/simplify: Use clone_at_zero() for "at_zero" evaluations 
The correct way of using the 'at_zero' regime of simplify is to perform
the simplification on a cloned AST subtree, otherwise the "at_zero"
evaluation seeps into the main tree.

Move the effect of the 'at_zero' flag to the cloning itself, so that
the simplify flag can be retired. We assume we can rely on id2ast in
the new clone method.
 2023-07-20 23:40:19 -04:00
Martin Povišer 77d4b5230e ast: Move to a new helper method to print input errors 
It's a repeating pattern to print an error message tied to an AST
node. Start using an 'input_error' helper for that. Among other
things this is beneficial in shortening the print lines, which tend
to be long.
 2023-07-20 23:40:19 -04:00
Martin Povišer 1ac1b2eed5 ast/simplify: Factor out helper to determine range width 2023-07-20 23:40:19 -04:00
Dag Lem cff53d6d87 Corrected handling of nested typedefs of struct/union 
This also corrects shadowing of constants in struct/union types.
 2023-07-20 23:39:44 -04:00
N. Engelhardt 21686f0d9d verific: import src attribute on $memrd/$memwr cells 2023-06-23 19:41:36 +02:00
Miodrag Milanovic aff0065646 Use defaultvalue for init values of input ports 2023-06-21 13:21:34 +02:00
Miodrag Milanovic 75cf79588e Add ability for user plugin to add new verific log callback 2023-06-12 10:01:01 +02:00
Miodrag Milanovic ecd289c100 Fix importing parametrized VHDL entity 2023-05-23 08:25:08 +02:00
Kamil Rakoczy 6b3e6d96a3 Fix missing brackets around else 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2023-05-10 08:09:11 +02:00
N. Engelhardt 0aeb6105eb
Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx 2023-05-08 16:15:13 +02:00
Dag Lem ad437c178d Handling of attributes for struct / union variables 
(* nowrshmsk *) on a struct / union variable now affects dynamic
bit slice assignments to members of the struct / union.

(* nowrshmsk *) can in some cases yield significant resource savings; the
combination of pipeline shifting and indexed writes is an example of this.

Constructs similar to the one below can benefit from (* nowrshmsk *), and
in addition it is no longer necessary to split out the shift assignments
on separate lines in order to avoid the error message "ERROR: incompatible
mix of lookahead and non-lookahead IDs in LHS expression."

    always_ff @(posedge clk) begin
        if (rotate) begin
            { v5, v4, v3, v2, v1, v0 } <= { v4, v3, v2, v1, v0, v5 };

            if (res) begin
                v0.bytes <= '0;
            end else if (w) begin
                v0.bytes[addr] <= data;
            end
        end
    end
 2023-05-03 18:44:07 +02:00
Jannis Harder 3cbca5064c verific: Handle non-seq properties with VerificClocking conditions 2023-04-21 17:19:42 +02:00
Jannis Harder ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking 
This handles conditions on clocked concurrent assertions in unclocked
procedural contexts.
 2023-04-21 16:51:42 +02:00
Jannis Harder 985f4926b7 verilog: Fix const eval of unbased unsized constants 
When the verilog frontend perfomed constant evaluation of unbased
unsized constants in a context-determined expression it did not properly
extend them by repeating the bit value. This only affected constant
evaluation and not constants that made it through unchanged to RTLIL.
The latter case was already covered by tests and working before.

This fixes the const-eval issue by checking the `is_unsized` flag in
bitsAsConst and extending the value accordingly.

The newly added test also tests the already working non-const-eval case
to highlight that both cases should behave the same.
 2023-04-20 12:12:50 +02:00
Jannis Harder fb1c2be76b verilog: Support void functions 
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
 2023-03-20 12:52:46 +01:00
Jannis Harder 390d1c583a verific: Fix enum_values support and signed attribute values 
This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
 2023-03-15 09:51:36 +01:00
Jannis Harder c50f641812
Merge pull request #3682 from daglem/struct-member-out-of-bounds 
Out of bounds checking for struct/union members
 2023-03-10 16:14:56 +01:00
Dag Lem 0d3423ddea Index struct/union members within corresponding wire chunks 
This guards against access to bits outside of struct/union
members via dynamic indexing.
 2023-03-05 14:54:17 +01:00
Miodrag Milanovic a30894e5fa Handle more wide case selector types 2023-02-27 09:24:04 +01:00
Dag Lem 79043cb849 Out of bounds checking for struct/union members 
Currently, only constant indices are checked.
 2023-02-19 23:25:08 +01:00
Dag Lem c1e12877f0 Support for data and array queries on struct/union item expressions 
For now, $bits, $left, $right, $low, $high, and $size are supported.
 2023-02-15 11:44:24 +01:00
Jannis Harder 53bda9de54
Merge pull request #3661 from daglem/struct-array-range-offset 
Handle range offsets in packed arrays within packed structs
 2023-02-15 11:21:56 +01:00
Dag Lem 615adc4253
Resolve package types in interfaces (#3658) 
* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
 2023-02-12 18:25:39 -05:00
Miodrag Milanovic 109b88c379 For case select values use Sa instead of Sx and Sz 2023-02-08 09:22:48 +01:00
Miodrag Milanovic e7e37df91b Add verific import support for OPER_WIDE_CASE_SELECT_BOX 2023-02-06 09:28:23 +01:00
Dag Lem 777c589e85 Handle range offsets in packed arrays within packed structs 
This brings the metadata for packed arrays in packed structs
in line with the metadata for unpacked arrays, and correctly
handles the case when both lsb and msb in an address range are
non-zero.
 2023-02-05 17:09:51 +01:00
Dag Lem 26db5a11d3 Resolve struct member package types 2023-01-29 13:51:44 -05:00
Dag Lem db13c6df2b
Handle struct members of union type (#3641) 2023-01-29 13:45:45 -05:00
Miodrag Milanovic 6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
N. Engelhardt 692a0fa33b print filename in liberty log_header 2023-01-11 21:31:46 +01:00
Jannis Harder 3ebc50dee4
Merge pull request #3467 from jix/fix_cellarray_simplify 
simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
 2022-12-19 16:05:13 +01:00
Miodrag Milanovic b867dee241 respect noblackbox attribute in verific 2022-12-15 08:17:53 +01:00
Jannis Harder 7ad7b550cb
Merge pull request #3573 from daglem/struct-array-multidimensional 
Support for packed multidimensional arrays within packed structs
 2022-12-07 19:24:12 +01:00
Jannis Harder dd8b412833 simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY 
Otherwise the AST_CELL simplification uses the wrong celltype before the
AST_CELLARRAY simplification has a chance to unroll it and change it to
the $array celltype.
 2022-12-07 18:21:36 +01:00
Miodrag Milanović 9362fdb4c6
Merge pull request #3568 from YosysHQ/verific_msg 
Set all Verific messages of certain type to other
 2022-12-05 16:22:44 +01:00
Miodrag Milanović 26aaf7683f
Merge pull request #3569 from YosysHQ/ver_no_rewriters 
verific: Ignore errors produced by extension
 2022-12-05 16:21:12 +01:00
Dag Lem 22090011ab Made make_struct_member_range side-effect-free again 2022-12-04 06:54:22 +01:00
Dag Lem f94eec952f Support for packed multidimensional arrays within packed structs 2022-12-03 19:54:47 +01:00
Miodrag Milanovic 34a64aa322 set VERI-1063 explicitly 2022-12-02 17:11:17 +01:00
Jannis Harder 4a2b7287ca
Merge pull request #3551 from daglem/struct-array-swapped-range 
Support for arrays with swapped ranges within structs
 2022-12-01 00:58:32 +01:00
Dag Lem 64f88eb7f1 Added asserts for current limitation of array dimensions in packed structs 2022-11-30 23:32:41 +01:00
Dag Lem 15c8e74329 Check for all cases of currently unsupported array dimensions in packed structs 2022-11-30 20:04:45 +01:00
Miodrag Milanovic 2dd55d73a0 reset elaboration error after rewriter 2022-11-30 17:26:48 +01:00
Miodrag Milanovic bfd79845b6 Set all verific messages of certain type to other 2022-11-30 16:42:37 +01:00
Miodrag Milanovic f764cd1655 update documentation 2022-11-25 14:27:30 +01:00
Miodrag Milanovic b0be19c126 Support importing verilog configurations using Verific 2022-11-25 13:02:11 +01:00
Dag Lem ddb12148e7 Support for swapped ranges in second array dimension 2022-11-23 16:31:08 +01:00
Jannis Harder fc2f622a27
Merge pull request #3552 from daglem/fix-sv-c-array-dimensions 
Correct interpretation of SystemVerilog C-style array dimensions
 2022-11-23 15:12:17 +01:00
Jannis Harder 239ecf9185 Merge branch 'zachjs-master' 2022-11-21 17:47:43 +01:00
Dag Lem a862642fac Correct interpretation of SystemVerilog C-style array dimensions 
IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
 2022-11-13 07:41:25 +01:00
Dag Lem bab88630c2 Support for arrays with swapped ranges within structs 
This also corrects the implementation of C type arrays within structs.

Fixes #3550
 2022-11-12 08:48:25 +01:00
Miodrag Milanovic 59b6ac47c9 Add additional help info 2022-10-31 18:04:34 +01:00
Miodrag Milanovic 6fb80bce15 Enable importing blackbox modules only 2022-10-31 10:51:28 +01:00
Miodrag Milanovic e702f2894a Support for reading liberty files using verific 2022-10-31 10:15:05 +01:00
Zachary Snow 71e7e09092 verilog: Support module-scoped task/function calls 
This is primarily intended to enable the standard-permitted use of
module-scoped identifiers to refer to tasks and non-constant functions.
As a side-effect, this also adds support for the non-standard use of
module-scoped identifiers referring to constant functions, a feature
that is supported in some other tools, including Iverilog.
 2022-10-29 15:14:11 -04:00
Miodrag Milanovic 48628fbf5a Skip verific primitives and operators import by default 2022-10-14 17:41:24 +02:00
Miodrag Milanovic 922f8b614a Add option to import all cells from all libraries 2022-10-14 16:54:57 +02:00
Miodrag Milanovic 03df1ac72b fix whitespace 2022-10-10 16:31:29 +02:00
Miodrag Milanović e8ce9442a6
Merge pull request #3452 from ALGCDG/master 
Add BLIF names command input plane size check
 2022-10-10 16:29:27 +02:00
Claire Xenia Wolf 090228a6a1 Fix handling of verific -L options, add implicit "-L work" 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-10-10 00:47:42 +02:00
Miodrag Milanovic 1a6f10e8ba Add support for EDIF file reading using Verific 2022-10-04 09:18:44 +02:00
Archie d29606532a Changing error reason string to be based on lut input plane limit constant. 2022-10-02 22:05:51 +02:00
Miodrag Milanovic 43267dec99 support file content redirection for verific frontened 2022-09-28 15:56:46 +02:00
Miodrag Milanovic b45517f7b7 Add comment for future self 2022-09-28 14:45:39 +02:00
Miodrag Milanovic f54ac8a6d6 Handle attributes imported from verific 2022-09-28 08:51:26 +02:00
Miodrag Milanovic 8fb498744f Import memory attributes 2022-09-21 15:48:40 +02:00
Miodrag Milanovic 3f94f9313a verific: better fix for read callback 2022-09-07 09:48:19 +02:00
Miodrag Milanovic 06a9c7499a verific: fix crash when using prep right after read 2022-09-07 09:40:14 +02:00
KrystalDelusion 9465b2af95 Fitting help messages to 80 character width 
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
 2022-08-24 10:40:57 +12:00
Archie 15a0697c70 Adding check for BLIF names command input plane size. 2022-08-21 23:18:20 -05:00
Miodrag Milanovic b76c72056b set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
Miodrag Milanovic 545a3417c8 resetall does not affect text defines, but undefineall does 2022-08-10 11:38:50 +02:00
Miodrag Milanovic 6c65ca4e50 Encode filename unprintable chars 2022-08-08 16:13:33 +02:00
Miodrag Milanovic 2b1aeb44d9 verific - make filepath handling compatible with verilog frontend 2022-08-08 11:57:28 +02:00
Miodrag Milanović 15393442d6
Merge pull request #3089 from YosysHQ/gatecat/liberty_wb 
Add read_liberty -wb
 2022-08-01 17:08:04 +02:00
Miodrag Milanovic 52a4a89265 Setting wire upto in verific import 2022-07-29 17:10:31 +02:00
Miodrag Milanović d19f9d0b66
Update README 2022-07-28 12:32:19 +02:00
Miodrag Milanovic 59b96bb1f8 Upadte documentation and changelog 2022-07-04 11:09:06 +02:00
Miodrag Milanovic b80976b543 Update to new verific extensions inteface 2022-06-30 11:19:01 +02:00
Archie 7eeb656e2a Add check for BLIF with no model name 2022-06-22 00:34:49 +01:00
Miodrag Milanovic 1fdbb42fdd Revert "use new verific extensions library" 
This reverts commit 607e957657.
 2022-06-21 18:07:47 +02:00
Miodrag Milanovic 607e957657 use new verific extensions library 2022-06-17 16:04:22 +02:00
Miodrag Milanovic ddc8044655 removed deprecated features code 2022-06-13 10:50:24 +02:00
Miodrag Milanovic 6e8e4b4550 verific: Added "-vlog-libext" option to specify search extension for libraries 2022-06-09 08:57:48 +02:00
Miodrag Milanovic e35a166353 verific: proper file location for readmem commands 2022-06-04 08:39:50 +02:00
Zachary Snow a650d9079f verilog: fix width/sign detection for functions 2022-05-30 16:45:39 -04:00
Jannis Harder 4bfaaea0d5 verilog: fix size and signedness of array querying functions 
genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.

Includes tests for the the relvant edge cases for context dependent
conversions.
 2022-05-30 09:11:31 -04:00
Jannis Harder b75fa62e9b verilog: fix $past's signedness 2022-05-25 16:32:08 -04:00
Jannis Harder cffec1f95f verilog: fix signedness when removing unreachable cases 2022-05-24 23:03:31 -04:00
Miodrag Milanovic fdb393b6ce fix text to fit 80 columns 2022-05-23 19:57:21 +02:00
Miodrag Milanovic 4a5790d404 Update verific command file documentation 2022-05-23 19:35:14 +02:00
Miodrag Milanovic a6ec5754c6 Use analysis mode if set in file 2022-05-23 19:13:45 +02:00
Jannis Harder fada77b8cf verific: Use new value change logic also for $stable of wide signals. 
I missed this in the previous PR.
 2022-05-11 13:05:27 +02:00
Jannis Harder 587e09d551
Merge pull request #3305 from jix/sva_value_change_logic 
verific: Improve logic generated for SVA value change expressions
 2022-05-09 16:40:34 +02:00
Jannis Harder a855d62b42 verific: Improve logic generated for SVA value change expressions 
The previously generated logic assumed an unconstrained past value in
the initial state and did not handle 'x values. While the current formal
verification flow uses 2-valued logic, SVA value change expressions
require a past value of 'x during the initial state to behave in the
expected way (i.e. to consider both an initial 0 and an initial 1 as
$changed and an initial 1 as $rose and an initial 0 as $fell).

This patch now generates logic that at the same time

	a) provides the expected behavior in a 2-valued logic setting, not
	   depending on any dont-care optimizations, and

	b) properly handles 'x values in yosys simulation
 2022-05-09 15:04:01 +02:00
Jannis Harder 96f64f4788 verific: Fix conditions of SVAs with explicit clocks within procedures 
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
 2022-05-03 14:13:08 +02:00
Miodrag Milanovic 422db937d4 Ignore merging past ffs that we are not properly merging 2022-04-29 14:35:02 +02:00
Miodrag Milanovic 1cc281ca6f verific: allow memories to be inferred in loops (vhdl) 2022-04-18 09:10:28 +02:00
N. Engelhardt 57bc29c64a verific: allow memories to be inferred in loops 2022-04-15 15:10:48 +02:00
Zachary Snow bf15dbd0f7 sv: fix always_comb auto nosync for nested and function blocks 2022-04-05 14:43:48 -06:00
Miodrag Milanovic 1a1f529099 Preserve internal wires for external nets 2022-04-01 12:07:15 +02:00
Miodrag Milanovic bbf65702a1 Fix valgrind tests when using verific 2022-03-30 17:25:53 +02:00
Miodrag Milanovic 703769e494 Properly mark modules imported 2022-03-26 09:43:51 +01:00
Miodrag Milanovic 245ecb0529 Import verific netlist in consistent order 2022-03-25 13:44:16 +01:00
Miodrag Milanović 13655ddccf
Merge pull request #3206 from YosysHQ/micko/quote_remove 
Remove quotes if any from attribute
 2022-03-04 16:39:01 +01:00
N. Engelhardt 8fd1b06249 fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
Miodrag Milanovic 29293a57bb Remove quotes if any from attribute 2022-02-16 19:10:13 +01:00
Zachary Snow 15a4e900b2 verilog: support for time scale delay values 2022-02-14 15:58:31 +01:00
Kamil Rakoczy 68c67c40ec
Fix access to whole sub-structs (#3086) 
* Add support for accessing whole struct
* Update tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-02-14 14:34:20 +01:00
Zachary Snow 15eb66b99d verilog: fix dynamic dynamic range asgn elab 2022-02-11 22:54:55 +01:00
Zachary Snow 90bb47d181 verilog: fix const func eval with upto variables 2022-02-11 21:01:51 +01:00
Miodrag Milanović fc7d78f071
Merge pull request #3164 from zachjs/fix-ast-warn 
fix dumpAst() compilation warning
 2022-02-11 16:43:35 +01:00
Miodrag Milanovic 2cef48bf2c Add ability to override verilog mode for verific -f command 2022-02-09 09:19:25 +01:00
Miodrag Milanovic 0b633b6c2e Use bmux for NTO1MUX 2022-02-02 16:16:08 +01:00
Zachary Snow 342927732e fix dumpAst() compilation warning 2022-01-18 00:17:08 -07:00
Zachary Snow aa35f24290 sv: auto add nosync to certain always_comb local vars 
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
 2022-01-07 22:53:22 -07:00
Zachary Snow 828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
Zachary Snow 8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Zachary Snow 7608985d2c fix width detection of array querying function in case and case item expressions 
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
 2021-12-17 21:22:08 -07:00
Thomas Sailer 4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers 
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
 2021-12-15 18:06:02 -07:00
Claire Xenia Wolf 313340aed5 Add YOSYS to the implicitly defined verilog macros in verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-13 18:20:08 +01:00
Miodrag Milanović 2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz 
Fix verific import of enum values with x and/or z
 2021-12-10 19:36:37 +01:00
Claire Xenia Wolf 2da214d721 Fix verific import of enum values with x and/or z 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 14:52:27 +01:00
Claire Xen 19773d093f
Update verific.cc 
Ad-hoc fixes/improvements
 2021-12-10 14:27:18 +01:00
Miodrag Milanovic b06f547993 If direction NONE use that from first bit 2021-12-08 11:50:10 +01:00
Miodrag Milanovic 3ebfa3fb84 Make sure cell names are unique for wide operators 2021-12-03 09:49:05 +01:00
gatecat b506f398dd Add read_liberty -wb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-11-25 19:13:08 +00:00
Kamil Rakoczy fdb19a5b3a
Support parameters using struct as a wiretype (#3050) 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-11-16 10:59:54 +01:00
Miodrag Milanovic 15a35f5584 No need to alocate more memory than used 2021-11-10 10:50:44 +01:00
Kamil Rakoczy f4f5acf396 genrtlil: Fix displaying debug info in packages 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-11-10 01:31:39 +01:00
Claire Xenia Wolf 2ea757da51 Add "verific -cfg" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-11-01 10:41:51 +01:00
Claire Xenia Wolf 83118bfb9e Fix verific gclk handling for async-load FFs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-31 17:12:29 +01:00
Miodrag Milanovic f7cc388bb5 Enable async load dff emit by default in Verific 2021-10-27 15:56:56 +02:00
Miodrag Milanovic 32673edfea Revert "Compile option for enabling async load verific support" 
This reverts commit b8624ad2ae.
 2021-10-27 15:55:43 +02:00
Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections 
- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change
 2021-10-25 18:25:50 -07:00
Rupert Swarbrick bd16d01c0e Split out logic for reprocessing an AstModule 
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
 2021-10-25 18:25:50 -07:00
Miodrag Milanovic b8624ad2ae Compile option for enabling async load verific support 2021-10-25 09:04:43 +02:00
Claire Xenia Wolf 90b440f870 Fix verific.cc PRIM_DLATCH handling 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-21 12:13:35 +02:00
Claire Xenia Wolf 16a177560f Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-21 05:42:47 +02:00
Miodrag Milanovic 17269ae59b Option to disable verific VHDL support 2021-10-20 10:02:58 +02:00
Miodrag Milanovic 1aa6896966 Support PRIM_BUFIF1 primitive 2021-10-14 13:04:32 +02:00
Claire Xen 2d3c79458d
Merge pull request #3039 from YosysHQ/claire/verific_aldff 
Add support for $aldff flip-flops to verific importer
 2021-10-11 10:01:56 +02:00
Claire Xenia Wolf c8074769b0 Add Verific adffe/dffsre/aldffe FIXMEs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-11 10:00:20 +02:00
Miodrag Milanovic 93fbc9fba4 Import module attributes from Verific 2021-10-10 10:01:45 +02:00
Claire Xenia Wolf 34f1df8435 Fixes and add comments for open FIXME items 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 17:24:45 +02:00
Claire Xenia Wolf 1602a03864 Add support for $aldff flip-flops to verific importer 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-10-08 16:21:25 +02:00
Miodrag Milanovic abc5700628 verific set db_infer_set_reset_registers 2021-10-04 16:48:33 +02:00
Zachary Snow fbd70f28f0 Specify minimum bison version 3.0+ 
Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous
release). Ideally, we would require "3" rather than "3.0" to give a
better error message, but bison 2.3, which still ships with macOS, does
not support major-only version requirements. With this change, building
with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14:
require bison 3.0, but have 2.3`.
 2021-10-01 21:18:33 -06:00
Claire Xen 0146d83ed8
Merge pull request #3014 from YosysHQ/claire/fix-vgtest 
Fix "make vgtest"
 2021-09-24 17:50:34 +02:00
Zachary Snow 9658d2e337 Fix TOK_ID memory leak in for_initialization 2021-09-23 13:33:55 -04:00
Zachary Snow d6fe6d4fb6 sv: support wand and wor of data types 
This enables the usage of declarations of wand or wor with a base type
of logic, integer, or a typename. Note that declarations of nets with
2-state base types is still permitted, in violation of the spec.
 2021-09-21 14:52:28 -04:00
Zachary Snow 6b7267b849 verilog: fix multiple AST_PREFIX scope resolution issues 
- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
 2021-09-21 12:10:59 -04:00
Marcelina Kościelnicka 551ef85cd7 verilog: Squash flex-triggered warning. 2021-09-13 18:58:17 +02:00
Miodrag Milanovic c3d4bb4cc9 update required verific version 2021-09-02 14:59:16 +02:00
Zachary Snow b2e9717419 sv: support declaration in generate for initialization 
This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
 2021-08-31 12:34:55 -06:00
Zachary Snow f0a52e3dd2 sv: support declaration in procedural for initialization 
In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
 2021-08-30 15:19:21 -06:00
Miodrag Milanovic b59c427348 Make Verific extensions optional 2021-08-20 10:19:04 +02:00
Rupert Swarbrick ee2b5b7ed1 Generate an RTLIL representation of bind constructs 
This code now takes the AST nodes of type AST_BIND and generates a
representation in the RTLIL for them.

This is a little tricky, because a binding of the form:

    bind baz foo_t foo_i (.arg (1 + bar));

means "make an instance of foo_t called foo_i, instantiate it inside
baz and connect the port arg to the result of the expression 1+bar".
Of course, 1+bar needs a cell for the addition. Where should that cell
live?

With this patch, the Binding structure that represents the construct
is itself an AST::AstModule module. This lets us put the adder cell
inside it. We'll pull the contents out and plonk them into 'baz' when
we actually do the binding operation as part of the hierarchy pass.

Of course, we don't want RTLIL::Binding to contain an
AST::AstModule (since kernel code shouldn't depend on a frontend), so
we define RTLIL::Binding as an abstract base class and put the
AST-specific code into an AST::Binding subclass. This is analogous to
the AST::AstModule class.
 2021-08-13 17:11:35 -06:00
Brett Witherspoon 979053855c sv: improve support for wire and var with user-defined types 
- User-defined types must be data types. Using a net type (e.g. wire) is
  a syntax error.
- User-defined types without a net type are always variables (i.e.
  logic).
- Nets and variables can now be explicitly declared using user-defined
  types:

    typedef logic [1:0] W;
    wire W w;

    typedef logic [1:0] V;
    var V v;

Fixes #2846
 2021-08-12 22:41:41 -06:00
Michael Singer 681a1c07e5 Allow optional comma after last entry in enum 2021-08-09 22:25:57 -06:00
Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types. 
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
 2021-08-06 21:35:43 +02:00
Miodrag Milanovic be04d8834e Require latest verific 2021-08-02 10:29:58 +02:00
Zachary Snow 4fec3a85cd genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00
Zachary Snow 3156226233 verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
Marcelina Kościelnicka 8bdc019730 verilog: Emit $meminit_v2 cell. 
Fixes #2447.
 2021-07-28 23:18:38 +02:00
Miodrag Milanovic 987fca5297 Update to latest verific 2021-07-21 09:46:53 +02:00
Rupert Swarbrick 414154dd27 Add support for parsing the SystemVerilog 'bind' construct 
This doesn't do anything useful yet: the patch just adds support for
the syntax to the lexer and parser and adds some tests to check the
syntax parses properly. This generates AST nodes, but doesn't yet
generate RTLIL.

Since our existing hierarchical_identifier parser doesn't allow bit
selects (so you can't do something like foo[1].bar[2].baz), I've also
not added support for a trailing bit select (the "constant_bit_select"
non-terminal in "bind_target_instance" in the spec). If we turn out to
need this in future, we'll want to augment hierarchical_identifier and
its other users too.

Note that you can't easily use the BNF from the spec:

    bind_directive ::=
        "bind" bind_target_scope [ : bind_target_instance_list]
               bind_instantiation ;
      | "bind" bind_target_instance bind_instantiation ;

even if you fix the lookahead problem, because code like this matches
both branches in the BNF:

    bind a b b_i (.*);

The problem is that 'a' could either be a module name or a degenerate
hierarchical reference. This seems to be a genuine syntactic
ambiguity, which the spec resolves (p739) by saying that we have to
wait until resolution time (the hierarchy pass) and take whatever is
defined, treating 'a' as an instance name if it names both an instance
and a module.

To keep the parser simple, it currently accepts this invalid syntax:

    bind a.b : c d e (.*);

This is invalid because we're in the first branch of the BNF above, so
the "a.b" term should match bind_target_scope: a module or interface
identifier, not an arbitrary hierarchical identifier.

This will fail in the hierarchy pass (when it's implemented in a
future patch).
 2021-07-16 09:31:39 -04:00
Zachary Snow a9c8ca21d5 sv: fix two struct access bugs 
- preserve signedness of struct members
- fix initial width detection of struct members (e.g., in case expressions)
 2021-07-15 11:57:20 -04:00
Marcelina Kościelnicka 009940f56c rtlil: Make Process handling more uniform with Cell and Wire. 
- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
  to add and remove processes
 2021-07-12 00:47:34 +02:00
Miodrag Milanovic 7a5ac90985 Update to latest Verific with extensions for initial assertions 2021-07-09 09:02:27 +02:00