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systemlib
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aligned pdf hardcopy colors to xschem light colorscheme, pdf and svg exports use the enable_layer[] array to display/hide layers as does draw().
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2020-08-30 10:38:29 +02:00 |
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utile
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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Makefile.in
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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actions.c
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bussed nets/pins in hierTEDAx netlists
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2020-11-28 16:41:35 +01:00 |
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break.awk
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according to answer from ngspice guys ngspice does not accept continuation lines for .title, .include and .lib statements, so break.awk will avoid breaking those lines. reversed default for tcl dim_background variable, so toggle colorscheme will work.
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2020-10-23 01:19:03 +02:00 |
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callback.c
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bussed nets/pins in hierTEDAx netlists
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2020-11-28 16:41:35 +01:00 |
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change_index.tcl
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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change_ref.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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check.c
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fold long lines
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2020-11-17 01:29:47 +01:00 |
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clip.c
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code refactoring (global context in Xschem_ctx), "New Schematic" or "New Symbol" will set netlist_type to "spice" or "symbol" respectively
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2020-10-12 13:13:31 +02:00 |
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convert_to_verilog2001.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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draw.c
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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editprop.c
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"xschem replace_symbol instance instname" --> "xschem replace_symbol instname", "xschem inst_pin_coord" made slot-aware, added comments in query functions
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2020-11-26 13:31:42 +01:00 |
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exp.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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expandlabel.y
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cleanup debug messages
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2020-11-16 02:25:43 +01:00 |
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findnet.c
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trim_wires() made 2 O.O.M. faster on big wire meshes; rects, lines, polys, arcs on hidden layers (View -> Visible Layers) not selectable by area or by mouse click
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2020-11-16 01:28:19 +01:00 |
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flatten.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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flatten_tedax.awk
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fix crashing netlister crashing bug if required schematic files are missing (null hier path). fix hierEDAx when netlisting empty blocks
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2020-11-24 17:37:27 +01:00 |
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font.c
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all xctx context is now a dynamically allocated structure; no observable performace impact
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2020-10-15 17:39:21 +02:00 |
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get_malloc_id.awk
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pass name and symname to tcl_hook, add @symname_ext in print_spice_element
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2020-10-14 21:04:45 +02:00 |
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globals.c
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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gschemtoxschem.awk
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added warnings (Options -> Show info window) if components are missing a name=... attribute / if symbols are missing a type=... attribute; eliminated usage of tcl "file normalize..." statements to avoid symlink dereferencing (if using symlinked libraries), aligned version/file_version tags in support awk scripts
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2020-10-06 16:19:52 +02:00 |
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gtkwave_server.tcl
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add gtkwave_server.tcl hook for gtkwave to listen to a tcp port
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2020-09-24 02:28:00 +02:00 |
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hash_iterator.c
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all xctx context is now a dynamically allocated structure; no observable performace impact
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2020-10-15 17:39:21 +02:00 |
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herculestospice.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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hilight.c
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Added various procedures to select flat / hierarchical instances and re-route a terminal to a different net. reroute_inst -> change a pin connection, reroute_net -> change net updating all connected components. "xschem instances_to_net", "xschem instance_nodemap", "xschem instance_pin_coord" new query commands added. "xschem get expandlabel node" renamed to "xschem expandlabel node".
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2020-11-26 03:46:55 +01:00 |
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hspice_backannotate.tcl
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code refactoring (global context in Xschem_ctx), "New Schematic" or "New Symbol" will set netlist_type to "spice" or "symbol" respectively
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2020-10-12 13:13:31 +02:00 |
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icon.c
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better xschem icon: added shapemask for "transparent" background
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2020-11-10 13:17:25 +01:00 |
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icon.xpm
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better xschem icon: added shapemask for "transparent" background
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2020-11-10 13:17:25 +01:00 |
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import_opus_symbols.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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in_memory_undo.c
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fold long lines
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2020-11-17 01:29:47 +01:00 |
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keys.help
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"Delete files" menu command added
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2020-10-24 23:46:19 +02:00 |
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label_compactor.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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main.c
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switch LC_ALL to "C" locale
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2020-11-28 16:54:15 +01:00 |
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make_edif.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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make_sch_from_cadence_pin.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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make_sch_from_spice.awk
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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make_sch_from_vhdl.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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make_sym.awk
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added warnings (Options -> Show info window) if components are missing a name=... attribute / if symbols are missing a type=... attribute; eliminated usage of tcl "file normalize..." statements to avoid symlink dereferencing (if using symlinked libraries), aligned version/file_version tags in support awk scripts
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2020-10-06 16:19:52 +02:00 |
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make_vhdl_from_spice.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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move.c
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fold long lines
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2020-11-17 01:29:47 +01:00 |
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netlist.c
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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netlist_compactor.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ngspice_backannotate.tcl
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exampels/poweramp.sch and examples/cmos_example.sch show how to use dynamuc ngspice simulation data backannotation, optimized fix of previous bbox bug
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2020-10-20 19:48:59 +02:00 |
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node_hash.c
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Removed all static/global name conflicts, avoided global conflicts with flex/bison generated code so xschem (as a test bench) can be compiled as a single big file that includes all other sources
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2020-11-03 12:10:55 +01:00 |
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options.c
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code refactoring (global context in Xschem_ctx), "New Schematic" or "New Symbol" will set netlist_type to "spice" or "symbol" respectively
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2020-10-12 13:13:31 +02:00 |
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order_labels.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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parse_synopsys_vhdl.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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parselabel.l
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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paste.c
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Removed all static/global name conflicts, avoided global conflicts with flex/bison generated code so xschem (as a test bench) can be compiled as a single big file that includes all other sources
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2020-11-03 12:10:55 +01:00 |
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psprint.c
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removed a stray "closepath" for open polygons in postscript output
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2020-11-19 11:28:04 +01:00 |
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rawtovcd.c
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code refactoring (global context in Xschem_ctx), "New Schematic" or "New Symbol" will set netlist_type to "spice" or "symbol" respectively
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2020-10-12 13:13:31 +02:00 |
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reduce_even_odd_array_labels.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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rescale.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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resources.tcl
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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save.c
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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scheduler.c
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bussed nets/pins in hierTEDAx netlists
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2020-11-28 16:41:35 +01:00 |
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select.c
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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sort_labels.awk
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spice_probe_dynamic.sym added to devices, retrieves node voltages with a pull method, so always updated, "@@pin" syntax in translate(), same as in format string for netlisting,print hilight nodes (ctrl-alt-j) will print .save instructions if netlist mode set to spice
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2020-10-20 01:05:40 +02:00 |
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spice.awk
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typo in spice.awk, fix check symbol storage before caching xctx->sym and xctx->symbols in load_sym_def(). Thanks to JL
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2020-10-16 22:16:54 +02:00 |
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spice_netlist.c
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fix crashing netlister crashing bug if required schematic files are missing (null hier path). fix hierEDAx when netlisting empty blocks
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2020-11-24 17:37:27 +01:00 |
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store.c
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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supergrep.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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svgdraw.c
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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symgen.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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tedax.awk
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hiertEDAx: don\t split on escaped white space. test schematic with weird instance/net names
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2020-11-24 15:25:37 +01:00 |
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tedax_netlist.c
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fix crashing netlister crashing bug if required schematic files are missing (null hier path). fix hierEDAx when netlisting empty blocks
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2020-11-24 17:37:27 +01:00 |
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token.c
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bussed nets/pins in hierTEDAx netlists
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2020-11-28 16:41:35 +01:00 |
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track_memory.awk
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refactored token.c, differentiate between windows and unix in absolute filename construction in xinit.c
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2020-10-14 01:38:51 +02:00 |
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traduci.awk
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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verilog.awk
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better node multiplicity detection in spice and verilog awk netlist post-processors (\?-?[0-9]+)
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2020-10-16 00:13:39 +02:00 |
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verilog_netlist.c
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fix crashing netlister crashing bug if required schematic files are missing (null hier path). fix hierEDAx when netlisting empty blocks
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2020-11-24 17:37:27 +01:00 |
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vhdl.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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vhdl_netlist.c
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fix crashing netlister crashing bug if required schematic files are missing (null hier path). fix hierEDAx when netlisting empty blocks
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2020-11-24 17:37:27 +01:00 |
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xinit.c
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wrap long lines in source code, set default direction of pins to "B"(idirectional) if not specified in spice netlist (no *.PININFO information)
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2020-11-22 00:51:24 +01:00 |
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xschem.h
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allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example
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2020-11-24 02:54:45 +01:00 |
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xschem.help
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added -b/--batch cmd option (__unix__ only) to detach xschem completely from console
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2020-08-31 21:24:03 +02:00 |
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xschem.tcl
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switch LC_ALL to "C" locale
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2020-11-28 16:54:15 +01:00 |
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xschemrc
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Option (default now) to export svg images using the svg <text> element. This makes generated SVGs much smaller and in most cases faster to render.
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2020-11-18 18:29:14 +01:00 |
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