fix crashing netlister crashing bug if required schematic files are missing (null hier path). fix hierEDAx when netlisting empty blocks

src/actions.c

@@ -1165,14 +1165,8 @@ void descend_schematic(int instnumber)
 
   if(                   /*  do not descend if not subcircuit */
      (xctx->inst[selectedgroup[0].n].ptr+ xctx->sym)->type &&
-     strcmp(
-        (xctx->inst[selectedgroup[0].n].ptr+ xctx->sym)->type,
-         "subcircuit"
-     ) &&
-     strcmp(
-        (xctx->inst[selectedgroup[0].n].ptr+ xctx->sym)->type,
-         "primitive"
-     )
+     strcmp( (xctx->inst[selectedgroup[0].n].ptr+ xctx->sym)->type, "subcircuit") &&
+     strcmp( (xctx->inst[selectedgroup[0].n].ptr+ xctx->sym)->type, "primitive")
   ) return;
 
   if(modified)

src/flatten_tedax.awk

@@ -68,9 +68,10 @@ function expand(cell, instname, path, maplist,       i, j, subpos, subcell, subi
         sub(/__map__/, "map", $0)
         out("#" spaces(hier * 2 - 1) $0)
       }
+      
       expand(subcell, subinst, path subinst hiersep, submaplist)
-      $0 = netlist[i] # restore $0 after recursive call
-      reparse()
+ 
+      i--; continue; # redo processing of current line
     }
     if($1 == "conn") {
       dbg("conn: $2=" $2)

src/spice_netlist.c

@@ -164,7 +164,10 @@ void global_spice_netlist(int global)  /* netlister driver */
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
    load_schematic(1, xctx->sch[xctx->currsch], 0);
 
+   my_strdup(469, &xctx->sch_path[xctx->currsch+1], xctx->sch_path[xctx->currsch]);
+   my_strcat(481, &xctx->sch_path[xctx->currsch+1], "->netlisting");
    xctx->currsch++;
+   
     dbg(1, "global_spice_netlist(): last defined symbol=%d\n",xctx->symbols);
    subckt_name=NULL;
    for(i=0;i<xctx->symbols;i++)

src/tedax_netlist.c

@@ -91,7 +91,10 @@ void global_tedax_netlist(int global)  /* netlister driver */
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
    load_schematic(1, xctx->sch[xctx->currsch], 0);
 
+   my_strdup(482, &xctx->sch_path[xctx->currsch+1], xctx->sch_path[xctx->currsch]);
+   my_strcat(485, &xctx->sch_path[xctx->currsch+1], "->netlisting");
    xctx->currsch++;
+
     dbg(2, "global_tedax_netlist(): last defined symbol=%d\n",xctx->symbols);
    for(i=0;i<xctx->symbols;i++)
    {

src/verilog_netlist.c

@@ -278,7 +278,10 @@ void global_verilog_netlist(int global)  /* netlister driver */
 
    load_schematic(1, xctx->sch[xctx->currsch], 0);
 
+   my_strdup(487, &xctx->sch_path[xctx->currsch+1], xctx->sch_path[xctx->currsch]);
+   my_strcat(496, &xctx->sch_path[xctx->currsch+1], "->netlisting");
    xctx->currsch++;
+
    dbg(2, "global_verilog_netlist(): last defined symbol=%d\n",xctx->symbols);
    subckt_name=NULL;
    for(i=0;i<xctx->symbols;i++)

src/vhdl_netlist.c

@@ -330,7 +330,10 @@ void global_vhdl_netlist(int global)  /* netlister driver */
    remove_symbols(); /* 20161205 ensure all unused symbols purged before descending hierarchy */
    load_schematic(1, xctx->sch[xctx->currsch], 0);
 
+   my_strdup(502, &xctx->sch_path[xctx->currsch+1], xctx->sch_path[xctx->currsch]);
+   my_strcat(509, &xctx->sch_path[xctx->currsch+1], "->netlisting");
    xctx->currsch++;
+
     dbg(2, "global_vhdl_netlist(): last defined symbol=%d\n",xctx->symbols);
    subckt_name=NULL;
    for(i=0;i<xctx->symbols;i++)

src/xschem.tcl

@@ -2507,6 +2507,8 @@ proc text_line {txtlabel clear {preserve_disabled disabled} } {
 }
 
 proc alert_ {txtlabel {position +200+300} {nowait {0}}} {
+   global no_x
+   if {[info exists no_x] } {return}
    toplevel .alert -class Dialog
    wm title .alert {Alert}
    set X [expr {[winfo pointerx .alert] - 60}]

xschem_library/pcb/hierarchical_tedax.sch

@@ -19,9 +19,9 @@ N 540 -100 540 -80 {lab=VSS}
 N 540 -200 540 -160 {lab=VREF}
 N 540 -200 630 -200 {lab=VREF}
 N 540 -320 540 -290 {lab=VCC}
-N 630 -380 630 -280 {lab=VSSLOAD}
-N 630 -380 1130 -380 {lab=VSSLOAD}
-N 1130 -380 1130 -360 {lab=VSSLOAD}
+N 630 -380 630 -280 {lab=VSS\\ LOAD}
+N 630 -380 1130 -380 {lab=VSS\\ LOAD}
+N 1130 -380 1130 -360 {lab=VSS\\ LOAD}
 N 1130 -300 1130 -270 {lab=D}
 N 860 -120 880 -120 {lab=#net1}
 N 770 -120 800 -120 {lab=RST}
@@ -37,7 +37,7 @@ N 390 -440 390 -420 {lab=VSS}
 N 310 -500 390 -500 { lab=VSS_ANALOG}
 N 310 -440 310 -420 {lab=VSS}
 N 540 -230 540 -200 {lab=VREF}
-N 1130 -430 1130 -380 {lab=VSSLOAD}
+N 1130 -430 1130 -380 {lab=VSS\\ LOAD}
 N 920 -240 920 -170 {lab=#net2}
 N 990 -220 990 -210 {lab=G}
 N 1020 -790 1070 -790 { lab=VOUT_PROTECTED1}
@@ -101,8 +101,6 @@ C {lab_pin.sym} 70 -390 0 1 {name=p12 lab=VOUT_PROTECTED2}
 C {lab_pin.sym} 70 -370 0 1 {name=p13 lab=VSS_ANALOG}
 C {lab_pin.sym} 70 -350 0 1 {name=p14 lab=VSSLOAD}
 C {noconn.sym} 90 -330 0 1 {name=l5}
-C {netlist_options.sym} 30 -260 0 0 {hiersep=.
-}
 C {voltage_protection.sym} 1880 -860 0 0 {name=xprot2}
 C {lab_pin.sym} 2080 -870 0 1 {name=p15 lab=VOUT_PROTECTED2}
 C {lab_pin.sym} 1730 -870 0 0 {name=p16 lab=VCC12}
@@ -110,3 +108,5 @@ C {diode.sym} 2080 -950 0 0 {name=D2 model=D1N914 area=1 device=D1N914 footprint
 C {vdd.sym} 2080 -980 0 0 {name=l10 lab=VCC}
 C {lab_pin.sym} 1730 -850 0 0 {name=p17 lab=VSS_ANALOG}
 C {lab_pin.sym} 70 -410 0 1 {name=p18 lab=VOUT_PROTECTED1}
+C {netlist_options.sym} 30 -260 0 0 {hiersep=.
+}