stefan schippers 8dde6c7ed3 remove unused xschemrc file		2023-04-28 17:17:00 +02:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	ind.sym artwork	2023-04-28 11:23:06 +02:00
examples	Add inst_sch_select/ example directory (instance based implementation selection)	2023-04-25 09:15:17 +02:00
generators	allow tcl procedures to generate generator script and parameters, update vhdl and verilog netlisters to handle generator schematic/symbol references	2023-04-26 09:54:35 +02:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
inst_sch_select	remove unused xschemrc file	2023-04-28 17:17:00 +02:00
logic	update test_ngspice.sch example circuit	2023-03-09 20:44:51 +01:00
ngspice	align set_thick_waves() to comply with previous commit	2023-04-27 22:49:43 +02:00
pcb	test schematics update	2022-10-21 11:28:17 +02:00
rom8k	add graph_linewidth_mult xschemrc variable to set default multiplier for graph line width w.r.t. xschem (current) line width. Add "Line width:" entry in graph_edit_properties dialog box	2023-04-28 10:45:56 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
viewdraw_import	add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing	2022-01-15 13:31:45 +01:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	update test schematic (better screen redraw if moving while simulating)	2022-10-27 10:09:19 +02:00
Makefile	Add inst_sch_select/ example directory (instance based implementation selection)	2023-04-25 09:15:17 +02:00