allow tcl procedures to generate generator script and parameters, update vhdl and verilog netlisters to handle generator schematic/symbol references
This commit is contained in:
stefan schippers
parent
3142279d02
commit
10441ef901
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@ -1217,11 +1217,11 @@ const char *get_sym_name(int inst, int ext)
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else sym = skip_dir(add_ext(rel_sym_path(sch), ".sym"));
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}
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else if(ext) {
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sym = get_cell_w_ext(xctx->inst[inst].name, 0);
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sym = get_cell_w_ext(tcl_hook2(xctx->inst[inst].name), 0);
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} else {
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sym = skip_dir(xctx->inst[inst].name);
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sym = skip_dir(tcl_hook2(xctx->inst[inst].name));
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}
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dbg(1, "get_sym_name(): returning sym=%s\n", sym);
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dbg(1, "get_sym_name(): inst=%d, ext=%d, returning sym=%s\n", inst, ext, sym);
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return sym;
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}
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@ -1404,21 +1404,24 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst)
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dbg(1, "get_sch_from_sym(): symbol %s inst=%d\n", sym->name, inst);
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if(inst >= 0) my_strdup(_ALLOC_ID_, &str_tmp, get_tok_value(xctx->inst[inst].prop_ptr, "schematic", 2));
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if(!str_tmp) my_strdup2(_ALLOC_ID_, &str_tmp, get_tok_value(sym->prop_ptr, "schematic", 2));
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if(str_tmp[0]) {
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if(str_tmp[0]) { /* schematic attribute in symbol or instance was given */
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/* @symname in schematic attribute will be replaced with symbol name */
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my_strdup2(_ALLOC_ID_, &sch, str_replace(str_tmp, "@symname", skip_dir(sym->name), '\\'));
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}
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if(str_tmp[0] && is_generator(str_tmp)) { /* generator: return as is */
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my_strncpy(filename, sch, PATH_MAX);
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} else if(str_tmp[0]) {
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dbg(1, "get_sch_from_sym(): sch=%s\n", sch);
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my_strdup2(_ALLOC_ID_, &sch, tcl_hook2(&sch));
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dbg(1, "get_sch_from_sym(): after tcl_hook2 sch=%s\n", sch);
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/* for schematics referenced from web symbols do not build absolute path */
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if(web_url) my_strncpy(filename, sch, PATH_MAX);
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else my_strncpy(filename, abs_sym_path(sch, ""), PATH_MAX);
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my_strdup2(_ALLOC_ID_, &sch, tcl_hook2(str_replace(str_tmp, "@symname", sym->name, '\\')));
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if(is_generator(sch)) { /* generator: return as is */
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my_strncpy(filename, sch, PATH_MAX);
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dbg(1, "get_sch_from_sym(): filename=%s\n", filename);
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} else { /* not generator */
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dbg(1, "get_sch_from_sym(): after tcl_hook2 sch=%s\n", sch);
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/* for schematics referenced from web symbols do not build absolute path */
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if(web_url) my_strncpy(filename, sch, PATH_MAX);
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else my_strncpy(filename, abs_sym_path(sch, ""), PATH_MAX);
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}
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} else { /* no schematic attribute from instance or symbol */
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if(is_generator(sym->name)) my_strncpy(filename, sym->name, PATH_MAX);
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const char *symname_tcl = tcl_hook2(sym->name);
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if(is_generator(symname_tcl)) my_strncpy(filename, symname_tcl, PATH_MAX);
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else if(tclgetboolvar("search_schematic")) {
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/* for schematics referenced from web symbols do not build absolute path */
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if(web_url) my_strncpy(filename, add_ext(sym->name, ".sch"), PATH_MAX);
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@ -1439,7 +1442,7 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst)
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/* if( strstr(xctx->current_dirname, "http://") == xctx->current_dirname ||
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* strstr(xctx->current_dirname, "https://") == xctx->current_dirname) {
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*/
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if(web_url) {
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if(web_url) {
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char sympath[PATH_MAX];
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/* download item into ${XSCHEM_TMP_DIR}/xschem_web */
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tclvareval("try_download_url {", xctx->current_dirname, "} {", filename, "}", NULL);
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19
src/save.c
19
src/save.c
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@ -3146,6 +3146,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
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const char *dash;
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xSymbol * symbol;
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int symbols, sym_n_pins=0, generator;
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const char *cmd;
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check_symbol_storage();
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symbol = xctx->sym;
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@ -3156,10 +3157,12 @@ int load_sym_def(const char *name, FILE *embed_fd)
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lcc=NULL;
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my_realloc(_ALLOC_ID_, &lcc, (level + 1) * sizeof(Lcc));
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max_level = level + 1;
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generator = is_generator(name);
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cmd = tcl_hook2(name);
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dbg(1, "l_s_d(): cmd=%s\n", cmd);
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generator = is_generator(cmd);
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if(generator) {
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char * cmd = get_generator_command(name);
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cmd = get_generator_command(cmd);
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dbg(1, "l_s_d(): cmd=%s\n", cmd);
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if(cmd) {
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lcc[level].fd = popen(cmd, "r"); /* execute ss="/path/to/xxx par1 par2 ..." and pipe in the stdout */
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my_free(_ALLOC_ID_, &cmd);
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@ -4002,8 +4005,9 @@ void descend_symbol(void)
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/* load_symbol(name_embedded); */
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load_schematic(1, name_embedded, 1, 1);
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} else {
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char sympath[PATH_MAX];
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my_strncpy(sympath, abs_sym_path(name, ""), S(sympath));
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char *sympath = NULL;
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my_strdup2(_ALLOC_ID_, &sympath, name);
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my_strdup2(_ALLOC_ID_, &sympath, abs_sym_path(tcl_hook2(sympath), ""));
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unselect_all(1);
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remove_symbols(); /* must follow save (if) embedded */
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dbg(1, "name=%s, sympath=%s\n", name, sympath);
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@ -4013,11 +4017,14 @@ void descend_symbol(void)
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(strstr(xctx->current_dirname, "http://") == xctx->current_dirname ||
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strstr(xctx->current_dirname, "https://") == xctx->current_dirname)) {
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/* symbols have already been downloaded while loading parent schematic: set local file path */
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my_snprintf(sympath, S(sympath), "%s/xschem_web/%s", tclgetvar("XSCHEM_TMP_DIR"), get_cell_w_ext(name, 0));
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my_mstrcat(_ALLOC_ID_, &sympath, tclgetvar("XSCHEM_TMP_DIR"),
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"/xschem_web/", get_cell_w_ext(name, 0), NULL);
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load_schematic(1, sympath, 1, 1);
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} else {
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dbg(1, "descend_symbol(): sympath=%s\n", sympath);
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load_schematic(1, sympath, 1, 1);
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}
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my_free(_ALLOC_ID_, &sympath);
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}
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zoom_full(1, 0, 1, 0.97);
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}
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@ -534,7 +534,9 @@ int spice_block_netlist(FILE *fd, int i)
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char *extra=NULL;
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int split_f;
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const char *sym_def;
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char *name = NULL;
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my_strdup(_ALLOC_ID_, &name, tcl_hook2(xctx->sym[i].name));
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split_f = tclgetboolvar("split_files");
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if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"spice_stop",0),"true") )
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@ -545,23 +547,21 @@ int spice_block_netlist(FILE *fd, int i)
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dbg(1, "spice_block_netlist(): filename=%s\n", filename);
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if(split_f) {
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my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
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tclgetvar("netlist_dir"), skip_dir(xctx->sym[i].name), getpid());
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tclgetvar("netlist_dir"), skip_dir(name), getpid());
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dbg(1, "spice_block_netlist(): split_files: netl_filename=%s\n", netl_filename);
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fd=fopen(netl_filename, "w");
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my_snprintf(cellname, S(cellname), "%s.spice", skip_dir(xctx->sym[i].name));
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my_snprintf(cellname, S(cellname), "%s.spice", skip_dir(name));
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}
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fprintf(fd, "\n* expanding symbol: %s # of pins=%d\n",
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xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
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fprintf(fd, "\n* expanding symbol: %s # of pins=%d\n", name,xctx->sym[i].rects[PINLAYER] );
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if(xctx->sym[i].base_name) fprintf(fd, "** sym_path: %s\n", abs_sym_path(xctx->sym[i].base_name, ""));
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else fprintf(fd, "** sym_path: %s\n", sanitized_abs_sym_path(xctx->sym[i].name, ""));
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else fprintf(fd, "** sym_path: %s\n", sanitized_abs_sym_path(name, ""));
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sym_def = get_tok_value(xctx->sym[i].prop_ptr,"spice_sym_def",0);
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if(sym_def[0]) {
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fprintf(fd, "%s\n", sym_def);
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} else {
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char *s = sanitize(skip_dir(xctx->sym[i].name));
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const char *s = sanitize(skip_dir(name));
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fprintf(fd, "** sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
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fprintf(fd, ".subckt %s ", s);
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my_free(_ALLOC_ID_, &s);
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print_spice_subckt_nodes(fd, i);
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my_strdup(_ALLOC_ID_, &extra, get_tok_value(xctx->sym[i].prop_ptr,"extra",0) );
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@ -598,6 +598,7 @@ int spice_block_netlist(FILE *fd, int i)
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if(debug_var==0) xunlink(netl_filename);
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}
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xctx->netlist_count++;
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my_free(_ALLOC_ID_, &name);
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return err;
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}
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71
src/token.c
71
src/token.c
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@ -61,26 +61,28 @@ void hash_all_names(void)
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my_free(_ALLOC_ID_, &type);
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}
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const char *tcl_hook2(char **res)
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/* if cmd is wrapped inside tcleval(...) pass the content to tcl
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* for evaluation, return tcl result. If no tcleval(...) found return copy of cmd */
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const char *tcl_hook2(const char *cmd)
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{
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static char *result = NULL;
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static const char *empty="";
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char *unescaped_res;
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if(res == NULL || *res == NULL) {
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if(cmd == NULL) {
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my_free(_ALLOC_ID_, &result);
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return empty;
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}
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if(strstr(*res, "tcleval(") == *res) {
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unescaped_res = str_replace(*res, "\\}", "}", 0);
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if(strstr(cmd, "tcleval(") == cmd) {
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unescaped_res = str_replace(cmd, "\\}", "}", 0);
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tclvareval("tclpropeval2 {", unescaped_res, "}" , NULL);
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my_strdup2(_ALLOC_ID_, &result, tclresult());
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/* dbg(0, "tcl_hook2: return: %s\n", result);*/
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return result;
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} else {
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/* dbg(0, "tcl_hook2: return: %s\n", *res); */
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return *res;
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/* dbg(0, "tcl_hook2: return: %s\n", cmd); */
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my_strdup2(_ALLOC_ID_, &result, cmd);
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}
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return result;
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}
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/* Missing:
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@ -187,11 +189,15 @@ int is_generator(const char *name)
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#endif
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}
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/* caller must free returned string
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* cleanup syntax of symbol generators: xxx(a,b,c) --> xxx_a_b_c */
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char *sanitize(const char *name)
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/* cleanup syntax of symbol generators: xxx(a,b,c) --> xxx_a_b_c */
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const char *sanitize(const char *name)
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{
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char *s = NULL;
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static char *s = NULL;
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static char *empty="";
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if(name == NULL) {
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my_free(_ALLOC_ID_, &s);
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return empty;
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}
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tclvareval("regsub -all { *[(),] *} {", name, "} _", NULL);
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tclvareval("regsub {_$} {", tclresult(), "} {}", NULL);
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my_strdup2(_ALLOC_ID_, &s, tclresult());
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@ -493,7 +499,7 @@ const char *get_tok_value(const char *s,const char *tok, int with_quotes)
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} else if(state==TOK_END) {
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result[value_pos]='\0';
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if( !cmp ) {
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return with_quotes & 2 ? result : tcl_hook2(&result);
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return with_quotes & 2 ? result : tcl_hook2(result);
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}
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value_pos=0;
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state=TOK_BEGIN;
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@ -502,7 +508,7 @@ const char *get_tok_value(const char *s,const char *tok, int with_quotes)
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if(c=='\0') {
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result[0]='\0';
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xctx->tok_size = 0;
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return with_quotes & 2 ? result : tcl_hook2(&result);
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return with_quotes & 2 ? result : tcl_hook2(result);
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}
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}
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}
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@ -854,11 +860,13 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
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else if(strcmp(token,"@symname")==0) /* of course symname must not be present */
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/* in hash table */
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{
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fputs(get_sym_name(inst, 0), fd);
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const char *s = sanitize(get_sym_name(inst, 0));
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fputs(s, fd);
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}
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else if (strcmp(token,"@symname_ext")==0)
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{
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fputs(get_sym_name(inst, 1), fd);
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const char *s = sanitize(get_sym_name(inst, 1));
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fputs(s, fd);
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}
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else if(strcmp(token,"@schname_ext")==0) /* of course schname must not be present */
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/* in hash table */
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@ -1229,9 +1237,9 @@ void print_vhdl_element(FILE *fd, int inst)
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/* print instance name and subckt */
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dbg(2, "print_vhdl_element(): printing inst name & subcircuit name\n");
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if( (lab = expandlabel(name, &tmp)) != NULL)
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fprintf(fd, "%d %s : %s\n", tmp, lab, get_sym_name(inst, 0) );
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fprintf(fd, "%d %s : %s\n", tmp, lab, sanitize(get_sym_name(inst, 0)) );
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else /* name in some strange format, probably an error */
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fprintf(fd, "1 %s : %s\n", name, get_sym_name(inst, 0) );
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fprintf(fd, "1 %s : %s\n", name, sanitize(get_sym_name(inst, 0)) );
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dbg(2, "print_vhdl_element(): printing generics passed as properties\n");
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@ -1376,7 +1384,7 @@ void print_generic(FILE *fd, char *ent_or_comp, int symbol)
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my_strdup(_ALLOC_ID_, &generic_type, get_tok_value(xctx->sym[symbol].prop_ptr,"generic_type",0));
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dbg(2, "print_generic(): symbol=%d template=%s \n", symbol, template);
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fprintf(fd, "%s %s ",ent_or_comp, skip_dir(xctx->sym[symbol].name));
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fprintf(fd, "%s %s ",ent_or_comp, sanitize(skip_dir(xctx->sym[symbol].name)));
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if(!strcmp(ent_or_comp,"entity"))
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fprintf(fd, "is\n");
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else
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@ -1594,11 +1602,11 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
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my_strdup(_ALLOC_ID_, &format1, get_tok_value(xctx->sym[symbol].prop_ptr, "format", 2));
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dbg(1, "print_spice_subckt(): format1=%s\n", format1);
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/* can not do this, since @symname is used as a marker later */
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/* can not do this, since @symname is used as a token later in format parser */
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/* my_strdup(_ALLOC_ID_, &format1, str_replace(format1, "@symname", skip_dir(xctx->sym[symbol].name), '\\')); */
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if(format1 && strstr(format1, "tcleval(") == format1) {
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tclres = tcl_hook2(&format1);
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tclres = tcl_hook2(format1);
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if(!strcmp(tclres, "?\n")) {
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char *ptr = strrchr(format1 + 8, ')');
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*ptr = '\0';
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@ -1869,17 +1877,16 @@ int print_spice_element(FILE *fd, int inst)
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}
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else if (strcmp(token,"@symname")==0) /* of course symname must not be present in attributes */
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{
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char *s = sanitize(get_sym_name(inst, 0));
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const char *s = sanitize(get_sym_name(inst, 0));
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tmp = strlen(s) +100 ; /* always make room for some extra chars
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* so 1-char writes to result do not need reallocs */
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STR_ALLOC(&result, tmp + result_pos, &size);
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result_pos += my_snprintf(result + result_pos, tmp, "%s", s);
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my_free(_ALLOC_ID_, &s);
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/* fputs(s,fd); */
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}
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else if (strcmp(token,"@symname_ext")==0) /* of course symname must not be present in attributes */
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{
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const char *s = get_sym_name(inst, 1);
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const char *s = sanitize(get_sym_name(inst, 1));
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tmp = strlen(s) +100 ; /* always make room for some extra chars
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* so 1-char writes to result do not need reallocs */
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STR_ALLOC(&result, tmp + result_pos, &size);
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@ -2237,11 +2244,13 @@ void print_tedax_element(FILE *fd, int inst)
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else if(strcmp(token,"@symname")==0) /* of course symname must not be present */
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/* in hash table */
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{
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fputs(get_sym_name(inst, 0), fd);
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const char *s = sanitize(get_sym_name(inst, 0));
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fputs(s, fd);
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}
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else if (strcmp(token,"@symname_ext")==0)
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{
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fputs(get_sym_name(inst, 1), fd);
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const char *s = sanitize(get_sym_name(inst, 1));
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fputs(s, fd);
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}
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else if(strcmp(token,"@schname_ext")==0) /* of course schname must not be present */
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/* in hash table */
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@ -2476,11 +2485,13 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
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else if(strcmp(token,"@symname")==0) /* of course symname must not be present */
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/* in hash table */
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{
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fputs(get_sym_name(inst, 0), fd);
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const char *s = sanitize(get_sym_name(inst, 0));
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fputs(s, fd);
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}
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else if (strcmp(token,"@symname_ext")==0)
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{
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fputs(get_sym_name(inst, 1), fd);
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const char *s = sanitize(get_sym_name(inst, 1));
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fputs(s, fd);
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}
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else if(strcmp(token,"@schname_ext")==0) /* of course schname must not be present */
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||||
/* in hash table */
|
||||
|
|
@ -2635,7 +2646,7 @@ void print_verilog_element(FILE *fd, int inst)
|
|||
s=xctx->inst[inst].prop_ptr;
|
||||
/* print instance subckt */
|
||||
dbg(2, "print_verilog_element(): printing inst name & subcircuit name\n");
|
||||
fprintf(fd, "%s\n", symname);
|
||||
fprintf(fd, "%s\n", sanitize(symname));
|
||||
my_free(_ALLOC_ID_, &symname);
|
||||
/* -------- print generics passed as properties */
|
||||
tmp=0;
|
||||
|
|
@ -3540,7 +3551,7 @@ const char *translate(int inst, const char* s)
|
|||
|
||||
/* if result is like: 'tcleval(some_string)' pass it thru tcl evaluation so expressions
|
||||
* can be calculated */
|
||||
return tcl_hook2(&result);
|
||||
return tcl_hook2(result);
|
||||
}
|
||||
|
||||
const char *translate2(Lcc *lcc, int level, char* s)
|
||||
|
|
@ -3668,7 +3679,7 @@ const char *translate2(Lcc *lcc, int level, char* s)
|
|||
my_free(_ALLOC_ID_, &token);
|
||||
my_free(_ALLOC_ID_, &value);
|
||||
dbg(1, "translate2(): result=%s\n", result);
|
||||
/* return tcl_hook2(&result); */
|
||||
/* return tcl_hook2(result); */
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -435,8 +435,9 @@ int verilog_block_netlist(FILE *fd, int i)
|
|||
int split_f;
|
||||
const char *sym_def;
|
||||
char *extra_ptr, *saveptr1, *extra_token, *extra = NULL, *extra2=NULL;
|
||||
char *name = NULL;
|
||||
|
||||
|
||||
my_strdup(_ALLOC_ID_, &name, tcl_hook2(xctx->sym[i].name));
|
||||
split_f = tclgetboolvar("split_files");
|
||||
if(!strcmp( get_tok_value(xctx->sym[i].prop_ptr,"verilog_stop",0),"true") )
|
||||
verilog_stop=1;
|
||||
|
|
@ -446,17 +447,16 @@ int verilog_block_netlist(FILE *fd, int i)
|
|||
|
||||
if(split_f) {
|
||||
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
|
||||
tclgetvar("netlist_dir"), skip_dir(xctx->sym[i].name), getpid());
|
||||
tclgetvar("netlist_dir"), skip_dir(name), getpid());
|
||||
dbg(1, "global_vhdl_netlist(): split_files: netl_filename=%s\n", netl_filename);
|
||||
fd=fopen(netl_filename, "w");
|
||||
my_snprintf(cellname, S(cellname), "%s.v", skip_dir(xctx->sym[i].name) );
|
||||
my_snprintf(cellname, S(cellname), "%s.v", skip_dir(name));
|
||||
|
||||
}
|
||||
dbg(1, "verilog_block_netlist(): expanding %s\n", xctx->sym[i].name);
|
||||
fprintf(fd, "\n// expanding symbol: %s # of pins=%d\n",
|
||||
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
|
||||
dbg(1, "verilog_block_netlist(): expanding %s\n", name);
|
||||
fprintf(fd, "\n// expanding symbol: %s # of pins=%d\n", name, xctx->sym[i].rects[PINLAYER] );
|
||||
if(xctx->sym[i].base_name) fprintf(fd, "// sym_path: %s\n", abs_sym_path(xctx->sym[i].base_name, ""));
|
||||
else fprintf(fd, "// sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
|
||||
else fprintf(fd, "// sym_path: %s\n", sanitized_abs_sym_path(name, ""));
|
||||
sym_def = get_tok_value(xctx->sym[i].prop_ptr,"verilog_sym_def",0);
|
||||
if(sym_def[0]) {
|
||||
fprintf(fd, "%s\n", sym_def);
|
||||
|
|
@ -465,7 +465,7 @@ int verilog_block_netlist(FILE *fd, int i)
|
|||
int_hash_init(&table, 37);
|
||||
my_strdup(_ALLOC_ID_, &extra, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
|
||||
my_strdup(_ALLOC_ID_, &extra2, get_tok_value(xctx->sym[i].prop_ptr, "verilog_extra", 0));
|
||||
fprintf(fd, "// sch_path: %s\n", filename);
|
||||
fprintf(fd, "// sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
|
||||
verilog_stop? load_schematic(0,filename, 0, 1) : load_schematic(1,filename, 0, 1);
|
||||
/* print verilog timescale and preprocessor directives 10102004 */
|
||||
fmt_attr = xctx->format ? xctx->format : "verilog_format";
|
||||
|
|
@ -500,7 +500,7 @@ int verilog_block_netlist(FILE *fd, int i)
|
|||
|
||||
|
||||
|
||||
fprintf(fd, "module %s (\n", symname);
|
||||
fprintf(fd, "module %s (\n", sanitize(symname));
|
||||
my_free(_ALLOC_ID_, &symname);
|
||||
/*print_generic(fd, "entity", i); */
|
||||
|
||||
|
|
@ -615,6 +615,7 @@ int verilog_block_netlist(FILE *fd, int i)
|
|||
if(debug_var==0) xunlink(netl_filename);
|
||||
}
|
||||
xctx->netlist_count++;
|
||||
my_free(_ALLOC_ID_, &name);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -331,7 +331,8 @@ int global_vhdl_netlist(int global) /* netlister driver */
|
|||
|
||||
fprintf(fd,"end %s ;\n\n", skip_dir( xctx->sch[xctx->currsch]) );
|
||||
fprintf(fd,"architecture arch_%s of %s is\n\n",
|
||||
skip_dir( xctx->sch[xctx->currsch]) , skip_dir( xctx->sch[xctx->currsch]));
|
||||
sanitize(skip_dir( xctx->sch[xctx->currsch])),
|
||||
sanitize(skip_dir( xctx->sch[xctx->currsch])));
|
||||
|
||||
dbg(1, "global_vhdl_netlist(): printing top level used components\n");
|
||||
/* print all components */
|
||||
|
|
@ -551,13 +552,13 @@ int vhdl_block_netlist(FILE *fd, int i)
|
|||
fprintf(fd, "\n-- expanding symbol: %s # of pins=%d\n",
|
||||
xctx->sym[i].name,xctx->sym[i].rects[PINLAYER] );
|
||||
if(xctx->sym[i].base_name) fprintf(fd, "-- sym_path: %s\n", abs_sym_path(xctx->sym[i].base_name, ""));
|
||||
else fprintf(fd, "-- sym_path: %s\n", abs_sym_path(xctx->sym[i].name, ""));
|
||||
else fprintf(fd, "-- sym_path: %s\n", sanitized_abs_sym_path(xctx->sym[i].name, ""));
|
||||
sym_def = get_tok_value(xctx->sym[i].prop_ptr,"vhdl_sym_def",0);
|
||||
if(sym_def[0]) {
|
||||
fprintf(fd, "%s\n", sym_def);
|
||||
} else {
|
||||
Int_hashtable table = {NULL, 0};
|
||||
fprintf(fd, "-- sch_path: %s\n", filename);
|
||||
fprintf(fd, "-- sch_path: %s\n", sanitized_abs_sym_path(filename, ""));
|
||||
load_schematic(1,filename, 0, 1);
|
||||
dbg(1, "vhdl_block_netlist(): packages\n");
|
||||
for(l=0;l<xctx->instances; ++l)
|
||||
|
|
@ -632,11 +633,12 @@ int vhdl_block_netlist(FILE *fd, int i)
|
|||
if(xctx->inst[l].prop_ptr) fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
|
||||
}
|
||||
}
|
||||
fprintf(fd,"end %s ;\n\n", skip_dir(xctx->sym[i].name) );
|
||||
fprintf(fd,"end %s ;\n\n", sanitize(skip_dir(xctx->sym[i].name)) );
|
||||
|
||||
dbg(1, "vhdl_block_netlist(): architecture\n");
|
||||
fprintf(fd,"architecture arch_%s of %s is\n\n",
|
||||
skip_dir(xctx->sym[i].name), skip_dir(xctx->sym[i].name) );
|
||||
sanitize(skip_dir(xctx->sym[i].name)),
|
||||
sanitize(skip_dir(xctx->sym[i].name)) );
|
||||
/* skip_dir( xctx->sch[xctx->currsch]), skip_dir( xctx->sch[xctx->currsch])); */
|
||||
/* load current schematic to print used components */
|
||||
|
||||
|
|
@ -724,7 +726,7 @@ int vhdl_block_netlist(FILE *fd, int i)
|
|||
}
|
||||
|
||||
if(xctx->schvhdlprop && xctx->schvhdlprop[0]) fprintf(fd, "%s\n", xctx->schvhdlprop);
|
||||
fprintf(fd, "end arch_%s ;\n\n", skip_dir(xctx->sym[i].name) ); /* skip_dir( xctx->sch[xctx->currsch]) ); */
|
||||
fprintf(fd, "end arch_%s ;\n\n", sanitize(skip_dir(xctx->sym[i].name)) );
|
||||
my_free(_ALLOC_ID_, &sig_type);
|
||||
my_free(_ALLOC_ID_, &port_value);
|
||||
my_free(_ALLOC_ID_, &type);
|
||||
|
|
|
|||
|
|
@ -646,6 +646,7 @@ static void delete_schematic_data(int delete_pixmap)
|
|||
remove_symbols();
|
||||
str_replace(NULL, NULL, NULL, 0);
|
||||
escape_chars(NULL);
|
||||
sanitize(NULL);
|
||||
is_generator(NULL);
|
||||
free_rawfile(0);
|
||||
free_xschem_data(); /* delete the xctx struct */
|
||||
|
|
|
|||
|
|
@ -1158,7 +1158,7 @@ extern const char *get_cell_w_ext(const char *str, int no_of_dir);
|
|||
extern const char *rel_sym_path(const char *s);
|
||||
extern const char *abs_sym_path(const char *s, const char *ext);
|
||||
extern const char *sanitized_abs_sym_path(const char *s, const char *ext);
|
||||
extern char *sanitize(const char *name);
|
||||
extern const char *sanitize(const char *name);
|
||||
extern const char *add_ext(const char *f, const char *ext);
|
||||
extern void make_symbol(void);
|
||||
/* sort based on pinnumber pin attribute if present */
|
||||
|
|
@ -1346,7 +1346,7 @@ extern void tclsetdoublevar(const char *s, const double value);
|
|||
extern void tclsetboolvar(const char *s, const int value);
|
||||
extern void tclsetintvar(const char *s, const int value);
|
||||
extern int tclvareval(const char *script, ...);
|
||||
extern const char *tcl_hook2(char **res);
|
||||
extern const char *tcl_hook2(const char *res);
|
||||
extern void statusmsg(char str[],int n);
|
||||
extern int place_text(int draw_text, double mx, double my);
|
||||
extern void init_inst_iterator(Iterator_ctx *ctx, double x1, double y1, double x2, double y2);
|
||||
|
|
|
|||
|
|
@ -14,10 +14,10 @@ L 4 -20 -20 -20 20 {}
|
|||
L 4 -20 20 20 0 {}
|
||||
L 4 30 -0 40 -0 {}
|
||||
L 4 20 0 30 0 {dash=3}
|
||||
B 5 37.5 -2.5 42.5 2.5 {name=Y dir=out }
|
||||
B 5 -42.5 -2.5 -37.5 2.5 {name=A dir=in }
|
||||
B 5 37.5 -2.5 42.5 2.5 {name=y dir=out }
|
||||
B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in }
|
||||
A 4 25 -0 5 180 360 {dash=3}
|
||||
T {@symname} -47.5 24 0 0 0.3 0.3 {}
|
||||
T {@name} 25 -22 0 0 0.2 0.2 {}
|
||||
T {Y} 7.5 -6.5 0 1 0.2 0.2 {}
|
||||
T {A} -17.5 -6.5 0 0 0.2 0.2 {}
|
||||
T {y} 7.5 -6.5 0 1 0.2 0.2 {}
|
||||
T {a} -17.5 -6.5 0 0 0.2 0.2 {}
|
||||
|
|
|
|||
|
|
@ -6,10 +6,10 @@ set arg1 [lindex $argv 0]
|
|||
if { $arg1 eq {inv}} {
|
||||
puts {v {xschem version=3.1.0 file_version=1.2}
|
||||
K {type=subcircuit
|
||||
verilog_primitive=true
|
||||
vhdl_primitive=true
|
||||
vhdl_format="@@y <= not @@a after 90 ps;"
|
||||
verilog_format="assign #90 @@y = ~@@a ;"
|
||||
xvhdl_primitive=true
|
||||
xverilog_primitive=true
|
||||
xvhdl_format="@@y <= not @@a after 90 ps;"
|
||||
xverilog_format="assign #90 @@y = ~@@a ;"
|
||||
format="@name @pinlist @symname wn=@wn lln=@lln wp=@wp lp=@lp"
|
||||
template="name=x1 wn=1u lln=2u wp=4u lp=2u"
|
||||
schematic=schematicgen(inv)}
|
||||
|
|
@ -29,10 +29,10 @@ T {a} -17.5 -6.5 0 0 0.2 0.2 {}
|
|||
} else {
|
||||
puts {v {xschem version=3.1.0 file_version=1.2}
|
||||
K {type=subcircuit
|
||||
verilog_primitive=true
|
||||
vhdl_primitive=true
|
||||
vhdl_format="@@y <= @@a after 90 ps;"
|
||||
verilog_format="assign #90 @@y = @@a ;"
|
||||
xvhdl_primitive=true
|
||||
xverilog_primitive=true
|
||||
xvhdl_format="@@y <= @@a after 90 ps;"
|
||||
xverilog_format="assign #90 @@y = @@a ;"
|
||||
format="@name @pinlist @symname wn=@wn lln=@lln wp=@wp lp=@lp"
|
||||
template="name=x1 wn=1u lln=2u wp=4u lp=2u"
|
||||
schematic=schematicgen(buf)}
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ C {symbolgen(inv)} 150 -460 0 0 {name=x1
|
|||
tclcommand="edit_file [abs_sym_path symbolgen]"
|
||||
ROUT=1200}
|
||||
C {lab_pin.sym} 30 -520 0 0 {name=p1 lab=IN}
|
||||
C {symbolgen(buf)} 150 -560 0 0 {name=x3
|
||||
C {symbolgen(buf,2)} 150 -560 0 0 {name=x3
|
||||
tclcommand="edit_file [abs_sym_path symbolgen]"
|
||||
ROUT=1200}
|
||||
C {lab_pin.sym} 310 -560 0 1 {name=p2 lab=IN_BUF}
|
||||
|
|
@ -103,7 +103,7 @@ schematic=schematicgen(inv)
|
|||
tclcommand="edit_file [abs_sym_path schematicgen]"}
|
||||
C {lab_pin.sym} 1120 -460 0 1 {name=p5 lab=IN_INV2}
|
||||
C {my_inv.sym} 960 -560 0 0 {name=x4 ROUT=1000
|
||||
schematic=schematicgen(buf)
|
||||
schematic="schematicgen(buf,4)"
|
||||
tclcommand="edit_file [abs_sym_path schematicgen]"}
|
||||
C {lab_pin.sym} 1120 -560 0 1 {name=p7 lab=IN_BUF2}
|
||||
C {vdd.sym} 620 -470 0 0 {name=l2 lab=VCC}
|
||||
|
|
@ -111,3 +111,4 @@ C {lab_pin.sym} 620 -440 0 1 {name=p8 lab=VCC}
|
|||
C {lab_pin.sym} 840 -520 0 0 {name=p9 lab=IN}
|
||||
C {parax_cap.sym} 1080 -550 0 0 {name=C3 gnd=0 value=100f m=1}
|
||||
C {parax_cap.sym} 1080 -450 0 0 {name=C4 gnd=0 value=100f m=1}
|
||||
C {noconn.sym} 840 -560 0 0 {name=l3}
|
||||
|
|
|
|||
Loading…
Reference in New Issue