Stefan Schippers 617d708009 verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...		2020-10-10 23:21:23 +02:00
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binto7seg	populating xschem git repo	2020-08-08 15:47:34 +02:00
devices	verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...	2020-10-10 23:21:23 +02:00
examples	small sample xschemrc fix	2020-10-06 21:59:23 +02:00
gschem_import	populating xschem git repo	2020-08-08 15:47:34 +02:00
logic	populating xschem git repo	2020-08-08 15:47:34 +02:00
ngspice	mos_power_ampli.sym and solar_panel.sch examples updated to display symbolnet names on pins	2020-10-02 15:45:30 +02:00
pcb	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
rom8k	some clarifications of steps to be taken to simulate example rom8k circuit	2020-10-08 23:24:27 +02:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
Makefile	populating xschem git repo	2020-08-08 15:47:34 +02:00