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A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
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Stefan Schippers 0ce6f6ba5d when netlisting primitive elements (not subcircuits) the "format", "verilog_format", "vhdl_format, "tedax_format" can be specified in instance attributes to override symbol. This allows to adapt primitives (example digital standard cells) to different design kits without using wrapper subcircuits. Together with "symname" redefinition in instance this allows to completely customize element netlisting. 2020-10-11 00:13:52 +02:00
XSchemWin various graphic rendering fixes for the new "view instance pin net names" function. Fixed some errors in merge schematic in callback.c and paste.c 2020-10-02 03:21:22 +02:00
doc doc updates (developer info) 2020-10-09 03:04:49 +02:00
scconfig "xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg) 2020-09-22 13:35:55 +02:00
src when netlisting primitive elements (not subcircuits) the "format", "verilog_format", "vhdl_format, "tedax_format" can be specified in instance attributes to override symbol. This allows to adapt primitives (example digital standard cells) to different design kits without using wrapper subcircuits. Together with "symname" redefinition in instance this allows to completely customize element netlisting. 2020-10-11 00:13:52 +02:00
tests better wire connecting bubble zoom scaling at different snap levels 2020-10-07 19:45:40 +02:00
xschem_library verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)... 2020-10-10 23:21:23 +02:00
.gitignore changed .gitignore for specific xschem files 2020-08-08 23:25:43 +02:00
AUTHORS populating xschem git repo 2020-08-08 15:47:34 +02:00
COPYING populating xschem git repo 2020-08-08 15:47:34 +02:00
Changelog fix Browse button in edit symbol prop dialog 2020-09-15 14:15:43 +02:00
INSTALL populating xschem git repo 2020-08-08 15:47:34 +02:00
LICENSE Update LICENSE 2020-10-10 11:44:58 +02:00
Makefile populating xschem git repo 2020-08-08 15:47:34 +02:00
Makefile.conf.in populating xschem git repo 2020-08-08 15:47:34 +02:00
README populating xschem git repo 2020-08-08 15:47:34 +02:00
README.md Update README.md 2020-10-08 00:54:06 +02:00
config.h.in populating xschem git repo 2020-08-08 15:47:34 +02:00
configure populating xschem git repo 2020-08-08 15:47:34 +02:00

README.md

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Manual and instructions