Stefan Frederik cc993bfe44 added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)		2021-01-02 20:33:34 +01:00
..
binto7seg	populating xschem git repo	2020-08-08 15:47:34 +02:00
devices	added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)	2021-01-02 20:33:34 +01:00
examples	added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements)	2021-01-02 20:33:34 +01:00
gschem_import	populating xschem git repo	2020-08-08 15:47:34 +02:00
logic	fix: avoid doing any erc checking/highlights if a schematic is explicitly loaded without linking components to symbols. This is done for instances with (spice|verilog)_stop=true attributes set to prevent unwanted symbol expansion	2020-12-23 18:16:53 +01:00
ngspice	added "auto join/trim wires" menu option since now the trim operation is doing fast even on big designs	2021-01-02 03:24:26 +01:00
pcb	"propagate_to" attribute for pins renamed to "goto"	2020-12-30 21:26:58 +01:00
rom8k	Fix: add symbol to space-hash in place_symbol() must be done before invoking symbol_bbox(); optimized eval_logic_expr()	2021-01-01 01:10:43 +01:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	example schematic updated and improvements	2021-01-01 04:24:57 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00