Fix: add symbol to space-hash in place_symbol() must be done before invoking symbol_bbox(); optimized eval_logic_expr()
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a5c4bf8aae
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b6b6bb4f27
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@ -877,8 +877,6 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
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xctx->instances++; /* must be updated before calling symbol_bbox() */
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if(xctx->prep_hash_inst) hash_inst(XINSERT, n); /* no need to rehash, add item */
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/* xctx->prep_hash_inst=0; */
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/* force these vars to 0 to trigger a prepare_netlist_structs(0) needed by symbol_bbox->translate
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@ -887,6 +885,8 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
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xctx->prep_hi_structs=0;
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symbol_bbox(n, &xctx->inst[n].x1, &xctx->inst[n].y1,
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&xctx->inst[n].x2, &xctx->inst[n].y2);
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if(xctx->prep_hash_inst) hash_inst(XINSERT, n); /* no need to rehash, add item */
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/* xctx->prep_hash_inst=0; */
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if(draw_sym & 3) bbox(ADD, xctx->inst[n].x1, xctx->inst[n].y1, xctx->inst[n].x2, xctx->inst[n].y2);
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set_modify(1);
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if(draw_sym&1) {
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@ -898,31 +898,32 @@ void print_stack(int *stack, int sp)
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int eval_logic_expr(int inst, int output)
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{
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int stack[STACKMAX];
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int i, sp = 0;
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char *saveptr = NULL;
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char *ptr1;
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char *ptr2;
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char *arg;
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int pos = 0, i, sp = 0;
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char *str;
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int res = 0;
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my_strdup(827, &saveptr, xctx->simdata.inst[inst].pin[output].function);
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dbg(1, "eval_logic_expr(): inst=%d pin=%d function=%s\n", inst, output, saveptr ? saveptr : "NULL");
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if(!saveptr) return 2; /* no logic function defined, return LOGIC_X */
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ptr2 = saveptr;
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while( (arg = my_strtok_r(ptr2, " ", &ptr1)) ) {
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ptr2 = NULL;
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if(arg[0] == 'd') { /* duplicate top element*/
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str = xctx->simdata.inst[inst].pin[output].function;
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dbg(1, "eval_logic_expr(): inst=%d pin=%d function=%s\n", inst, output, str ? str : "NULL");
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if(!str) return 2; /* no logic function defined, return LOGIC_X */
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while(str[pos]) {
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if(str[pos] == 'd') { /* duplicate top element*/
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if(sp > 0 && sp < STACKMAX) {
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stack[sp] = stack[sp - 1];
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sp++;
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}
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} else if(arg[0] == '~') { /* negation operator */
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} else if(str[pos] == 'x') { /* exchange top 2 operands */
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if(sp > 1) {
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int tmp = stack[sp - 2];
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stack[sp - 2] = stack[sp - 1];
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stack[sp - 1] = tmp;
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}
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} else if(str[pos] == '~') { /* negation operator */
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if(sp > 0) {
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sp--;
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if(stack[sp] != 2) stack[sp] = !stack[sp];
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++sp;
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}
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} else if(arg[0] == '|') { /* or operator */
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} else if(str[pos] == '|') { /* or operator */
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if(sp > 1) {
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res = 0;
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for(i = sp - 2; i < sp; i++) {
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@ -936,7 +937,7 @@ int eval_logic_expr(int inst, int output)
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stack[sp - 2] = res;
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sp--;
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}
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} else if(arg[0] == '&') { /* and operator */
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} else if(str[pos] == '&') { /* and operator */
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if(sp > 1) {
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res = 1;
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for(i = sp - 2; i < sp; i++) {
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@ -950,7 +951,7 @@ int eval_logic_expr(int inst, int output)
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stack[sp - 2] = res;
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sp--;
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}
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} else if(arg[0] == '^') { /* xor operator */
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} else if(str[pos] == '^') { /* xor operator */
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if(sp > 1) {
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res = 0;
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for(i = sp - 2; i < sp; i++) {
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@ -965,22 +966,25 @@ int eval_logic_expr(int inst, int output)
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stack[sp - 2] = res;
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sp--;
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}
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} else if(arg[0] == 'L') { /* logic low (0) */
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} else if(str[pos] == 'L') { /* logic low (0) */
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if(sp < STACKMAX) {
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stack[sp++] = 0;
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}
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} else if(arg[0] == 'H') { /* logic high (1) */
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} else if(str[pos] == 'H') { /* logic high (1) */
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if(sp < STACKMAX) {
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stack[sp++] = 1;
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}
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} else if(isdigit(arg[0])) {
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} else if(isdigit(str[pos])) {
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if(sp < STACKMAX) {
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stack[sp++] = get_logic_value(inst, atoi(arg));
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char *num = str + pos;
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while(isdigit(str[++pos])) ;
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pos--; /* push back last non digit character */
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stack[sp++] = get_logic_value(inst, atoi(num));
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}
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else dbg(0, "eval_logic_expr(): stack overflow!\n");
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}
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pos++;
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}
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my_free(1218, &saveptr);
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dbg(1, "eval_logic_expr(): inst %d output %d, returning %d\n", inst, output, stack[0]);
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return stack[0];
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}
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@ -1,5 +1,7 @@
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v {xschem version=2.9.5_RC6 file_version=1.1}
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G {type=subcircuit
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v {xschem version=2.9.9 file_version=1.2 }
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G {}
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K {type=subcircuit
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function0="1 2 & ~"
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @VCCPIN @VSSPIN @symname wna=@wna lna=@lna wpa=@wpa lpa=@lpa wnb=@wnb lnb=@lnb wpb=@wpb lpb=@lpb m=@m"
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@ -38,8 +40,8 @@ L 4 22.5 -22.5 30 -15 {}
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L 4 30 -15 33.75 -7.5 {}
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L 4 33.75 -7.5 35 0 {}
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B 5 57.5 -2.5 62.5 2.5 {name=y dir=out verilog_type=wire}
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B 5 -42.5 -22.5 -37.5 -17.5 {name=a dir=in}
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B 5 -42.5 17.5 -37.5 22.5 {name=b dir=in}
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B 5 -42.5 -22.5 -37.5 -17.5 {name=a dir=in goto=0}
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B 5 -42.5 17.5 -37.5 22.5 {name=b dir=in goto=0}
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T {na:@wna\\/@lna
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nb:@wnb\\/@lnb} -35 65 2 1 0.2 0.2 {}
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T {pa:@wpa\\/@lpa
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@ -1,5 +1,7 @@
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v {xschem version=2.9.7 file_version=1.2}
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G {type=subcircuit
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v {xschem version=2.9.9 file_version=1.2 }
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G {}
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K {type=subcircuit
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function0="1 ~"
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vhdl_stop=true
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verilog_stop=true
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format="@name @pinlist @VCCPIN @VSSPIN @symname wn=@wn lln=@lln wp=@wp lp=@lp m=@m"
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@ -26,7 +28,7 @@ L 4 18.75 5 23.75 5 {}
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L 4 16.25 2.5 18.75 5 {}
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L 4 26.25 0 40 0 {}
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B 5 37.5 -2.5 42.5 2.5 {name=y dir=out verilog_type=wire}
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B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in}
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B 5 -42.5 -2.5 -37.5 2.5 {name=a dir=in goto=0}
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T {n:@wn\\/@lln} -35 35 2 1 0.2 0.2 {}
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T {p:@wp\\/@lp} -35 -22.5 2 1 0.2 0.2 {}
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T {@name} -26.25 -5 0 0 0.2 0.2 {}
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