stef
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7d8ce2f9ad
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remove spaces on line ends, brace expr tcl expression when possible, resize rectangle in intuitive interface made easier at far zoom levels
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2025-12-13 11:51:05 +01:00 |
stefan schippers
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20359ed43e
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update license info. Remove unneeded newline saving in version line of .sch/.sym files, remove c89 flag based on lib versions
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2024-11-12 20:23:18 +01:00 |
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stefan schippers
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5c22d26072
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update copyright info to 2023
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2023-05-21 12:52:19 +02:00 |
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Stefan Frederik
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3f627123b2
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persists highlights on instances: remove highlighted instance from hash if user selects and presses ctrl-k as it is done for nets. Avoid instance highlight to also highlight net with identical name (example instance x1 and net x1). Verilog and Vhdl netlists handle duplicated (pass-through) pins
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2022-10-11 13:12:17 +02:00 |
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Stefan Frederik
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b7c7c336dd
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added vhdl_sym_def, spice_sym_def, verilog_sym_def attributes for symbols. If defined and not empty the corresponding netlister will insert the content of the attribute instead of the subcircuit schematic implementation. Typically used to include a definition file. Updated documentation
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2022-09-29 11:59:43 +02:00 |
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Stefan Frederik
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cd7eb3ab54
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update license info
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2022-06-24 00:36:12 +02:00 |
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Stefan Frederik
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be43fe41b0
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added bit blasting option (default: disabled) in menu for verilog netlists: group bit slices in instance net assignments. Doc updates (FSiC-2022)
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2022-06-14 10:20:06 +02:00 |
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Stefan Frederik
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28cc187b56
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when placing components with lock=true set in template attribute allow to move it to its final position like any other unlocked symbol. Code in place in verilog.awk to do bit unblasting in net-> port associations, but not enalbed it for now as icarus verilog does not handle some bus slices (for example if bus slice direction is different from declared bus direction)
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2022-06-09 09:32:34 +02:00 |
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Stefan Frederik
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ba15e21b24
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preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking
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2021-12-15 15:17:45 +01:00 |
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Stefan Frederik
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00311e7ff1
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update license info
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2021-07-27 16:42:54 +02:00 |
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Stefan Schippers
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35c2d0fa93
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better node multiplicity detection in spice and verilog awk netlist post-processors (\?-?[0-9]+)
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2020-10-16 00:13:39 +02:00 |
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Stefan Schippers
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c87f44a441
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added "xchem load_symbol" command to load a symbol without binding to any instance, text edit attribute "Load" button will start in "$current_dirname"
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2020-10-15 15:37:06 +02:00 |
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Stefan Schippers
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4362c44a8d
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fix various regressions: escape the ? pattern in awk, be more selective in ? node multiplicity tag recognition in spice.awk, yet some more fixes in abs_sym_path thanks to JL
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2020-10-15 13:38:27 +02:00 |
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Stefan Schippers
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e82f270f61
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replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary.
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2020-10-14 23:15:05 +02:00 |
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Stefan SChippers
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5e8df730a0
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |