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xschem
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remove spaces on line ends, brace expr tcl expression when possible, resize rectangle in intuitive interface made easier at far zoom levels

This commit is contained in:
stef 2025-12-13 11:51:05 +01:00
parent 688f5fd128
commit 7d8ce2f9ad
97 changed files with 2625 additions and 2625 deletions
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6
scconfig/hooks.c
View File

@ -280,12 +280,12 @@ int hook_detect_target()
append("cc/cflags", " ");
append("cc/cflags", get("cc/argstd/Wall"));
}
if (require("cc/argstd/std_c89", 0, 0) == 0) {
append("cc/cflags", " ");
append("cc/cflags", get("cc/argstd/std_c89"));
}
if (require("cc/argstd/pedantic", 0, 0) == 0) {
append("cc/cflags", " ");
append("cc/cflags", get("cc/argstd/pedantic"));
@ -305,7 +305,7 @@ int hook_detect_target()
append("cc/ldflags", get("cc/argstd/pg"));
}
/* no-pie no more needed it seems */
/*
/*
if (require("cc/argstd/no-pie", 0, 0) == 0) {
append("cc/cflags", " ");
append("cc/cflags", get("cc/argstd/no-pie"));

226
src/actions.c
View File

@ -33,9 +33,9 @@ void here(double i)
/* super simple 32 bit hashing function for files
* It is suppoded to be used on text files.
* Calculates the same hash on windows (crlf) and unix (lf) text files.
* If you want high collision resistance and
* If you want high collision resistance and
* avoid 'birthday problem' collisions use a better hash function, like md5sum
* or sha256sum
* or sha256sum
*/
unsigned int hash_file(const char *f, int skip_path_lines)
{
@ -107,8 +107,8 @@ const char *get_text_floater(int i)
if(!xctx->floater_inst_table.table) {
floater_hash_all_names();
}
if(xctx->text[i].floater_instname)
if(xctx->text[i].floater_instname)
instname = xctx->text[i].floater_instname;
else {
instname = get_tok_value(xctx->text[i].prop_ptr, "name", 0);
@ -128,7 +128,7 @@ const char *get_text_floater(int i)
}
dbg(1, "floater: %s\n",txt_ptr);
} else {
/* do just a tcl substitution if floater does not reference an existing instance
/* do just a tcl substitution if floater does not reference an existing instance
* (but name=something or floater=something attribute must be present) and text
* matches tcleval(...) or contains '@' */
if(strstr(txt_ptr, "tcleval(") == txt_ptr || strchr(txt_ptr, '@')) {
@ -139,7 +139,7 @@ const char *get_text_floater(int i)
}
}
return txt_ptr;
}
}
/* mod:
* 0 : clear modified flag, update title and tab names, upd. simulation button colors.
@ -154,7 +154,7 @@ const char *get_text_floater(int i)
int set_modify(int mod)
{
int i, floaters = 0;
dbg(1, "set_modify(): %d, prev_set_modify=%d\n", mod, xctx->prev_set_modify);
/* set modify state */
@ -187,8 +187,8 @@ int set_modify(int mod)
tclvareval("catch {", xctx->top_path, ".menubar entryconfigure Waves -background $simulate_bg}", NULL);
}
}
}
}
/* clear floater caches */
if(mod == 1 || mod == -2 || mod == -1) {
for(i = 0; i < xctx->texts; i++)
@ -279,7 +279,7 @@ char *escape_chars(const char *source, const char *charset)
dest[d++] = source[s];
}
} else {
if(strchr(charset, source[s])) {
if(strchr(charset, source[s])) {
dest[d++] = '\\';
dest[d++] = source[s];
} else {
@ -337,15 +337,15 @@ void set_grid(double newgrid)
}
/*
/*
*
*
*
* what==0: force creation of $netlist_dir (if netlist_dir variable not empty)
* and return current setting.
*
*
* what==1: if no dir given prompt user
* else set netlist_dir to dir
*
* else set netlist_dir to dir
*
* what==2: just set netlist_dir according to local_netlist_dir setting
*/
int set_netlist_dir(int what, const char *dir)
@ -363,9 +363,9 @@ int set_netlist_dir(int what, const char *dir)
/* wrapper to TCL function */
/* remove parameter section of symbol generator before calculating abs path : xxx(a,b) -> xxx */
const char *sanitized_abs_sym_path(const char *s, const char *ext)
{
{
char c[PATH_MAX+1000];
my_snprintf(c, S(c), "abs_sym_path [regsub {\\(.*} {%s} {}] {%s}", s, ext);
tcleval(c);
return tclresult();
@ -493,12 +493,12 @@ void new_xschem_process(const char* cell, int symbol)
ZeroMemory(&si, sizeof(si));
si.cb = sizeof(si);
ZeroMemory(&pi, sizeof(pi));
/* "detach" (-b) is not processed for Windows, so
/* "detach" (-b) is not processed for Windows, so
use DETACHED_PROCESS in CreateProcessA to not create
a TCL shell
*/
if (!cell || !cell[0]) {
if (!symbol)
if (!cell || !cell[0]) {
if (!symbol)
my_snprintf(cmd_line, S(cmd_line), "%s -b -s --tcl \"set XSCHEM_START_WINDOW {}\"", xschem_executable);
else
my_snprintf(cmd_line, S(cmd_line), "%s -b -y --tcl \"set XSCHEM_START_WINDOW {}\"", xschem_executable);
@ -537,7 +537,7 @@ const char *get_file_path(char *f)
* 1 : file saved or not needed to save since no change
* -1 : user cancel
* 0 : file not saved due to errors or per user request
* confirm:
* confirm:
* 0 : do not ask user to save
* 1 : ask user to save
* fast:
@ -557,7 +557,7 @@ int save(int confirm, int fast)
force = 1;
confirm = 0;
}
}
}
if(force || xctx->modified)
{
@ -624,7 +624,7 @@ void ask_new_file(int in_new_window, char *filename)
char win_path[WINDOW_PATH_SIZE];
int skip = 0;
dbg(1, "ask_new_file(): load: f=%s\n", f);
if(check_loaded(f, win_path) && !filename &&
xctx->current_win_path && strcmp(win_path, xctx->current_win_path)) {
char msg[PATH_MAX + 100];
@ -687,7 +687,7 @@ void remove_symbol(int j)
}
my_free(_ALLOC_ID_, &xctx->sym[j].poly[c]);
xctx->sym[j].polygons[c] = 0;
for(i=0;i<xctx->sym[j].lines[c]; ++i) {
if(xctx->sym[j].line[c][i].prop_ptr != NULL) {
my_free(_ALLOC_ID_, &xctx->sym[j].line[c][i].prop_ptr);
@ -695,7 +695,7 @@ void remove_symbol(int j)
}
my_free(_ALLOC_ID_, &xctx->sym[j].line[c]);
xctx->sym[j].lines[c] = 0;
for(i=0;i<xctx->sym[j].arcs[c]; ++i) {
if(xctx->sym[j].arc[c][i].prop_ptr != NULL) {
my_free(_ALLOC_ID_, &xctx->sym[j].arc[c][i].prop_ptr);
@ -703,7 +703,7 @@ void remove_symbol(int j)
}
my_free(_ALLOC_ID_, &xctx->sym[j].arc[c]);
xctx->sym[j].arcs[c] = 0;
for(i=0;i<xctx->sym[j].rects[c]; ++i) {
if(xctx->sym[j].rect[c][i].prop_ptr != NULL) {
my_free(_ALLOC_ID_, &xctx->sym[j].rect[c][i].prop_ptr);
@ -822,7 +822,7 @@ int set_sym_flags(xSymbol *sym)
sym->flags |= SPECTRE_SHORT;
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
sym->flags |= SPECTRE_IGNORE;
ptr = get_tok_value(sym->prop_ptr,"verilog_ignore",0);
if(!strcmp(ptr, "short"))
sym->flags |= VERILOG_SHORT;
@ -869,7 +869,7 @@ int set_inst_flags(xInstance *inst)
inst->flags |= HIDE_INST;
if(!strboolcmp(get_tok_value(inst->prop_ptr,"hide_texts",0), "true"))
inst->flags |= HIDE_SYMBOL_TEXTS;
ptr = get_tok_value(inst->prop_ptr,"spice_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= SPICE_SHORT;
@ -881,25 +881,25 @@ int set_inst_flags(xInstance *inst)
inst->flags |= SPECTRE_SHORT;
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= SPECTRE_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"verilog_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= VERILOG_SHORT;
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= VERILOG_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"vhdl_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= VHDL_SHORT;
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= VHDL_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"tedax_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= TEDAX_SHORT;
else if(!strboolcmp(ptr, "true") || !strcmp(ptr, "open"))
inst->flags |= TEDAX_IGNORE;
ptr = get_tok_value(inst->prop_ptr,"lvs_ignore",0);
if(!strcmp(ptr, "short"))
inst->flags |= LVS_IGNORE_SHORT;
@ -958,13 +958,13 @@ void reset_caches(void)
dbg(1, "reset_caches()\n");
for(i = 0; i < xctx->instances; i++) {
set_inst_flags(&xctx->inst[i]);
}
for(i = 0; i < xctx->symbols; i++) {
}
for(i = 0; i < xctx->symbols; i++) {
set_sym_flags(&xctx->sym[i]);
}
}
}
/* what:
/* what:
* 1: create
* 0: clear
*/
@ -1151,7 +1151,7 @@ int connect_by_kissing(void)
wptr = wptr->next;
}
if(kissing) {
if(!done_undo) {
xctx->push_undo();
done_undo = 1;
@ -1339,7 +1339,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
my_strdup(_ALLOC_ID_, &prop, xctx->inst[xctx->sel_array[j].n].instname);
my_strcat(_ALLOC_ID_, &prop, "_");
tclsetvar("custom_label_prefix",prop);
if(interactive == 1 && !do_all_inst) {
dbg(1,"attach_labels_to_inst(): invoking tcl attach_labels_to_inst\n");
tcleval("attach_labels_to_inst");
@ -1369,7 +1369,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
xctx->inst[xctx->sel_array[j].n].x0,
xctx->inst[xctx->sel_array[j].n].y0,
xctx->sym[xctx->inst[xctx->sel_array[j].n].ptr].name);
x0 = xctx->inst[xctx->sel_array[j].n].x0;
y0 = xctx->inst[xctx->sel_array[j].n].y0;
rot = xctx->inst[xctx->sel_array[j].n].rot;
@ -1377,29 +1377,29 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
symbol = xctx->sym + xctx->inst[xctx->sel_array[j].n].ptr;
npin = symbol->rects[PINLAYER];
rct=symbol->rect[PINLAYER];
for(i=0;i<npin; ++i) {
my_strdup(_ALLOC_ID_, &labname,get_tok_value(rct[i].prop_ptr,"name",1));
dbg(1,"attach_labels_to_inst(): 2 --> labname=%s\n", labname);
pinx0 = (rct[i].x1+rct[i].x2)/2;
piny0 = (rct[i].y1+rct[i].y2)/2;
if(strcmp(get_tok_value(rct[i].prop_ptr,"dir",0),"in")) dir=1; /* out or inout pin */
else dir=0; /* input pin */
/* opin or iopin on left of symbol--> reverse orientation 20171205 */
if(rotated_text ==-1 && dir==1 && pinx0<0) dir=0;
ROTATION(rot, flip, 0.0, 0.0, pinx0, piny0, pinx0, piny0);
pinx0 += x0;
piny0 += y0;
get_square(pinx0, piny0, &sqx, &sqy);
iptr=xctx->instpin_spatial_table[sqx][sqy];
wptr=xctx->wire_spatial_table[sqx][sqy];
skip=0;
while(iptr) {
ii = iptr->n;
@ -1407,7 +1407,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
iptr = iptr->next;
continue;
}
if( iptr->x0 == pinx0 && iptr->y0 == piny0 ) {
skip=1;
break;
@ -1428,7 +1428,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
my_strcat(_ALLOC_ID_, &prop, (char *)tclgetvar("custom_label_prefix"));
}
/* /20171005 */
my_strcat(_ALLOC_ID_, &prop, labname);
dir ^= flip; /* 20101129 20111030 */
if(rotated_text ==-1) {
@ -1466,7 +1466,7 @@ void attach_labels_to_inst(int interactive) /* offloaded from callback.c 201710
}
/* if hilights are present in schematic propagate to new added labels */
if(xctx->hilight_nets) {
propagate_hilights(1, 0, XINSERT_NOREPLACE);
propagate_hilights(1, 0, XINSERT_NOREPLACE);
redraw_hilights(0);
}
my_free(_ALLOC_ID_, &symname_pin);
@ -1603,7 +1603,7 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
}
dbg(1, "place_symbol(): done set_inst_prop()\n"); /* 03-02-2000 */
xctx->instances++;/* translate expects the correct balue of xctx->instances */
/* After having assigned prop_ptr to new instance translate symbol reference
* to resolve @params --> res.tcl(@value\) --> res.tcl(100) */
@ -1647,10 +1647,10 @@ int place_symbol(int pos, const char *symbol_name, double x, double y, short rot
dbg(0, "%s", msg);
if(has_x) tclvareval("alert_ {", msg, "} {} 1", NULL);
#if 1
if(xctx->inst[n].instname) my_free(_ALLOC_ID_, &xctx->inst[n].instname);
if(xctx->inst[n].name) my_free(_ALLOC_ID_, &xctx->inst[n].name);
if(xctx->inst[n].prop_ptr) my_free(_ALLOC_ID_, &xctx->inst[n].prop_ptr);
if(xctx->inst[n].lab) my_free(_ALLOC_ID_, &xctx->inst[n].lab);
if(xctx->inst[n].instname) my_free(_ALLOC_ID_, &xctx->inst[n].instname);
if(xctx->inst[n].name) my_free(_ALLOC_ID_, &xctx->inst[n].name);
if(xctx->inst[n].prop_ptr) my_free(_ALLOC_ID_, &xctx->inst[n].prop_ptr);
if(xctx->inst[n].lab) my_free(_ALLOC_ID_, &xctx->inst[n].lab);
if(prop) my_free(_ALLOC_ID_, &prop);
xctx->instances--;
return 0;
@ -1701,7 +1701,7 @@ void symbol_in_new_window(int new_process)
char filename[PATH_MAX];
char win_path[WINDOW_PATH_SIZE];
rebuild_selected_array();
if(xctx->lastsel !=1 || xctx->sel_array[0].type!=ELEMENT) {
if(tclgetboolvar("search_schematic")) {
my_strncpy(filename, abs_sym_path(xctx->current_name, ".sym"), S(filename));
@ -1736,7 +1736,7 @@ int copy_hierarchy_data(const char *from_win_path, const char *to_win_path)
Str_hashentry **fromnext;
Str_hashentry **tonext;
if(!get_window_count()) { return 0; }
save_xctx = get_save_xctx();
n = get_tab_or_window_number(from_win_path);
@ -1889,7 +1889,7 @@ void launcher(void)
}
/* get symbol reference of instance 'inst', looking into
/* get symbol reference of instance 'inst', looking into
* instance 'schematic' attribute (and appending '.sym') if set
* or get it from inst[inst].name.
* perform tcl substitution of the result and
@ -1904,9 +1904,9 @@ const char *get_sym_name(int inst, int ndir, int ext, int abs_path)
/* resolve schematic=generator.tcl( @n ) where n=11 is defined in instance attrs */
my_strdup2(_ALLOC_ID_, &sch, get_tok_value(xctx->inst[inst].prop_ptr,"schematic", 6));
schematic_token_found = xctx->tok_size;
if(sch && sch[0])
if(sch && sch[0])
my_strdup2(_ALLOC_ID_, &sch, translate3(sch, 1, xctx->inst[inst].prop_ptr, NULL, NULL, NULL));
if(sch && sch[0])
if(sch && sch[0])
my_strdup2(_ALLOC_ID_, &sch, tcl_hook2(
str_replace(sch, "@symname", get_cell(xctx->inst[inst].name, 0), '\\', -1)));
@ -1916,12 +1916,12 @@ const char *get_sym_name(int inst, int ndir, int ext, int abs_path)
*/
dbg(1, "get_sym_name(): sch=%s\n", sch);
if(schematic_token_found) { /* token exists */
if(schematic_token_found) { /* token exists */
if(abs_path)
sym = abs_sym_path(sch, ".sym");
else
sym = add_ext(rel_sym_path(sch), ".sym");
}
}
else {
if(abs_path)
sym = abs_sym_path(tcl_hook2(xctx->inst[inst].name), "");
@ -1937,7 +1937,7 @@ const char *get_sym_name(int inst, int ndir, int ext, int abs_path)
void copy_symbol(xSymbol *dest_sym, xSymbol *src_sym)
{
int c, j;
dest_sym->minx = src_sym->minx;
dest_sym->maxx = src_sym->maxx;
dest_sym->miny = src_sym->miny;
@ -1974,14 +1974,14 @@ void copy_symbol(xSymbol *dest_sym, xSymbol *src_sym)
for(c = 0;c<cadlayers; ++c) {
/* symbol lines */
dest_sym->line[c] = my_calloc(_ALLOC_ID_, src_sym->lines[c], sizeof(xLine));
for(j = 0; j < src_sym->lines[c]; ++j) {
for(j = 0; j < src_sym->lines[c]; ++j) {
dest_sym->line[c][j] = src_sym->line[c][j];
dest_sym->line[c][j].prop_ptr = NULL;
my_strdup(_ALLOC_ID_, &dest_sym->line[c][j].prop_ptr, src_sym->line[c][j].prop_ptr);
}
/* symbol rects */
dest_sym->rect[c] = my_calloc(_ALLOC_ID_, src_sym->rects[c], sizeof(xRect));
for(j = 0; j < src_sym->rects[c]; ++j) {
for(j = 0; j < src_sym->rects[c]; ++j) {
dest_sym->rect[c][j] = src_sym->rect[c][j];
dest_sym->rect[c][j].prop_ptr = NULL;
dest_sym->rect[c][j].extraptr = NULL;
@ -1989,14 +1989,14 @@ void copy_symbol(xSymbol *dest_sym, xSymbol *src_sym)
}
/* symbol arcs */
dest_sym->arc[c] = my_calloc(_ALLOC_ID_, src_sym->arcs[c], sizeof(xArc));
for(j = 0; j < src_sym->arcs[c]; ++j) {
for(j = 0; j < src_sym->arcs[c]; ++j) {
dest_sym->arc[c][j] = src_sym->arc[c][j];
dest_sym->arc[c][j].prop_ptr = NULL;
my_strdup(_ALLOC_ID_, &dest_sym->arc[c][j].prop_ptr, src_sym->arc[c][j].prop_ptr);
}
/* symbol polygons */
dest_sym->poly[c] = my_calloc(_ALLOC_ID_, src_sym->polygons[c], sizeof(xPoly));
for(j = 0; j < src_sym->polygons[c]; ++j) {
for(j = 0; j < src_sym->polygons[c]; ++j) {
int points = src_sym->poly[c][j].points;
dest_sym->poly[c][j] = src_sym->poly[c][j];
dest_sym->poly[c][j].prop_ptr = NULL;
@ -2025,7 +2025,7 @@ void copy_symbol(xSymbol *dest_sym, xSymbol *src_sym)
my_strdup2(_ALLOC_ID_, &dest_sym->text[j].font, src_sym->text[j].font);
my_strdup2(_ALLOC_ID_, &dest_sym->text[j].floater_instname, src_sym->text[j].floater_instname);
}
}
}
void toggle_ignore(void)
{
@ -2057,7 +2057,7 @@ void toggle_ignore(void)
else if(flag == 1) flag = 2;
else flag = 0;
if(flag == 1) {
my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, subst_token(xctx->inst[i].prop_ptr, attr, "true"));
} else if(flag == 2) {
@ -2104,7 +2104,7 @@ void get_additional_symbols(int what)
char *sch = NULL;
char symbol_base_sch[PATH_MAX] = "";
size_t schematic_token_found = 0;
if(xctx->inst[i].ptr < 0) continue;
dbg(1, "get_additional_symbols(): inst=%d (%s) sch=%s\n",i, xctx->inst[i].name, sch);
/* copy instance based *_sym_def attributes to symbol */
@ -2120,7 +2120,7 @@ void get_additional_symbols(int what)
my_strdup2(_ALLOC_ID_, &sch, translate3(sch, 1, xctx->inst[i].prop_ptr, NULL, NULL, NULL));
dbg(1, " get_additional_symbols(): sch=%s tok_size= %ld\n", sch, xctx->tok_size);
my_strdup2(_ALLOC_ID_, &sch, tcl_hook2(
str_replace(sch, "@symname", get_cell(xctx->inst[i].name, 0), '\\', -1)));
dbg(1, " get_additional_symbols(): sch=%s\n", sch);
@ -2155,13 +2155,13 @@ void get_additional_symbols(int what)
my_mstrcat(_ALLOC_ID_, &symname_attr, "symname=", get_cell(sym, 0), NULL);
my_mstrcat(_ALLOC_ID_, &symname_attr, " symref=", get_sym_name(i, 9999, 1, 1), NULL);
my_strdup(_ALLOC_ID_, &spice_sym_def,
my_strdup(_ALLOC_ID_, &spice_sym_def,
translate3(spice_sym_def, 1, xctx->inst[i].prop_ptr,
symptr->templ,
symptr->templ,
symname_attr, NULL));
my_strdup(_ALLOC_ID_, &spectre_sym_def,
my_strdup(_ALLOC_ID_, &spectre_sym_def,
translate3(spectre_sym_def, 1, xctx->inst[i].prop_ptr,
symptr->templ,
symptr->templ,
symname_attr, NULL));
my_free(_ALLOC_ID_, &symname_attr);
/* if instance symbol has default_schematic set to ignore copy the symbol anyway, since
@ -2180,7 +2180,7 @@ void get_additional_symbols(int what)
/* the copied symbol will not inherit the default_schematic attribute otherwise it will also
* be skipped */
if(default_schematic) {
my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr,
subst_token(xctx->sym[j].prop_ptr, "default_schematic", NULL)); /* delete attribute */
}
/* if symbol has no corresponding schematic file use symbol base schematic */
@ -2189,11 +2189,11 @@ void get_additional_symbols(int what)
subst_token(xctx->sym[j].prop_ptr, "schematic", symbol_base_sch));
}
if(spice_sym_def) {
my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr,
subst_token(xctx->sym[j].prop_ptr, "spice_sym_def", spice_sym_def));
}
if(spectre_sym_def) {
my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->sym[j].prop_ptr,
subst_token(xctx->sym[j].prop_ptr, "spectre_sym_def", spectre_sym_def));
}
if(verilog_sym_def) {
@ -2263,7 +2263,7 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst, int fallback)
/* instance based symbol selection */
/* resolve schematic=generator.tcl( @n ) where n=11 is defined in instance attrs */
my_strdup2(_ALLOC_ID_, &str_tmp, get_tok_value(xctx->inst[inst].prop_ptr,"schematic", 6));
if(str_tmp[0])
if(str_tmp[0])
my_strdup2(_ALLOC_ID_, &str_tmp, translate3(str_tmp, 1, xctx->inst[inst].prop_ptr, NULL, NULL, NULL));
/*
* my_strdup(_ALLOC_ID_, &str_tmp, translate3(get_tok_value(xctx->inst[inst].prop_ptr,"schematic", 6),
@ -2286,7 +2286,7 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst, int fallback)
else my_strncpy(filename, abs_sym_path(sch, ""), PATH_MAX);
}
}
if(has_x && fallback && !is_gen && filename[0]) {
file_exists = !stat(filename, &buf);
if(!file_exists) {
@ -2339,7 +2339,7 @@ void get_sch_from_sym(char *filename, xSymbol *sym, int inst, int fallback)
dbg(1, "get_sch_from_sym(): sym->name=%s, filename=%s\n", sym->name, filename);
}
/* When descended into an i-th instance of a vector instance this function allows
/* When descended into an i-th instance of a vector instance this function allows
* to change the path to the j-th instance. the instnumber parameters follows the same rules
* as descend_schematic() */
int change_sch_path(int instnumber, int dr)
@ -2389,7 +2389,7 @@ int change_sch_path(int instnumber, int dr)
* if set_title == 0 do not set window title (faster)
* == 1 do set_title
* == 2 do not process instance pins/nets
* == 4 do not descend into i-th instance of vecrtor instance. just
* == 4 do not descend into i-th instance of vecrtor instance. just
* concatenate instance name as is to path and descend.
* above flags can be ORed together */
int descend_schematic(int instnumber, int fallback, int alert, int set_title)
@ -2416,7 +2416,7 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
{
char cmd[PATH_MAX+1000];
char res[PATH_MAX];
my_strncpy(filename, xctx->sch[xctx->currsch], S(filename));
my_snprintf(cmd, S(cmd), "save_file_dialog {Save file} * INITIALLOADDIR {%s}", filename);
tcleval(cmd);
@ -2439,12 +2439,12 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
) return 0;
if(xctx->modified) {
int ret;
ret = save(1, 0);
/* if circuit is changed but not saved before descending
* state will be inconsistent when returning, can not propagare hilights
* save() return value:
* 1 : file saved
* 1 : file saved
* -1 : user cancel
* 0 : file not saved due to errors or per user request
*/
@ -2453,7 +2453,7 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
}
/* build up current hierarchy path */
dbg(1, "descend_schematic(): selected instname=%s\n", xctx->inst[n].instname);
if(xctx->inst[n].instname && xctx->inst[n].instname[0]) {
if(set_title & 4) {
my_strdup2(_ALLOC_ID_, &str, xctx->inst[n].instname);
@ -2532,10 +2532,10 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
my_free(_ALLOC_ID_, &pin_node);
}
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].prop_ptr,
xctx->inst[n].prop_ptr);
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].templ, xctx->sym[xctx->inst[n].ptr].templ);
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].sym_extra,
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].sym_extra,
get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "extra", 0));
dbg(1,"descend_schematic(): inst_number=%d\n", inst_number);
@ -2546,7 +2546,7 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
xctx->sch_inst_number[xctx->currsch] = inst_number;
dbg(1, "descend_schematic(): current path: %s\n", xctx->sch_path[xctx->currsch+1]);
dbg(1, "descend_schematic(): inst_number=%d\n", inst_number);
xctx->previous_instance[xctx->currsch]=n;
xctx->zoom_array[xctx->currsch].x=xctx->xorigin;
xctx->zoom_array[xctx->currsch].y=xctx->yorigin;
@ -2564,7 +2564,7 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
propagate_hilights(1, 0, XINSERT_NOREPLACE);
}
dbg(1, "descend_schematic(): before zoom(): prep_hash_inst=%d\n", xctx->prep_hash_inst);
if(xctx->rects[GRIDLAYER] > 0 && tcleval("info exists ngspice::ngspice_data")[0] == '0') {
Graph_ctx *gr = &xctx->graph_struct;
xRect *r = &xctx->rect[GRIDLAYER][0];
@ -2580,8 +2580,8 @@ int descend_schematic(int instnumber, int fallback, int alert, int set_title)
return descend_ok;
}
/*
* what:
/*
* what:
* 1: ask gui user confirm if schematic modified
* 2: do *NOT* reset window title
*/
@ -2609,7 +2609,7 @@ void go_back(int what)
else if(!strcmp(tclresult(), "") ) return;
}
/* do not automatically save if confirm==0. Script developers should take care of this */
/*
/*
* else {
* save_ok = save_schematic(xctx->sch[xctx->currsch], 0);
* }
@ -2649,7 +2649,7 @@ void go_back(int what)
xctx->modified=save_modified; /* to force ask save embedded sym in parent schematic */
if(xctx->hilight_nets) {
if(prev_sch_type != CAD_SYMBOL_ATTRS) hilight_parent_pins();
if(prev_sch_type != CAD_SYMBOL_ATTRS) hilight_parent_pins();
propagate_hilights(1, 1, XINSERT_NOREPLACE);
}
xctx->xorigin=xctx->zoom_array[xctx->currsch].x;
@ -2788,7 +2788,7 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
{
if(selected == 1 && !xctx->rect[c][i].sel) continue;
/* skip graph objects if no datafile loaded */
if(c == GRIDLAYER && xctx->rect[c][i].flags) {
if(c == GRIDLAYER && xctx->rect[c][i].flags) {
if(hide_graphs && !waves) continue;
}
rect.x1=xctx->rect[c][i].x1;
@ -2809,7 +2809,7 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
* str = get_tok_value(xctx->wire[i].prop_ptr, "lab",0);
* if(!str[0] || !bus_hilight_hash_lookup(str, 0,XLOOKUP)) continue;
*/
if(!xctx->hilight_nets || !xctx->wire[i].node ||
if(!xctx->hilight_nets || !xctx->wire[i].node ||
!xctx->wire[i].node[0] || !bus_hilight_hash_lookup(xctx->wire[i].node, 0,XLOOKUP)) continue;
}
if(xctx->wire[i].bus == -1.0){
@ -2830,8 +2830,8 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
}
if(has_x && selected != 2) {
for(i=0;i<xctx->texts; ++i)
{
int no_of_lines;
{
int no_of_lines;
double longest_line;
if(selected == 1 && !xctx->text[i].sel) continue;
@ -3109,11 +3109,11 @@ void draw_stuff(void)
#ifdef STORE
xctx->rectcolor = (int) (16.0*rand()/(RAND_MAX+1.0))+4;
storeobject(-1, x1, y1, x2, y2, xRECT,xctx->rectcolor, 0, NULL);
#else
#else
drawtemprect(xctx->gc[xctx->rectcolor], ADD, x1, y1, x2, y2);
#endif
}
for(i = 0; i < n; ++i)
{
w=(xctx->areaw*xctx->zoom/80) * rand() / (RAND_MAX+1.0);
@ -3126,11 +3126,11 @@ void draw_stuff(void)
#ifdef STORE
xctx->rectcolor = (int) (16.0*rand()/(RAND_MAX+1.0))+4;
storeobject(-1, x1, y1, x2, y2,xRECT,xctx->rectcolor, 0, NULL);
#else
#else
drawtemprect(xctx->gc[xctx->rectcolor], ADD, x1, y1, x2, y2);
#endif
}
for(i = 0; i < n; ++i)
{
w=xctx->zoom * rand() / (RAND_MAX+1.0);
@ -3143,7 +3143,7 @@ void draw_stuff(void)
#ifdef STORE
xctx->rectcolor = (int) (16.0*rand()/(RAND_MAX+1.0))+4;
storeobject(-1, x1, y1, x2, y2,xRECT,xctx->rectcolor, 0, NULL);
#else
#else
drawtemprect(xctx->gc[xctx->rectcolor], ADD, x1, y1, x2, y2);
#endif
}
@ -3188,7 +3188,7 @@ void new_wire(int what, double mx_snap, double my_snap)
drawline(WIRELAYER,NOW, nl_xx1,nl_yy1,nl_xx2,nl_yy1, 0.0, 0, NULL);
}
if(xctx->nl_y2!=xctx->nl_y1) {
nl_xx1 = xctx->nl_x1; nl_yy1 = xctx->nl_y1;
nl_xx1 = xctx->nl_x1; nl_yy1 = xctx->nl_y1;
nl_xx2 = xctx->nl_x2; nl_yy2 = xctx->nl_y2;
ORDER(nl_xx2,nl_yy1,nl_xx2,nl_yy2);
storeobject(-1, nl_xx2,nl_yy1,nl_xx2,nl_yy2,WIRE,0,0,NULL);
@ -3280,7 +3280,7 @@ void change_layer()
store_arc(-1, x1, y1, r, a, b, xctx->rectcolor, 0, xctx->arc[c][n].prop_ptr);
}
if(type==POLYGON && xctx->poly[c][n].sel==SELECTED) {
store_poly(-1, xctx->poly[c][n].x, xctx->poly[c][n].y,
store_poly(-1, xctx->poly[c][n].x, xctx->poly[c][n].y,
xctx->poly[c][n].points, xctx->rectcolor, 0, xctx->poly[c][n].prop_ptr);
}
else if(type==xRECT && xctx->rect[c][n].sel==SELECTED) {
@ -3294,7 +3294,7 @@ void change_layer()
else if(type==xTEXT && xctx->text[n].sel==SELECTED) {
if(xctx->rectcolor != xctx->text[n].layer) {
char *p;
my_strdup2(_ALLOC_ID_, &xctx->text[n].prop_ptr,
my_strdup2(_ALLOC_ID_, &xctx->text[n].prop_ptr,
subst_token(xctx->text[n].prop_ptr, "layer", dtoa(xctx->rectcolor) ));
xctx->text[n].layer = xctx->rectcolor;
p = xctx->text[n].prop_ptr;
@ -3438,10 +3438,10 @@ void new_line(int what, double mx_snap, double my_snap)
drawtemp_manhattanline(xctx->gctiled, NOW, xctx->nl_x1, xctx->nl_y1, xctx->nl_x2, xctx->nl_y2, 0);
restore_selection(xctx->nl_x1, xctx->nl_y1, xctx->nl_x2, xctx->nl_y2);
xctx->nl_x2 = mx_snap; xctx->nl_y2 = my_snap;
if(!(what & CLEAR)) {
if(!(what & CLEAR)) {
drawtemp_manhattanline(xctx->gc[xctx->rectcolor], NOW, xctx->nl_x1, xctx->nl_y1, xctx->nl_x2, xctx->nl_y2, 0);
}
}
}
}
}
void new_rect(int what, double mousex_snap, double mousey_snap)
@ -3664,7 +3664,7 @@ int text_bbox(const char *str,double xscale, double yscale,
{
register int c=0, length =0;
double w, h;
w=0;h=1;
*cairo_lines = 1;
if(str!=NULL) while( str[c] )
@ -3870,7 +3870,7 @@ void pan(int what, int mx, int my)
}
}
/* instead of doing a drawtemprect(xctx->gctiled, NOW, ....) do 4
/* instead of doing a drawtemprect(xctx->gctiled, NOW, ....) do 4
* XCopy Area operations */
void fix_restore_rect(double x1, double y1, double x2, double y2)
{
@ -3907,7 +3907,7 @@ void select_rect(int stretch, int what, int select)
double nl_xx1, nl_yy1, nl_xx2, nl_yy2;
int incremental_select = tclgetboolvar("incremental_select");
int sel_touch = tclgetboolvar("select_touch");
dbg(1, "select_rect(): what=%d, mousex_save=%g mousey_save=%g, mousex=%g mousey=%g\n",
dbg(1, "select_rect(): what=%d, mousex_save=%g mousey_save=%g, mousex=%g mousey=%g\n",
what, xctx->mx_double_save, xctx->my_double_save, xctx->mousex, xctx->mousey);
if(what & RUBBER)
{
@ -3959,7 +3959,7 @@ void select_rect(int stretch, int what, int select)
if(!sel_touch || xctx->nl_dir == 0)
select_inside(stretch, xctx->nl_xr,xctx->nl_yr,xctx->nl_xr2,xctx->nl_yr2, xctx->nl_sel);
else
else
select_touch(xctx->nl_xr,xctx->nl_yr,xctx->nl_xr2,xctx->nl_yr2, xctx->nl_sel);
draw_selection(xctx->gc[SELLAYER], 0);

2
src/add_custom_button.tcl
View File

@ -34,7 +34,7 @@ if {[lsearch -exact $toolbar_list MyButton] < 0} {
}
## Create an image object. Name should be img<name of button>
image create photo imgMyButton
image create photo imgMyButton
imgMyButton put $MyButtonData
}

16
src/break.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: break.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -44,9 +44,9 @@ BEGIN{ quote=0 }
for(i=1;i<=l;i++) {
pos++
c = substr($0,i,1)
if(c ~/[{}']/) quote=!quote
if(c ~/[{}']/) quote=!quote
if(!nobreak && pos> 130 && !quote && (c ~/[ \t]/)) {
if(first=="*")
if(first=="*")
c = "\n*+" c
else
c = "\n+" c
@ -54,7 +54,7 @@ BEGIN{ quote=0 }
}
printf "%s",c
}
printf "\n"
printf "\n"
} else { #20151203
split($0, a, /[^ \t]+/)
for(i=1;i<=NF;i++) {

314
src/callback.c
View File

File diff suppressed because it is too large Load Diff

10
src/change_ref.awk
View File

@ -1,22 +1,22 @@
#!/bin/sh
#
# File: change_ref.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA

32
src/check.c
View File

@ -26,7 +26,7 @@
#endif
static int check_includes(double x1a, double y1a, double x2a, double y2a,
double x1b, double y1b, double x2b, double y2b)
{
{
if( x1b >= x1a && x2b <= x2a && y1b >= y1a && y2b <= y2a &&
( (x2a-x1a)*(y2b-y1b) == (x2b-x1b)*(y2a-y1a) ) /* parallel */
) {
@ -37,7 +37,7 @@ static int check_includes(double x1a, double y1a, double x2a, double y2a,
static int check_breaks(double x1, double y1, double x2, double y2, double x, double y)
{
if( ( (x > x1 && x < x2) || (y > y1 && y < y2) ) &&
if( ( (x > x1 && x < x2) || (y > y1 && y < y2) ) &&
( (x2-x1)*(y-y1) == (x-x1)*(y2-y1) ) /* parallel */
) {
return 1;
@ -258,7 +258,7 @@ void trim_wires(void)
}
j = wptr->n;
if(i == j || wireflag[j]) continue;
includes = check_includes(xctx->wire[i].x1, xctx->wire[i].y1, xctx->wire[i].x2, xctx->wire[i].y2,
xctx->wire[j].x1, xctx->wire[j].y1, xctx->wire[j].x2, xctx->wire[j].y2);
if(includes) {
@ -272,7 +272,7 @@ void trim_wires(void)
}
}
/* dbg(1, "trim_wires(): included: %g\n", timer(1)); */
/* delete wires */
j = 0;
for(i=0;i<xctx->wires; ++i)
@ -294,7 +294,7 @@ void trim_wires(void)
changed = 1;
}
/* dbg(1, "trim_wires(): delete_1: %g\n", timer(1)); */
/* after wire deletions full rehash is needed */
hash_wires();
@ -335,12 +335,12 @@ void trim_wires(void)
if(k == 1) xctx->wire[i].end1 += 1;
else xctx->wire[i].end2 += 1;
}
}
}
}
}
}
/* dbg(1, "trim_wires(): endpoints: %g\n", timer(1)); */
/* merge parallel touching (in wire[i].x2, wire[i].y2) wires */
for(i=0;i<xctx->wires; ++i) {
if(wireflag[i]) continue;
@ -353,7 +353,7 @@ void trim_wires(void)
if( touch(xctx->wire[j].x1, xctx->wire[j].y1, xctx->wire[j].x2, xctx->wire[j].y2, x0,y0) &&
/* parallel */
(xctx->wire[i].x2 - xctx->wire[i].x1) * (xctx->wire[j].y2 - xctx->wire[j].y1) ==
(xctx->wire[j].x2 - xctx->wire[j].x1) * (xctx->wire[i].y2 - xctx->wire[i].y1) &&
(xctx->wire[j].x2 - xctx->wire[j].x1) * (xctx->wire[i].y2 - xctx->wire[i].y1) &&
/* touch in wire[j].x1, wire[j].y1 */
xctx->wire[j].x1 == x0 && xctx->wire[j].y1 == y0 &&
/* no other connecting wires */
@ -368,7 +368,7 @@ void trim_wires(void)
}
}
/* dbg(1, "trim_wires(): merge: %g\n", timer(1)); */
/* delete wires */
j = 0;
for(i=0;i<xctx->wires; ++i)
@ -426,7 +426,7 @@ static int touches_inst_pin(double x, double y, int inst)
/* return 2 if x0, y0 is on the segment
* return 1 if x0, y0 is less than cadsnap (10) from the segment
* return 0 if nothing will be cut (mouse too far away or degenerated segment)
* return 0 if nothing will be cut (mouse too far away or degenerated segment)
* In this case x0, y0 are reset to the closest point on the segment */
static int closest_point_calculation(double x1, double y1, double x2, double y2,
double *x0, double *y0, int align)
@ -500,7 +500,7 @@ void break_wires_at_point(double x0, double y0, int align)
xctx->wire[xctx->wires].bus = xctx->wire[i].bus;
xctx->wire[xctx->wires].node=NULL;
hash_wire(XINSERT, xctx->wires, 0); /* insertion happens at beginning of list */
dbg(1, "break_wires_at_pins(): hashing new wire %d: %g %g %g %g\n",
dbg(1, "break_wires_at_pins(): hashing new wire %d: %g %g %g %g\n",
xctx->wires, xctx->wire[xctx->wires].x1, xctx->wire[xctx->wires].y1,
xctx->wire[xctx->wires].x2, xctx->wire[xctx->wires].y2);
my_strdup(_ALLOC_ID_, &xctx->wire[xctx->wires].node, xctx->wire[i].node);
@ -558,9 +558,9 @@ void break_wires_at_pins(int remove)
i, xctx->wire[i].x1, xctx->wire[i].y1, xctx->wire[i].x2, xctx->wire[i].y2);
if(!changed) { xctx->push_undo(); changed=1;}
check_wire_storage();
if(!remove || !RECT_INSIDE(xctx->wire[i].x1, xctx->wire[i].y1, x0, y0,
if(!remove || !RECT_INSIDE(xctx->wire[i].x1, xctx->wire[i].y1, x0, y0,
xctx->inst[k].xx1, xctx->inst[k].yy1, xctx->inst[k].xx2, xctx->inst[k].yy2)
|| (!touches_inst_pin(xctx->wire[i].x1, xctx->wire[i].y1, k) && xctx->wire[i].end1 > 0)
|| (!touches_inst_pin(xctx->wire[i].x1, xctx->wire[i].y1, k) && xctx->wire[i].end1 > 0)
) {
xctx->wire[xctx->wires].x1=xctx->wire[i].x1;
xctx->wire[xctx->wires].y1=xctx->wire[i].y1;
@ -574,7 +574,7 @@ void break_wires_at_pins(int remove)
xctx->wire[xctx->wires].bus = xctx->wire[i].bus;
xctx->wire[xctx->wires].node=NULL;
hash_wire(XINSERT, xctx->wires, 0); /* insertion happens at beginning of list */
dbg(1, "break_wires_at_pins(): hashing new wire %d: %g %g %g %g\n",
dbg(1, "break_wires_at_pins(): hashing new wire %d: %g %g %g %g\n",
xctx->wires, xctx->wire[xctx->wires].x1, xctx->wire[xctx->wires].y1,
xctx->wire[xctx->wires].x2, xctx->wire[xctx->wires].y2);
my_strdup(_ALLOC_ID_, &xctx->wire[xctx->wires].node, xctx->wire[i].node);
@ -590,7 +590,7 @@ void break_wires_at_pins(int remove)
xctx->inst[k].xx1, xctx->inst[k].yy1, xctx->inst[k].xx2, xctx->inst[k].yy2)) {
if(touches_inst_pin(xctx->wire[i].x2, xctx->wire[i].y2, k) || xctx->wire[i].end2 == 0) {
dbg(1, "break_wires_at_pins(): wire %d needs to be deleted: %g %g %g %g\n",
dbg(1, "break_wires_at_pins(): wire %d needs to be deleted: %g %g %g %g\n",
i, xctx->wire[i].x1, xctx->wire[i].y1, xctx->wire[i].x2, xctx->wire[i].y2);
/* mark for deletion only if no other nets attached */
xctx->wire[i].sel = SELECTED4; /* use a special flag to later delete these wires
@ -608,7 +608,7 @@ void break_wires_at_pins(int remove)
xctx->inst[k].xx1, xctx->inst[k].yy1, xctx->inst[k].xx2, xctx->inst[k].yy2);
dbg(1, "i=%d, t1=%d, t2=%d, e1=%d, e2=%d\n", i, t1, t2, e1, e2);
if(inside && ( (t1 && t2) || (t1 && e2 == 0) || (t2 && e1 == 0) )) {
xctx->wire[i].sel = SELECTED4;
xctx->wire[i].sel = SELECTED4;
if(!changed) { xctx->push_undo(); changed=1;}
}
}

2
src/clip.c
View File

@ -136,7 +136,7 @@ void clip_xy_to_short(double x, double y, short *sx, short *sy)
*sy = (short) (y * r);
}
/*
/*
*static short clip_to_short(double n)
*{
* return n > SHRT_MAX ? SHRT_MAX : n < SHRT_MIN ? SHRT_MIN : n;

18
src/convert_to_verilog2001.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: convert_to_verilog2001.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -42,7 +42,7 @@ module==1 && $0 == ");" {
port_decl==1 && $1 ~ /^(output|input|inout)$/{
dir=$1 #20161118
getline
getline
sub(/;[ \t]*$/,"")
$1 = dir " " $1
if(comma) ports = ports ",\n"
@ -50,7 +50,7 @@ port_decl==1 && $1 ~ /^(output|input|inout)$/{
comma=1
next
}
port_decl==1 && $0 ~ /^parameter/{
sub(/[ \t]*;[ \t]*$/, "")
if(parameter!="") parameter = parameter ",\n"
@ -61,7 +61,7 @@ port_decl==1 && $0 ~/^[ \t]*$/{
port_decl=0
if(parameter) print "#(\n" parameter "\n)"
print "(\n" ports "\n);"
next
}
@ -69,6 +69,6 @@ module==1 || port_decl==1{
next
}
{
{
print
}

10
src/create_alloc_ids.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/gawk -f
#
# File: create_alloc_ids.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA

10
src/create_alloc_ids_windows.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/gawk -f
#
# File: create_alloc_ids_windows.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA

12
src/create_graph.tcl
View File

@ -1,21 +1,21 @@
#
# File: create_graph.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -31,7 +31,7 @@ proc create_graph {title rawfile node {analysis tran} {color {4 5 6 7 8 9 10 11
# clear loaded raw file if any
xschem raw_clear
# set current layer to graph layer (grey, layer 2)
xschem set rectcolor 2
xschem set rectcolor 2
# create a 300x400 rectangle
xschem rect 0 -300 400 0
# make it a graph

290
src/draw.c
View File

File diff suppressed because it is too large Load Diff

40
src/editprop.c
View File

@ -85,7 +85,7 @@ int my_strncasecmp(const char *s1, const char *s2, size_t n)
* else return 0.0
*/
double get_attr_val(const char *str)
{
{
double s = 0.0;
char *endptr;
@ -102,7 +102,7 @@ double get_attr_val(const char *str)
}
return s;
}
}
@ -167,7 +167,7 @@ char *my_fgets(FILE *fd, size_t *line_len)
}
/* split a string into tokens like standard strtok_r,
* if keep_quote == 0:
* if keep_quote == 0:
* if quote string is not empty any character matching quote is considered a quoting
* character, removed from input and all characters before next quote are considered
* as part of the token. backslash can be used to enter literal quoting characters and
@ -185,13 +185,13 @@ char *my_fgets(FILE *fd, size_t *line_len)
* "bbb"
* ccc ddd
* eee
*
*
* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 1);
* aaa
* \"bbb\"
* "ccc ddd"
* eee
*
*
* my_strtok_r("aaa \\\"bbb\\\" \"ccc ddd\" eee", " ", "\"", 4);
* aaa
* \"bbb\"
@ -237,7 +237,7 @@ size_t my_strdup(int id, char **dest, const char *src) /* empty source string --
{
size_t len;
if(*dest == src && src!=NULL)
if(*dest == src && src!=NULL)
dbg(0, "my_strdup(): WARNING: src == *dest == %p, id=%d\n", src, id);
if(src!=NULL && src[0]!='\0') {
len = strlen(src)+1;
@ -471,7 +471,7 @@ size_t my_snprintf(char *string, size_t size, const char *format, ...)
size_t my_strdup2(int id, char **dest, const char *src) /* 20150409 duplicates also empty string */
{
size_t len;
if(*dest == src && src!=NULL)
if(*dest == src && src!=NULL)
dbg(0, "my_strdup2(): WARNING: src == *dest == %p, id=%d\n", src, id);
if(src!=NULL) {
len = strlen(src)+1;
@ -699,12 +699,12 @@ size_t my_strcat(int id, char **str, const char *append_str)
/* same as my_strcat, but appending "" to NULL returns "" instead of NULL */
size_t my_strcat2(int id, char **str, const char *append_str)
{
{
size_t s, a;
dbg(3,"my_strcat(%d,): str=%s append_str=%s\n", id,
*str? *str : "<NULL>", append_str ? append_str : "<NULL>");
if( *str != NULL)
{
{
s = strlen(*str);
if(append_str == NULL || append_str[0]=='\0') return s;
a = strlen(append_str) + 1;
@ -924,7 +924,7 @@ float my_atof(const char *p)
double my_atod(const char *p)
{
static const double p10[]={
1e-1, 1e-2, 1e-3, 1e-4, 1e-5, 1e-6, 1e-7, 1e-8, 1e-9,
1e-1, 1e-2, 1e-3, 1e-4, 1e-5, 1e-6, 1e-7, 1e-8, 1e-9,
1e-10, 1e-11, 1e-12, 1e-13, 1e-14, 1e-15, 1e-16, 1e-17, 1e-18
};
int frac;
@ -1413,7 +1413,7 @@ static int edit_text_property(int x)
if(x < 0 || x > 2) {
fprintf(errfp, "edit_text_property() : unknown parameter x=%d\n",x);
return 0;
}
}
dbg(1, "edit_text_property(): entering\n");
sel = xctx->sel_array[0].n;
my_strdup(_ALLOC_ID_, &oldprop, xctx->text[sel].prop_ptr);
@ -1556,7 +1556,7 @@ int drc_check(int i)
if(res) {
const char *result;
const char *replace_res;
replace_res = str_replace(res, "@symname", xctx->sym[xctx->inst[j].ptr].name, '\\', -1);
result = tcleval(replace_res);
if(result && result[0]) {
@ -1572,7 +1572,7 @@ int drc_check(int i)
if(has_x) {
/* tclvareval("alert_ {", check_result, "} {}", NULL); */
statusmsg(check_result, 3);
tcleval("show_infotext 1");
tcleval("show_infotext 1");
} else {
dbg(0, "%s\n", check_result);
}
@ -1677,7 +1677,7 @@ static int update_symbol(const char *result, int x, int selected_inst)
my_strdup2(_ALLOC_ID_, &translated_sym, translate(*ii, symbol));
dbg(1, "update_symbol: %s -- %s\n", translated_sym, old_translated_sym);
if(changed_symbol ||
( !strcmp(symbol, xctx->inst[*ii].name) && strcmp(translated_sym, old_translated_sym) ) ) {
( !strcmp(symbol, xctx->inst[*ii].name) && strcmp(translated_sym, old_translated_sym) ) ) {
sym_number=match_symbol(translated_sym); /* check if exist */
if(sym_number>=0) {
prefix=(get_tok_value(xctx->sym[sym_number].templ, "name",0))[0]; /* get new symbol prefix */
@ -1765,7 +1765,7 @@ static int edit_symbol_property(int x, int first_sel)
*ii=xctx->sel_array[first_sel].n;
*netl_com = 0;
if ((xctx->inst[*ii].ptr + xctx->sym)->type!=NULL)
*netl_com =
*netl_com =
!strcmp( (xctx->inst[*ii].ptr+ xctx->sym)->type, "netlist_commands");
if(xctx->inst[*ii].prop_ptr!=NULL) {
if(*netl_com && x==1) {
@ -1821,7 +1821,7 @@ void change_elem_order(int n)
xctx->semaphore--;
if(strcmp(tclgetvar("tctx::retval"),"") )
{
int c = 0;
int c = 0;
xctx->push_undo();
modified = 1;
xctx->prep_hash_inst=0;
@ -1885,7 +1885,7 @@ void change_elem_order(int n)
if(modified) set_modify(1);
}
}
/* replace substring 'rep' in 'str' with 'with', if 'rep' not preceeded by an 'escape' char
/* replace substring 'rep' in 'str' with 'with', if 'rep' not preceeded by an 'escape' char
* 'count' indicates the number of replacements to do or all if -1
*/
char *str_replace(const char *str, const char *rep, const char *with, int escape, int count)
@ -1914,7 +1914,7 @@ char *str_replace(const char *str, const char *rep, const char *with, int escape
while(*s) {
STR_ALLOC(&result, result_pos + with_len + 1, &size);
cond = (count == -1 || replacements < count) &&
cond = (count == -1 || replacements < count) &&
((s == str) || ((*(s - 1) != escape))) &&
(!strncmp(s, rep, rep_len));
if(cond) {
@ -2019,7 +2019,7 @@ void edit_property(int x)
if(x == 1 && strcmp(tclgetvar("tctx::rcode"),"") )
{
if(xctx->netlist_type==CAD_SYMBOL_ATTRS &&
if(xctx->netlist_type==CAD_SYMBOL_ATTRS &&
(!xctx->schsymbolprop || strcmp(xctx->schsymbolprop, tclgetvar("tctx::retval") ) ) ) {
xctx->push_undo();
modified = 1;
@ -2037,7 +2037,7 @@ void edit_property(int x)
xctx->push_undo();
my_strdup(_ALLOC_ID_, &xctx->schspectreprop, (char *) tclgetvar("tctx::retval"));
} else if(xctx->netlist_type==CAD_SPICE_NETLIST &&
} else if(xctx->netlist_type==CAD_SPICE_NETLIST &&
(!xctx->schprop || strcmp(xctx->schprop, tclgetvar("tctx::retval") ) ) ) {
modified = 1;
xctx->push_undo();

12
src/eval_expr.y
View File

@ -89,14 +89,14 @@ symrec *tptr; /* For returning symbol-table pointers */
/* Grammar follows */
%%
input:
| input line
| input line
;
line:
line:
XCHAR {get_char($1);}
| EXPR exp ')' {get_expr($2);lex_state = 0;}
| EXPR '\'' exp '\'' ')' {get_expr($3);lex_state = 0;}
| EXPR exp error
| EXPR exp error
;
exp: NUM {$$ = $1;}
@ -223,7 +223,7 @@ void eval_expr_clear_table(void)
my_free(_ALLOC_ID_, &tmp);
}
}
static int kklex()
{
@ -231,7 +231,7 @@ static int kklex()
if(!str) { return 0; }
if(strstr(str, "expr(") == str) {
lex_state = 1;
lex_state = 1;
str += 5;
dbg(dbglev, "lex(): EXPR\n");
engineering = 0;
@ -268,7 +268,7 @@ static int kklex()
{
char s[100] ="";
int rd = 0;
str--;
str--;
sscanf(str, "%99[.0-9a-zA-Z_-]%n", s, &rd);
kklval.val = atof_eng(s);

4
src/exp.awk
View File

@ -1,8 +1,8 @@
#!/bin/sh
#!/bin/sh
awk '
BEGIN{
BEGIN{
number="[-+]?([0-9]+|[0-9]*\\.[0-9]+)([eE][+-]?[0-9]+)?"
operator ="[+-*/]"
begin="^("

88
src/expandlabel.y
View File

@ -1,7 +1,7 @@
/* File: expandlabel.y
*
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
@ -39,13 +39,13 @@ typedef struct /* used in expandlabel.y */
} Stringptr;
#endif
#define YYERROR_VERBOSE
#define YYERROR_VERBOSE
#define INITIALIDXSIZE 8
extern Stringptr dest_string; /* 20140108 */
static int idxsize=INITIALIDXSIZE;
extern int yylex();
/*
/*
extern FILE *errfp;
extern void *my_malloc(int id, size_t size);
extern void my_free(int id, void *ptr);
@ -169,33 +169,33 @@ static char *expandlabel_strmult(int n, char *s)
memcpy(pos, s, len); /* 20180923 */
pos[len]=',';
pos+=len+1;
}
}
*(pos-1)='\0';
return str;
}
static char *expandlabel_strbus_suffix(char *s, int *n, char *suffix)
{
int i,l;
int tmplen;
char *res=NULL;
char *tmp=NULL;
{
int i,l;
int tmplen;
char *res=NULL;
char *tmp=NULL;
my_realloc(_ALLOC_ID_, &res, n[0] * (strlen(s) + strlen(suffix) + 30));
my_realloc(_ALLOC_ID_, &tmp, strlen(s) + strlen(suffix) + 30);
l=0;
for(i=1;i<n[0];i++)
{
tmplen = sprintf(tmp, "%s[%d]%s,", s, n[i], suffix);
for(i=1;i<n[0];i++)
{
tmplen = sprintf(tmp, "%s[%d]%s,", s, n[i], suffix);
/* strcpy(res+l,tmp); */
memcpy(res+l,tmp, tmplen+1); /* 20180923 */
l+=tmplen;
}
l+=tmplen;
}
my_free(_ALLOC_ID_, &tmp);
sprintf(res+l, "%s[%d]%s", s, n[i], suffix);
return res;
}
}
static char *expandlabel_strbus(char *s, int *n)
{
int i,l;
@ -219,7 +219,7 @@ static char *expandlabel_strbus(char *s, int *n)
static void check_idx(int **ptr,int n)
{
if(n>=idxsize)
if(n>=idxsize)
{
idxsize*=2;
dbg(3, "check_idx(): reallocating idx array: size=%d\n",idxsize);
@ -249,25 +249,25 @@ static char *expandlabel_strbus_nobracket(char *s, int *n)
}
static char *expandlabel_strbus_nobracket_suffix(char *s, int *n, char *suffix)
{
int i,l;
int tmplen;
char *res=NULL;
{
int i,l;
int tmplen;
char *res=NULL;
char *tmp=NULL;
my_realloc(_ALLOC_ID_, &res, n[0] * (strlen(s) + strlen(suffix) + 30));
my_realloc(_ALLOC_ID_, &tmp, strlen(s) + strlen(suffix) + 30);
l=0;
for(i=1;i<n[0];i++)
{
l=0;
for(i=1;i<n[0];i++)
{
tmplen = sprintf(tmp, "%s%d%s,", s, n[i], suffix);
/* strcpy(res+l,tmp); */
memcpy(res+l,tmp, tmplen+1);
l+=tmplen;
l+=tmplen;
}
my_free(_ALLOC_ID_, &tmp);
sprintf(res+l, "%s%d%s", s, n[i], suffix);
return res;
}
return res;
}
%}
@ -308,12 +308,12 @@ int *idx; /* for bus index & bus index ranges */
line: /* empty */
| list {
dbg(dbg_var, "yyparse(): list, dest_string.str=%s\n", $1.str);
my_strdup(_ALLOC_ID_, &(dest_string.str),$1.str);
my_free(_ALLOC_ID_, &$1.str);
my_strdup(_ALLOC_ID_, &(dest_string.str),$1.str);
my_free(_ALLOC_ID_, &$1.str);
dest_string.m=$1.m;
}
;
list: B_NAME {
list: B_NAME {
dbg(dbg_var, "yyparse(): B_NAME, $1=%s\n", $1);
$$.str = expandlabel_strdup($1);
my_free(_ALLOC_ID_, &$1);
@ -325,7 +325,7 @@ list: B_NAME {
my_free(_ALLOC_ID_, &$1);
$$.m = 1;
}
| list B_NAME {
| list B_NAME {
dbg(dbg_var, "yyparse(): list B_NAME, $2=%s\n", $2);
$$.str = expandlabel_strcat($1.str, $2);
my_free(_ALLOC_ID_, &$1.str);
@ -348,7 +348,7 @@ list: B_NAME {
$$.m = $1 * $3.m;
my_free(_ALLOC_ID_, &$3.str);
}
| list ',' list {
| list ',' list {
dbg(dbg_var, "yyparse(): list , list\n");
$$.str=expandlabel_strcat_char($1.str, ',', $3.str);
$$.m = $1.m + $3.m;
@ -367,7 +367,7 @@ list: B_NAME {
dbg(dbg_var, "yyparse(): ( list )\n");
$$=$2;
}
| B_NAME '[' B_NAME ']'
| B_NAME '[' B_NAME ']'
{
size_t size = strlen($1) + strlen($3) + 3;
dbg(dbg_var, "yyparse(): B_NAME [ B_NAME ] , $1=%s $3=%s\n", $1, $3);
@ -377,13 +377,13 @@ list: B_NAME {
my_free(_ALLOC_ID_, &$1);
my_free(_ALLOC_ID_, &$3);
}
| B_NAME '[' index ']'
| B_NAME '[' index ']'
{
dbg(dbg_var, "yyparse(): B_NAME [ index ] , $1=%s $3=%d\n", $1, $3[0]);
$$.str=expandlabel_strbus($1,$3);
my_free(_ALLOC_ID_, &$1);
my_free(_ALLOC_ID_, &$1);
$$.m=$3[0];
my_free(_ALLOC_ID_, &$3);
my_free(_ALLOC_ID_, &$3);
idxsize=INITIALIDXSIZE;
}
| B_NAME '[' index ']' B_TRAILER
@ -397,13 +397,13 @@ list: B_NAME {
idxsize=INITIALIDXSIZE;
}
| B_NAME '[' index_nobracket ']'
| B_NAME '[' index_nobracket ']'
{
dbg(dbg_var, "yyparse(): B_NAME [ index_nobracket ] $1=%s $3=%d\n",$1, $3[0]);
$$.str=expandlabel_strbus_nobracket($1,$3);
my_free(_ALLOC_ID_, &$1);
$$.m=$3[0];
my_free(_ALLOC_ID_, &$3);
my_free(_ALLOC_ID_, &$3);
idxsize=INITIALIDXSIZE;
}
| B_NAME '[' index_nobracket ']' B_TRAILER
@ -464,7 +464,7 @@ index: B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM
if(i==$3) break;
}
}
| B_IDXNUM {
| B_IDXNUM {
$$=my_malloc(_ALLOC_ID_, INITIALIDXSIZE*sizeof(int));
$$[0]=0;
check_idx(&$$, ++$$[0]);
@ -487,7 +487,7 @@ index: B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM
}
| index ',' B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM
{
int i;
int i;
int sign;
sign = XSIGN($5-$3);
@ -497,7 +497,7 @@ index: B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM ':' B_IDXNUM
$$[$$[0]]=i;
if(sign==1 && i + $7 > $5) break;
if(sign==-1 && i - $7 < $5) break;
}
}
}
| index ',' B_IDXNUM ':' B_IDXNUM
{
@ -578,9 +578,9 @@ index_nobracket: B_IDXNUM B_DOUBLEDOT B_IDXNUM B_DOUBLEDOT B_IDXNUM B_DOUBLEDOT
}
| index_nobracket ',' B_IDXNUM B_DOUBLEDOT B_IDXNUM B_DOUBLEDOT B_IDXNUM
{
int i;
int i;
int sign;
sign = XSIGN($5-$3);
for(i=$3;;i+=sign*$7)
{

10
src/findnet.c
View File

@ -34,7 +34,7 @@ static void find_closest_wire(double mx, double my, int override_lock)
double threshold;
double d = distance;
threshold = CADWIREMINDIST * CADWIREMINDIST * xctx->zoom * xctx->zoom * tk_scaling * tk_scaling;
dbg(1, "threshold=%g\n", threshold);
for(i=0;i<xctx->wires; ++i)
{
@ -46,7 +46,7 @@ static void find_closest_wire(double mx, double my, int override_lock)
if( w != -1 && d <= threshold &&
(override_lock || strboolcmp(get_tok_value(xctx->wire[w].prop_ptr, "lock", 0), "true")) )
{
sel.n = w; sel.type = WIRE;
sel.n = w; sel.type = WIRE;
distance = d;
}
}
@ -137,7 +137,7 @@ static void find_closest_polygon(double mx, double my, int override_lock)
xPoly *p = &xctx->poly[c][i];
bezier = !strboolcmp(get_tok_value(p->prop_ptr, "bezier", 0), "true");
bezier = bezier && (p->points > 2);
if(bezier) {
d = find_closest_bezier(mx, my, d, c, i, &l, &col);
} else {
@ -210,7 +210,7 @@ int find_closest_net_or_symbol_pin(double mx, double my, double *x, double *y)
x1 = X_TO_XSCHEM(xctx->areax1);
y1 = Y_TO_XSCHEM(xctx->areay1);
x2 = X_TO_XSCHEM(xctx->areax2);
x2 = X_TO_XSCHEM(xctx->areax2);
y2 = Y_TO_XSCHEM(xctx->areay2);
hash_instances();
@ -409,7 +409,7 @@ static void find_closest_box(double mx ,double my, int override_lock)
for(i=0;i<xctx->rects[c]; ++i)
{
if( POINTINSIDE(mx, my, xctx->rect[c][i].x1 - threshold, xctx->rect[c][i].y1 - threshold,
xctx->rect[c][i].x2 + threshold, xctx->rect[c][i].y2 + threshold) &&
xctx->rect[c][i].x2 + threshold, xctx->rect[c][i].y2 + threshold) &&
!POINTINSIDE(mx, my, xctx->rect[c][i].x1 + threshold, xctx->rect[c][i].y1 + threshold,
xctx->rect[c][i].x2 - threshold, xctx->rect[c][i].y2 - threshold))
{

48
src/flatten.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: flatten.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -66,7 +66,7 @@ BEGIN{
sub(/^\*\*/,"",$0)
}
if($0 ~ /^\**\.ENDS/ && first_subckt) {
first_subckt = 0
first_subckt = 0
sub(/^\*\*/,"",$0)
}
if($0 ~/^\+/) # join folded lines
@ -76,7 +76,7 @@ BEGIN{
gsub(/[\t ]*=[\t ]*/, "=")
a[lines++]=$0
}
}
END{
@ -86,14 +86,14 @@ END{
devpattern = devpattern j
}
devpattern = devpattern "]"
for(j=0;j<lines;j++)
for(j=0;j<lines;j++)
{
$0=a[j]
if($1 ~ /\.GLOBAL/) # get global nodes
for(i=2;i<=NF;i++) global[$i]=i;
if($1 ~ /^\.SUBCKT/) # parse subckts
{ # subckt["name","first"]= first line
{ # subckt["name","first"]= first line
subname=$2 # subckt["name","last"]= last line
subckt[subname,"first"]=j # subckt["name", "ports"] = # of ports
for(k=3;k<=NF;k++) # subckt["name", "port","node"]=
@ -102,14 +102,14 @@ END{
if($k ~ /=/) break
subckt[subname,"port",$k]=k-2
}
subckt[subname,"ports"]=k-3
subckt[subname,"ports"]=k-3
for(;k<=NF;k++) # subckt["name", "param", "parname"]=
if($k ~ /=/) # default value
{
split($k,tmp,"=")
subckt[subname,"param",tmp[1]]=tmp[2]
}
}
}
if($1 ~ /^\.ENDS/) {
subckt[subname,"last"]=j
}
@ -117,13 +117,13 @@ END{
print "** " topcell " flat netlist"
expand(topcell,"","","")
print ".end"
# parameters:
# parameters:
# - subckt name to expand
# - current path (will be prefixed to inst & node names)
# - string of params: par1=val1 par2=val2 par3=val3 ...
# - port list to connect the subckt to.
}
}
# recursive routine!!! private variables must be declared local !!
@ -138,7 +138,7 @@ function expand(name, path, param,ports, # func. params
pathname=pathsep path ; pathnode=path pathsep
}
split(param,paramarray)
for(k in paramarray)
for(k in paramarray)
{
split(paramarray[k],parameter,"=")
paramarray2[parameter[1]]=parameter[2]
@ -156,17 +156,17 @@ function expand(name, path, param,ports, # func. params
paramlist = ""; portlist = ""; subname=""
for(k=num;k>=2;k--)
{
if(line[k] ~ /=/)
if(line[k] ~ /=/)
{
split(line[k],parameter,"=")
if(parameter[2] in paramarray2)
if(parameter[2] in paramarray2)
paramlist= parameter[1] "=" paramarray2[parameter[2]] " " paramlist
else paramlist= line[k] " " paramlist
}
else if(subname=="") {subname=line[k]; subname_pos=k }
else if( (subname,ports) in subckt && k<=subckt[subname,"ports"]+1)
else if( (subname,ports) in subckt && k<=subckt[subname,"ports"]+1)
portlist = getnode(name,pathnode,portarray,line[k]) " " portlist
else if(k<subname_pos){
else if(k<subname_pos){
# 30032003 undefined subcircuit
portlist = getnode(name,pathnode,portarray,line[k]) " " portlist
}
@ -180,7 +180,7 @@ function expand(name, path, param,ports, # func. params
printf "%s %s %s %s\n",line[1] pathname , portlist, subname, paramlist
}
print "*--------END___" pathnode line[1] "->" subname
print "*--------END___" pathnode line[1] "->" subname
}
else
{
@ -210,7 +210,7 @@ function expand(name, path, param,ports, # func. params
}
else { # if parameter get actual value
if(line[k] in paramarray2) line[k] = paramarray2[line[k]]
else { # try to see if parameter inside quotes or braces
else { # try to see if parameter inside quotes or braces
m = line[k]
gsub(/[{}']/, "", m)
if(m in paramarray2) line[k] = paramarray2[m]
@ -218,7 +218,7 @@ function expand(name, path, param,ports, # func. params
printf "%s ", line[k]
}
}
}
}
else if(line[1] ~/^\.(SAVE|PRINT|PROBE)/) {
printf "%s ", general_sub(a[j],name,pathnode,portarray)
}
@ -235,7 +235,7 @@ function subst_param(s, pa, p, i, ss)
{
for(p in pa) {
while(1) {
i = match(s, "[^a-zA-Z0-9_]" p "[^=a-zA-Z0-9_]")
i = match(s, "[^a-zA-Z0-9_]" p "[^=a-zA-Z0-9_]")
ss = ""
if(i) {
ss = ss substr(s, 1, RSTART)
@ -255,7 +255,7 @@ function subst_param(s, pa, p, i, ss)
function getnode(name, path, portarray, node)
# return the full path-name of <node> in subckt <name>
# return the full path-name of <node> in subckt <name>
# in path <path>, called with ports <portarray>
{
sub(/ *$/, "", node)
@ -263,7 +263,7 @@ function getnode(name, path, portarray, node)
if(name!=topcell) # if we are in top cell, nothing to do
{
if(name SUBSEP "port" SUBSEP node in subckt)
return portarray[subckt[name,"port",node]] # <node> is a port,
return portarray[subckt[name,"port",node]] # <node> is a port,
#return port mapping
if(!(node in global)) return path node # local node
}

38
src/flatten_savenodes.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: flatten.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -65,7 +65,7 @@ BEGIN{
sub(/^\*\*/,"",$0)
}
if(toupper($0) ~ /^\**\.ENDS/ && first_subckt) {
first_subckt = 0
first_subckt = 0
sub(/^\*\*/,"",$0)
}
if($0 ~/^\+/) # join folded lines
@ -73,16 +73,16 @@ BEGIN{
a[lines-1]=a[lines-1] " " substr($0,2); next
}
a[lines++]=$0
}
}
END{
for(j=0;j<lines;j++)
for(j=0;j<lines;j++)
{
$0=a[j]
if(toupper($1) ~ /\.GLOBAL/) # get global nodes
for(i=2;i<=NF;i++) global[$i]=i;
if(toupper($1) ~ /^\.SUBCKT/) # parse subckts
{ # subckt["name","first"]= first line
{ # subckt["name","first"]= first line
subname=$2 # subckt["name","last"]= last line
subckt[subname,"first"]=j # subckt["name", "ports"] = # of ports
for(k=3;k<=NF;k++) # subckt["name", "port","node"]=
@ -91,21 +91,21 @@ END{
if($k ~ /=/) break
subckt[subname,"port",$k]=k-2
}
subckt[subname,"ports"]=k-3
}
subckt[subname,"ports"]=k-3
}
if(toupper($1) ~ /^\.ENDS/) {
subckt[subname,"last"]=j
}
}
print "** flattened .save nodes"
expand(topcell,"","")
# parameters:
# parameters:
# - subckt name to expand
# - current path (will be prefixed to inst & node names)
# - port list to connect the subckt to.
if(do_end !="") print do_end
}
}
# recursive routine!!! private variables must be declared local !!
function expand(name, path,ports, # func. params
@ -125,9 +125,9 @@ function expand(name, path,ports, # func. params
for(k=num;k>=2;k--) {
if(line[k] !~ /=/) {
if(subname=="") {subname=line[k]; subname_pos=k }
else if( (subname,ports) in subckt && k<subckt[subname,"ports"]+0)
else if( (subname,ports) in subckt && k<subckt[subname,"ports"]+0)
portlist = getnode(name,pathnode,portarray,line[k]) " " portlist
else if(k<subname_pos){
else if(k<subname_pos){
# undefined subcircuit
portlist = getnode(name,pathnode,portarray,line[k]) " " portlist
}
@ -136,13 +136,13 @@ function expand(name, path,ports, # func. params
# print "*--------BEGIN_" pathnode line[1]_"->" subname
if( (subname,"first") in subckt) # 30032003 do not expand subcircuit call if undefined subckt
expand(subname,pathnode line[1],portlist)
# print "*--------END___" pathnode line[1] "->" subname
# print "*--------END___" pathnode line[1] "->" subname
}
else {
if(toupper(line[1]) ~ /^\.(SAVE|PRINT)$/ && toupper(line[2]) !~/^ALL$/) {
printf line[1] " "
printf line[1] " "
for(k = 2; k <= num; k++) {
if(k > 2) printf " "
if(k > 2) printf " "
if(line[k] ~ /^[iI]\($/ && line[k+2]==")" && do_save == 1) {
if(name != topcell)
if(xyce==1)
@ -169,7 +169,7 @@ function expand(name, path,ports, # func. params
}
function getnode(name, path, portarray, node)
# return the full path-name of <node> in subckt <name>
# return the full path-name of <node> in subckt <name>
# in path <path>, called with ports <portarray>
{
if(name!=topcell) { # if we are in top cell, nothing to do

24
src/flatten_tedax.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: flatten_tedax.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -71,7 +71,7 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
for(i = start[cell]+1; i <= end[cell]-1; i++) {
$0 = netlist[i]
reparse()
# __subcircuit__ pcb_voltage_protection x0
# __subcircuit__ pcb_voltage_protection x0
# __map__ VOUT -> VOUTXX
# __map__ ... -> ...
if($1 == "__subcircuit__") {
@ -80,7 +80,7 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
subpos = i
sub(/__subcircuit__/, "subcircuit", $0)
out("#" spaces(hier * 2 - 1) $0)
submaplist = ""
submaplist = ""
for(i++; ;i++) {
$0 = netlist[i]
reparse()
@ -91,9 +91,9 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
sub(/__map__/, "map", $0)
out("#" spaces(hier * 2 - 1) $0)
}
expand(subcell, subinst, path subinst hiersep, submaplist)
i--; continue; # redo processing of current line
}
if($1 == "conn") {
@ -112,7 +112,7 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
function spaces(n, s)
{
n = (n > 0) ? n - 1 : 0
n = (n > 0) ? n - 1 : 0
s =" "
while(length(s) < n) s = s s
return substr(s,1,n)
@ -120,7 +120,7 @@ function spaces(n, s)
function out(s)
{
if(length(s) > 512)
if(length(s) > 512)
print "flatten_tedax: WARNING: >> " s "\n line length > 512 chars, this breaks tEDAx" > "/dev/stderr"
print s
}
@ -130,7 +130,7 @@ function dbg(s)
if(debug) print s > "/dev/stderr"
}
function resolve_node(node, path, maplist, arr, n, retnode, i)
function resolve_node(node, path, maplist, arr, n, retnode, i)
{
dbg("resolve_node: node=" node " maplist=" maplist)
gsub(/\\ /, SUBSEP "s", maplist)

2
src/get_malloc_id.awk
View File

@ -53,7 +53,7 @@ xinit.c \
| awk '{
if(n>0 && $1 <= prev) print ">>>>>>>>>>> ERROR >>>>>>>>> " $0
else if(n>0 && $1 != prev+1) {
if($1-1 > prev+1)
if($1-1 > prev+1)
print ">>>>>>>>>>> FREE >>>>>>>>> " prev+1 ":" $1-1
else
print ">>>>>>>>>>> FREE >>>>>>>>> " $1-1

88
src/gschemtoxschem.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: gschemtoxschem.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -33,7 +33,7 @@ BEGIN{
debug=0 # set to 1 to print debug info to stderr
}
#### on first line
#### on first line
FNR==1{
if(FILENAME ~/\.sym$/) is_symbol = 1
sch = FILENAME
@ -63,7 +63,7 @@ FNR==1{
y2 = $5 / 10
lines = lines "L 4 " order(x1, y1, x2, y2) " {}\n"
}
#### Text objects
# T x y color size visibility show angle alignment num_lines
# 1 2 3 4 5 6 7 8 9 10
@ -122,14 +122,14 @@ FNR==1{
# if($0 ~ /^(device|description|footprint|source|numslots)=/) {
# attributes = $0
# sub(/=.*/, "", attributes)
# if(extra !="") extra = extra " "
# if(extra_pinnumber !="") extra_pinnumber = extra_pinnumber " "
# if(extra !="") extra = extra " "
# if(extra_pinnumber !="") extra_pinnumber = extra_pinnumber " "
# extra = extra attributes
# extra_pinnumber = extra_pinnumber "-"
# }
save = $0
sub(/^device=/, "type=")
sub(/^device=/, "type=")
if ($0 ~/^value=IO/) { # inconsistency in io-1.sym
$0 = "type=IO"
}
@ -138,7 +138,7 @@ FNR==1{
if($0 ~/=OUTPUT/) {pin = 1; sub(/=.*/, "=opin"); template_attrs = template_attrs "lab=xxx "}
if($0 ~/=IO/) {pin = 1; sub(/=.*/, "=iopin"); template_attrs = template_attrs "lab=xxx "}
if(is_symbol && has_schematic) global_attrs = "type=subcircuit\n" global_attrs
else global_attrs = $0 "\n" global_attrs
else global_attrs = $0 "\n" global_attrs
}
$0 = save
if(show == 1) {
@ -156,8 +156,8 @@ FNR==1{
if(visibility) {
texts = texts "T {" text "} " xt " " (-yt) " " int(angle/90) " " flip " " size " " size " {" text_align "}\n"
}
}
}
#### box objects
else if($0 ~ /^B/){
x1 = $2 / 10
@ -169,24 +169,24 @@ FNR==1{
boxes = boxes "L 4 " x1 " " (-y2) " " x2 " " (-y2) " {}\n"
boxes = boxes "L 4 " x1 " " (-y2) " " x1 " " (-y1) " {}\n"
}
#### circle objects
else if($0 ~ /^V/){ #circle
circles = circles "A 4 " ($2/10) " " (-$3/10) " " ($4/10) " " 0 " " 360 " {}\n"
}
#### arc objects
# A 1000 1000 100 90 180 3 0 0 0 -1 -1
else if($0 ~ /^A/){ #arc
arcs = arcs "A 4 " ($2/10) " " (-$3/10) " " ($4/10) " " ($5) " " ($6) " {}\n"
}
#### path objects: use xschem polygon
# H 3 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 5 <--n_lines
#path object --> simulate with polygon
else if($0 ~ /^H/){
numlines =$NF
polys = polys "P 4 " numlines " "
polys = polys "P 4 " numlines " "
for(i = 0; i < numlines; i++) {
getline
sub(/,/, " ", $0)
@ -197,11 +197,11 @@ FNR==1{
polyx[i] = $2/10
polyy[i] = -$3/10
}
polys = polys polyx[i] " " polyy[i] " "
polys = polys polyx[i] " " polyy[i] " "
}
polys = polys "{fill=true}\n"
}
#### net (wire) objects
# N 39000 50400 39000 51000 4
else if($0 ~/^N/) {
@ -248,12 +248,12 @@ FNR==1{
wires = wires "C {lab_wire.sym} " tx " " ty " 0 1 {" propstring "}\n"
}
}
#### component instance object
# selectable angle flip
# selectable angle flip
#C 36700 54700 1 90 0 resistor-1.sym
#component
else if($0 ~ /^C/){
else if($0 ~ /^C/){
cx = $2/10
cy=-$3/10
crot = $5/90
@ -295,7 +295,7 @@ FNR==1{
getline
continue
}
}
gsub(/ /, "\\\\\\\\ ", $0) # prefix spaces with double backslash
propstring = propstring $0 "\n"
@ -314,7 +314,7 @@ FNR==1{
}
components = components "C {" symbol "} " cx " " cy " " crot " " cflip " {" propstring "}\n"
}
#### pin object
# P 900 100 750 100 1 0 0
else if($0 ~ /^P/){
@ -322,9 +322,9 @@ FNR==1{
pin_idx++
pin_line[pin_idx] = "L 3 " order($2, $3, $4, $5) " {}"
if($8 == 0) {
pin_box[pin_idx] = "B 5 " $2-halfpinsize " " (-$3-halfpinsize) " " $2+halfpinsize " " (-$3+halfpinsize)
pin_box[pin_idx] = "B 5 " $2-halfpinsize " " (-$3-halfpinsize) " " $2+halfpinsize " " (-$3+halfpinsize)
} else {
pin_box[pin_idx] = "B 5 " $4-halfpinsize " " (-$5-halfpinsize) " " $4+halfpinsize " " (-$5+halfpinsize)
pin_box[pin_idx] = "B 5 " $4-halfpinsize " " (-$5-halfpinsize) " " $4+halfpinsize " " (-$5+halfpinsize)
}
ret = getline
if($0 == "{") {
@ -363,19 +363,19 @@ FNR==1{
attr = "name"
found_name = 1
}
if(attr == "pintype") {
if(attr == "pintype") {
found_pintype=1
attr = "dir"
if(value=="clk") value = "in"
if(value!="in" && value !="out") value = "inout"
}
if(attr == "pinseq") {
pin_index[value] = pin_idx
pinseq++
if(value > max_pinseq) max_pinseq = value
}
gsub(/\\/, "\\\\\\\\", value) # replace single slash with double backslash.
gsub(/\\/, "\\\\\\\\", value) # replace single slash with double backslash.
gsub(/ /, "\\\\\\\\ ", value) # prefix spaces with double backslash
gsub(/\\_/, "_", value)
pin_attr[pin_idx, nattr] = attr
@ -430,14 +430,14 @@ function print_header()
sub(/:.*/,"", netname)
sub(/.*:/, "", pinnumber)
template_attrs = template_attrs netname "=" netname "\n"
if(extra !="") extra = extra " "
if(extra_format !="") extra_format = extra_format " "
if(extra_pinnumber !="") extra_pinnumber = extra_pinnumber " "
extra = extra netname
extra_pinnumber = extra_pinnumber pinnumber
if(extra !="") extra = extra " "
if(extra_format !="") extra_format = extra_format " "
if(extra_pinnumber !="") extra_pinnumber = extra_pinnumber " "
extra = extra netname
extra_pinnumber = extra_pinnumber pinnumber
extra_format = extra_format "@" netname
}
}
if(extra) {
extra = "extra=\"" extra "\""
@ -446,7 +446,7 @@ function print_header()
extra_pinnumber = "extra_pinnumber=\"" extra_pinnumber "\""
}
if(pin == 1) spice_attrs = tedax_attrs=""
if(pin == 1) spice_attrs = tedax_attrs=""
else if(pin == 2) {
spice_attrs = tedax_attrs=""
sub(/type=[^ ]+\n/, "type=label\n", global_attrs)
@ -465,13 +465,13 @@ function print_header()
template_attrs = "template=\"" template_attrs "\"\n"
if(FILENAME ~/\.sym$/) {
if(global_attrs !~ /type=/)
if(pin == 2) {
if(global_attrs !~ /type=/)
if(pin == 2) {
global_attrs = "type=label\n" global_attrs
} else {
global_attrs = "type=symbol\n" global_attrs
}
print "K {" global_attrs template_attrs tedax_attrs spice_attrs
print "K {" global_attrs template_attrs tedax_attrs spice_attrs
if(extra) {
print extra
}
@ -498,11 +498,11 @@ function file_exists(f, r, c)
else return 1
}
function order(x1, y1, x2, y2, tmp)
function order(x1, y1, x2, y2, tmp)
{
y1 = -y1
y2 = -y2
if(x2<x1) {
if(x2<x1) {
tmp = x1; x1 = x2; x2 = tmp; tmp = y1; y1 = y2; y2 = tmp
} else if(x2 == x1 && y2 < y1) {
tmp = y1; y1 = y2; y2 = tmp
@ -510,7 +510,7 @@ function order(x1, y1, x2, y2, tmp)
return x1 " " y1 " " x2 " " y2
}
function rectorder(x1, y1, x2, y2, tmp)
function rectorder(x1, y1, x2, y2, tmp)
{
y1 = -y1
y2 = -y2
@ -647,7 +647,7 @@ END{
len = length(pin_value[idx, j])
correct_align()
if( visible ) {
if(pin_attr[idx, j] ~/^pinnumber$/) text_attr="layer=13"
if(pin_attr[idx, j] ~/^pinnumber$/) text_attr="layer=13"
else text_attr=""
print "T {" attr "} " xt " " (-yt) " " int(angle/90) " " flip " " size " " size " {" text_attr text_align "}"
}
@ -655,4 +655,4 @@ END{
npin++
} # end print pins
}

2
src/hash_iterator.c
View File

@ -26,7 +26,7 @@ void init_inst_iterator(Iterator_ctx *ctx, double x1, double y1, double x2, doub
{
ctx->instflag = NULL;
dbg(3, "init_inst_iterator(): instances=%d\n", xctx->instances);
if(xctx->instances) {
my_realloc(_ALLOC_ID_, &ctx->instflag, xctx->instances*sizeof(unsigned short));
memset(ctx->instflag, 0, xctx->instances*sizeof(unsigned short));

26
src/herculestospice.awk
View File

@ -4,16 +4,16 @@ BEGIN{
}
{
{
debug=0
if($1=="model") macro=$2
if( $1=="inst") {
props=""
props=""
inst_nonets=1
printf "%s ", expand_label(prefix[macro] $2)
}
if($1=="nets") {
inst_nonets=0
$1=""; $0 = $0
@ -30,7 +30,7 @@ BEGIN{
if ( !(macroport[macro,i] in instport) ) {
print "hercules2spice: " macroport[macro,i] " not in instport (" $0 ")" > "/dev/stderr"
}
s = expand_label(instport[ macroport[macro,i] ] )
s = expand_label(instport[ macroport[macro,i] ] )
expand_label(macroport[macro,i]) # calculate label_width ...
printf "@%d %s ", label_width,s
}
@ -40,13 +40,13 @@ BEGIN{
if( $1 == "props" ) {
$1=""; $0 = $0
sub(/^ /, "")
n = split($0, s_arr, /\\/)
n = split($0, s_arr, /\\/)
props=""
for(i=1; i<=n; i+=2) {
if( 1 ) { ############## s_arr[i] ~ /^[wWlL]$/) {
if(props !="") props = props " "
if(props !="") props = props " "
props = props s_arr[i] "=\"" s_arr[i+1] "\""
}
}
}
}
@ -66,7 +66,7 @@ BEGIN{
if(startmacro!="") print ".ends"
printf "\n.subckt %s ", $3
startmacro=$1
}
}
if($1=="prefix") {
prefix[macroname] = $2
@ -102,7 +102,7 @@ BEGIN{
if(defaults !="") defaults = defaults " "
defaults = defaults s_arr[i] "=\"" s_arr[i+1] "\""
}
}
@ -138,13 +138,13 @@ BEGIN{
}
}
END{
print ".ends"
}
@ -193,8 +193,8 @@ function expand_label(s, tmp, n, i, j, l, mult, s_arr, lab, idx_le
l = l expand_label( substr(s_arr[i], 1, tmp-1) ">")
if(l!="") l = l ","
l = l expand_label( lab "<" substr(s_arr[i], tmp+1))
} else if(s_arr[i] ~ /^[^<>]+<[0-9]+:[0-9]+:[0-9]+>$/) {
lab = incr = idx_left = idx_right = s_arr[i]

100
src/hilight.c
View File

@ -34,7 +34,7 @@ static unsigned int hi_hash(const char *tok)
hash += (hash << 5) + c;
}
xctx->sch_path_hash[xctx->currsch] = hash;
} else {
} else {
hash = xctx->sch_path_hash[xctx->currsch];
}
while ( (c = (unsigned char)*tok++) ) {
@ -48,8 +48,8 @@ static void hilight_hash_free_entry(Hilight_hashentry *entry)
Hilight_hashentry *tmp;
while(entry) {
tmp = entry->next;
my_free(_ALLOC_ID_, &entry->token);
my_free(_ALLOC_ID_, &entry->path);
my_free(_ALLOC_ID_, &entry->token);
my_free(_ALLOC_ID_, &entry->path);
my_free(_ALLOC_ID_, &entry);
entry = tmp;
}
@ -79,7 +79,7 @@ static Hilight_hashentry *hilight_hash_lookup(const char *token, int value, int
{
unsigned int hashcode, index;
Hilight_hashentry **preventry;
if(token==NULL) return NULL;
hashcode=hi_hash(token);
index=hashcode % HASHSIZE;
@ -151,7 +151,7 @@ Hilight_hashentry *bus_hilight_hash_lookup(const char *token, int value, int wha
char *string=NULL;
Hilight_hashentry *ptr1=NULL, *ptr2=NULL;
int mult;
dbg(1, "bus_hilight_hash_lookup(): token=%s value=%d what=%d\n",
token ? token : "<NULL>", value, what);
xctx->some_nets_added = 0;
@ -218,10 +218,10 @@ void copy_hilights(void)
new_entry = &xctx->hilight_table[i];
while(entry && *entry) {
Hilight_hashentry *new = (Hilight_hashentry *)my_calloc(_ALLOC_ID_, 1, sizeof( Hilight_hashentry ));
if(*new_entry) (*new_entry) = new;
xctx->hilight_nets = 1;
my_strdup2(_ALLOC_ID_, &(new->token), (*entry)->token);
my_strdup2(_ALLOC_ID_, &(new->path), (*entry)->path);
new->hash = (*entry)->hash;
@ -267,7 +267,7 @@ void display_hilights(int what, char **str)
my_strcat(_ALLOC_ID_, str,"}");
first = 0;
}
skip:
skip:
entry = entry->next;
}
}
@ -282,7 +282,7 @@ static int there_are_hilights()
if(hiptr[i]) return 1;
}
for(i = 0; i < xctx->instances; ++i) {
if(inst[i].color != -10000) return 1;
if(inst[i].color != -10000) return 1;
}
return 0;
}
@ -304,13 +304,13 @@ int hilight_graph_node(const char *node, int col)
path_skip++; /* skip initial '.' */
/* skip path components that are above the level where raw file was loaded */
while(*path_skip && skip < start_level) {
if(*path_skip == '.') skip++;
if(*path_skip == '.') skip++;
++path_skip;
}
}
my_strdup2(_ALLOC_ID_, &n, node);
nptr = n;
dbg(1, "hilight_graph_node(): path_skip=%s, %s: %d\n", path_skip, node, col);
if(strstr(n, "i(v.")) {current = 1; nptr += 4;}
else if(strstr(n, "I(V.")) {current = 1; nptr += 4;}
@ -326,7 +326,7 @@ int hilight_graph_node(const char *node, int col)
nptr = ptr2 + 1;
if(!strstr(path_skip, path3))
my_mstrcat(_ALLOC_ID_, &path2, path, path3, ".", NULL);
else
else
my_strdup2(_ALLOC_ID_, &path2, path);
}
else {
@ -347,7 +347,7 @@ int hilight_graph_node(const char *node, int col)
return 1;
}
/* by default:
/* by default:
* xctx->active_layer[0] = 7
* xctx->active_layer[1] = 8
* xctx->active_layer[2] = 10 if 9 is disabled it is skipped
@ -375,7 +375,7 @@ void incr_hilight_color(void)
dbg(1, "incr_hilight_color(): xctx->hilight_color=%d\n", xctx->hilight_color);
}
static void set_rawfile_for_bespice()
static void set_rawfile_for_bespice()
{
char raw_file[PATH_MAX];
char netlist_file[PATH_MAX];
@ -392,7 +392,7 @@ static void set_rawfile_for_bespice()
tclvareval("puts $bespice_server_getdata(sock) ",
"{create_equivalent_nets \"", raw_file, "\" \"", netlist_file, "\"}",
NULL);
/* (3) make sure that the raw file is used for commands plotting voltages and currents
/* (3) make sure that the raw file is used for commands plotting voltages and currents
this is important if more than one file has been opened. */
tclvareval("puts $bespice_server_getdata(sock) ",
"{use_file_for_link_to_schematic \"", raw_file, "\"}",
@ -460,7 +460,7 @@ void create_plot_cmd(void)
c = get_color(entry->value);
++idx;
if(viewer == NGSPICE) {
sprintf(color_str, "%02x/%02x/%02x",
sprintf(color_str, "%02x/%02x/%02x",
xctx->xcolor_array[c].red>>8, xctx->xcolor_array[c].green>>8, xctx->xcolor_array[c].blue>>8);
if(idx > 9) {
idx = 2;
@ -481,7 +481,7 @@ void create_plot_cmd(void)
}
if(viewer == GAW) {
char *t=NULL, *p=NULL;
sprintf(color_str, "%02x%02x%02x",
sprintf(color_str, "%02x%02x%02x",
xctx->xcolor_array[c].red>>8, xctx->xcolor_array[c].green>>8, xctx->xcolor_array[c].blue>>8);
my_strdup(_ALLOC_ID_, &t, tok);
my_strdup2(_ALLOC_ID_, &p, (entry->path)+1);
@ -502,12 +502,12 @@ void create_plot_cmd(void)
}
if(viewer == BESPICE) {
char *t=NULL, *p=NULL;
sprintf(color_str, "#%02x%02x%02x",
sprintf(color_str, "#%02x%02x%02x",
xctx->xcolor_array[c].red>>8, xctx->xcolor_array[c].green>>8, xctx->xcolor_array[c].blue>>8);
my_strdup(_ALLOC_ID_, &t, tok);
my_strdup2(_ALLOC_ID_, &p, (entry->path)+1);
/* bespice command syntax :
/* bespice command syntax :
add_voltage_on_spice_node_to_plot <plot name> <section name> <hierarchical spice node name> <flag clear> [<color>]
plot name is "*" => automatic
section name is empty => automatic or user defined
@ -560,7 +560,7 @@ void hilight_net_pin_mismatches(void)
int mult;
xRect *rct;
int incr_hi;
incr_hi = tclgetboolvar("incr_hilight");
rebuild_selected_array();
prepare_netlist_structs(0);
@ -608,7 +608,7 @@ void hilight_parent_pins(void)
inst_number = xctx->sch_inst_number[xctx->currsch];
/* may be set to -1 by descend_symbol to notify we are
* descending into a smbol from an instance with no embed flag set
* descending into a smbol from an instance with no embed flag set
* this is used when descending into symbols created from generators */
if(inst_number == -1) inst_number = 1;
@ -620,7 +620,7 @@ void hilight_parent_pins(void)
/* propagate global nets */
for(j=0;j<HASHSIZE; ++j) {
entry=xctx->hilight_table[j];
for( entry=xctx->hilight_table[j]; entry; entry = entry->next) {
for( entry=xctx->hilight_table[j]; entry; entry = entry->next) {
if(entry->token[0] == ' ') continue; /* skip instances, process only nets */
if(record_global_node(3, NULL, entry->token)) {
dbg(1, "entry token=%s, value=%d\n", entry->token, entry->value);
@ -651,7 +651,7 @@ void hilight_parent_pins(void)
if(entry)
{
dbg(1, "found hilight entry in child: %s\n", entry->token);
bus_hilight_hash_lookup(find_nth(net_node, ",", "", 0,
bus_hilight_hash_lookup(find_nth(net_node, ",", "", 0,
((inst_number - 1) * mult + k - 1) % net_mult + 1), entry->value, XINSERT);
}
else
@ -662,7 +662,7 @@ void hilight_parent_pins(void)
* in the hierarchy. If you want to see how child pins propagate upstream
* you should unhilight all net probes, hilight the desired child pins and then go up */
/*
/*
* bus_hilight_hash_lookup(find_nth(net_node, ",", "", 0,
* ((inst_number - 1) * mult + k - 1) % net_mult + 1), 0, XDELETE);
*/
@ -703,7 +703,7 @@ void hilight_child_pins(void)
}
/* may be set to -1 by descend_symbol to notify we are
* descending into a smbol from an instance with no embed flag set
* descending into a smbol from an instance with no embed flag set
* this is used when descending into symbols created from generators */
if(inst_number == -1) inst_number = 1;
@ -752,7 +752,7 @@ static int bus_search(const char*s)
}
#ifndef __unix__
int win_regexec(const char *options, const char *pattern, const char *name)
int win_regexec(const char *options, const char *pattern, const char *name)
{
if (options!=NULL)
tclvareval("regexp {", options,"} {", pattern, "} {", name, "}", NULL);
@ -797,7 +797,7 @@ int search(const char *tok, const char *val, int sub, int sel, int match_case, i
}
save_draw = xctx->draw_window;
xctx->draw_window=1;
/* replace strcmp and strstr with my_strcasecmp and my_strcasestr
/* replace strcmp and strstr with my_strcasecmp and my_strcasestr
* if SPICE or VHDL (case insensitive) netlist mode is set */
if(!match_case) {
comparefn = my_strcasecmp;
@ -808,7 +808,7 @@ int search(const char *tok, const char *val, int sub, int sel, int match_case, i
cflags |= REG_ICASE; /* ignore case for Spice and VHDL (these are case insensitive netlists) */
}
if(regcomp(&re, val , cflags)) return TCL_ERROR;
#else
#else
if(!match_case) {
my_strdup(_ALLOC_ID_, &regexp_options, "-nocase");
}
@ -1119,7 +1119,7 @@ static void drill_hilight(int mode)
if( (entry=bus_hilight_hash_lookup(netbitname, 0, XLOOKUP)) ) {
if( hilight_connected_inst || (symbol->type && IS_LABEL_SH_OR_PIN(symbol->type)) ) {
xctx->inst[i].color = entry->value;
inst_hilight_hash_lookup(i, entry->value, XINSERT_NOREPLACE);
inst_hilight_hash_lookup(i, entry->value, XINSERT_NOREPLACE);
}
my_strdup(_ALLOC_ID_, &propagate_str, get_tok_value(rct[j].prop_ptr, "propag", 0));
if(propagate_str) {
@ -1204,7 +1204,7 @@ static void send_net_to_bespice(int simtype, const char *node)
my_strdup2(_ALLOC_ID_, &p, xctx->sch_path[xctx->currsch]+1);
for(k=1; k<=tok_mult; ++k) {
my_strdup(_ALLOC_ID_, &t, find_nth(expanded_tok, ",", "", 0, k));
/* bespice command syntax :
/* bespice command syntax :
add_voltage_on_spice_node_to_plot <plot name> <section name> <hierarchical spice node name> <flag clear> [<color>]
plot name is "*" => automatic
section name is empty => automatic or user defined
@ -1298,7 +1298,7 @@ static void send_current_to_bespice(int simtype, const char *node)
const char *tok;
char color_str[30];
char *t=NULL, *p=NULL;
set_rawfile_for_bespice();
if(!node || !node[0]) return;
@ -1311,7 +1311,7 @@ static void send_current_to_bespice(int simtype, const char *node)
my_strdup2(_ALLOC_ID_, &p, xctx->sch_path[xctx->currsch]+1);
for(k=1; k<=tok_mult; ++k) {
my_strdup(_ALLOC_ID_, &t, find_nth(expanded_tok, ",", "", 0, k));
/* bespice command syntax :
/* bespice command syntax :
add_current_through_spice_device_to_plot <plot name> <section name> <hierarchical spice device name> <flag clear> [<color>]
plot name is "*" => automatic
section name is empty => automatic or user defined
@ -1358,7 +1358,7 @@ static void send_current_to_graph(char **s, int simtype, const char *node)
my_snprintf(ss, S(ss), "i(%s%s%s) %d", there_is_hierarchy ? "v." : "", path, t, c);
my_strcat(_ALLOC_ID_, s, ss);
} else { /* Xyce */
/*
/*
my_snprintf(ss, S(ss), "%s%s%s#branch %d", there_is_hierarchy ? "v." : "",
path, (there_is_hierarchy ? t+1 : t) , c);
*/
@ -1428,7 +1428,7 @@ void propagate_hilights(int set, int clear, int mode)
dbg(1, "propagate_hilights() for %s\n", xctx->current_name);
en_hi = tclgetboolvar("en_hilight_conn_inst");
prepare_netlist_structs(0);
for(i = 0; i < xctx->instances; ++i) {
if(xctx->inst[i].ptr < 0 ) {
@ -1437,7 +1437,7 @@ void propagate_hilights(int set, int clear, int mode)
continue;
}
type = (xctx->inst[i].ptr+ xctx->sym)->type;
hilight_connected_inst = en_hi &&
hilight_connected_inst = en_hi &&
((xctx->inst[i].flags & HILIGHT_CONN) || ((xctx->inst[i].ptr+ xctx->sym)->flags & HILIGHT_CONN));
/* hilight/clear instances with highlight=true attr set and en_hilight_conn_inst option is set ... */
if(type && !IS_LABEL_SH_OR_PIN(type)) {
@ -1473,7 +1473,7 @@ void propagate_hilights(int set, int clear, int mode)
entry=bus_hilight_hash_lookup( xctx->inst[i].node[0], 0, XLOOKUP);
if(entry && set) {
xctx->inst[i].color = entry->value;
inst_hilight_hash_lookup(i, entry->value, XINSERT_NOREPLACE);
inst_hilight_hash_lookup(i, entry->value, XINSERT_NOREPLACE);
}
else if(!entry && clear) xctx->inst[i].color = -10000;
}
@ -1702,7 +1702,7 @@ static void create_simdata(void)
xctx->simdata[i].pin[j].go_to=NULL;
my_snprintf(function, S(function), "function%d", j);
my_strdup(_ALLOC_ID_, &xctx->simdata[i].pin[j].function, get_tok_value(symbol->prop_ptr, function, 0));
my_strdup(_ALLOC_ID_, &xctx->simdata[i].pin[j].go_to,
my_strdup(_ALLOC_ID_, &xctx->simdata[i].pin[j].go_to,
get_tok_value(symbol->rect[PINLAYER][j].prop_ptr, "goto", 0));
str = get_tok_value(symbol->rect[PINLAYER][j].prop_ptr, "clock", 0);
xctx->simdata[i].pin[j].clock = str[0] ? str[0] - '0' : -1;
@ -1810,9 +1810,9 @@ static void propagate_logic()
if(newval != 4 && xctx->simdata[i].pin[propagate].value != val ) {
found=1; /* keep looping until no more nets are found. */
xctx->simdata[i].pin[propagate].value = val;
dbg(1, "propagate_logic(): DRIVERS inst %s pin %d, net %s --> value %d\n",
dbg(1, "propagate_logic(): DRIVERS inst %s pin %d, net %s --> value %d\n",
xctx->inst[i].instname, j, xctx->inst[i].node[propagate], val);
}
}
} /* while( ith-goto ) */
} /* if((xctx->simdata && xctx->simdata[i].pin && xctx->simdata[i].pin[j].go_to) */
} /* for(j...) */
@ -1825,7 +1825,7 @@ static void propagate_logic()
for(j=0;j < xctx->simdata[i].npin; ++j) {
if(xctx->simdata[i].pin[j].value != -10000) {
if(!xctx->inst[i].node || !xctx->inst[i].node[j]) continue;
entry = hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP);
entry = hilight_hash_lookup(xctx->inst[i].node[j], 0, XLOOKUP);
if(!entry || xctx->hilight_time != entry->time) {
hilight_hash_lookup(xctx->inst[i].node[j], xctx->simdata[i].pin[j].value, XINSERT);
dbg(1, "propagate_logic(): UPDATE1 inst %s pin %d, net %s --> value %d\n",
@ -1860,7 +1860,7 @@ void logic_set(int value, int num, const char *net_name)
int big = xctx->wires> 2000 || xctx->instances > 2000 ;
static const int map[] = {LOGIC_0, LOGIC_1, LOGIC_X, LOGIC_Z, LOGIC_NOUP};
Hilight_hashentry *entry;
tclsetvar("tclstop", "0");
prepare_netlist_structs(0);
if(!xctx->simdata) create_simdata();
@ -2060,7 +2060,7 @@ void select_hilight_net(void)
for(i=0;i<xctx->instances; ++i) {
type = (xctx->inst[i].ptr+ xctx->sym)->type;
hilight_connected_inst = en_hi &&
hilight_connected_inst = en_hi &&
((xctx->inst[i].flags & HILIGHT_CONN) || ((xctx->inst[i].ptr+ xctx->sym)->flags & HILIGHT_CONN));
if( xctx->inst[i].color != -10000) {
dbg(1, "select_hilight_net(): instance %d flags & HILIGHT_CONN true\n", i);
@ -2092,7 +2092,7 @@ void select_hilight_net(void)
xctx->need_reb_sel_arr = 1;
rebuild_selected_array(); /* sets or clears xctx->ui_state SELECTION flag */
redraw_hilights(0);
}
@ -2324,13 +2324,13 @@ void print_hilight_net(int show)
/* before invoking this function, in this case --> skip */
if(node_entry && !strcmp(xctx->sch_path[xctx->currsch], entry->path)) {
if(show==3) {
if(xctx->netlist_type == CAD_SPICE_NETLIST)
fprintf(fd, ".save v(%s%s)\n",
entry->path + 1,
if(xctx->netlist_type == CAD_SPICE_NETLIST)
fprintf(fd, ".save v(%s%s)\n",
entry->path + 1,
entry->token[0] == '#' ? entry->token + 1 : entry->token );
else
fprintf(fd, "%s%s\n",
entry->path + 1,
fprintf(fd, "%s%s\n",
entry->path + 1,
entry->token[0] == '#' ? entry->token + 1 : entry->token );
} else if(show==1) {
fprintf(fd, "%s\n", entry->token);
@ -2407,7 +2407,7 @@ void list_hilights(int all)
entry->token, " ", my_itoa(entry->value), "\n", NULL);
}
}
} else
} else
for(i=0;i<HASHSIZE; ++i) {
entry=xctx->hilight_table[i];
while(entry) {

24
src/hspice_backannotate.tcl
View File

@ -1,21 +1,21 @@
#
# File: hspice_backannotate.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -100,24 +100,24 @@ proc annotate {} {
xschem push_undo
xschem set no_undo 1
xschem set no_draw 1
read_hspice_log $::netlist_dir/hspice.out
set lastinst [xschem get instances]
for { set i 0 } { $i < $lastinst } {incr i } {
set name [xschem getprop instance $i name]
set type [xschem getprop instance $i cell::type]
if { $type == "probe"} {
if { $type == "probe"} {
set net [xschem instance_net $i p]
if {[catch {xschem setprop -fast instance $i voltage [get_voltage $net]} err]} {
puts "1 error : $err net: $net"
}
}
if { $type == "current_probe"} {
if { $type == "current_probe"} {
if {[catch {xschem setprop -fast instance $i current [get_current $name]} err]} {
puts "2 error : $err"
}
}
if { $type == "differential_probe"} {
if { $type == "differential_probe"} {
set netp [xschem instance_net $i p]
set netm [xschem instance_net $i m]
if {[catch {xschem setprop -fast instance $i voltage [get_diff_voltage $netp $netm]} err]} {
@ -126,13 +126,13 @@ proc annotate {} {
}
# puts "$i $name $type"
}
# re-enable undo and draw
xschem set no_undo 0
xschem set no_draw 0
xschem redraw
### xschem setprop instructions have not altered circuit topology so
### xschem setprop instructions have not altered circuit topology so
### in this case a connectivity rebuild is not needed.
# xschem rebuild_connectivity
#

16
src/import_opus_symbols.awk
View File

@ -1,8 +1,8 @@
#!/usr/bin/awk -f
# import a opus generated list of symbols (cell_pinouts)
# (generated with the cell_binding.il skill)
# import a opus generated list of symbols (cell_pinouts)
# (generated with the cell_binding.il skill)
# and outputs a tcl source file.
# this source file can be sourced by the xschem tcl interpreter
# this source file can be sourced by the xschem tcl interpreter
# to generate schematics and symbols
# IMPORTANT: set the target library in library variable !!!!
#
@ -26,7 +26,7 @@ BEGIN{
delete opins
delete iopins
}
if($6=="input") ipins[$4]=1
if($6=="output") opins[$4]=1
if($6=="inputOutput") iopins[$4]=1
@ -43,20 +43,20 @@ END{
function print_cell()
{
print "set cellname " library "/" oldcell
printf "set gensch_i_pin {"
for(i in ipins) {
printf "set gensch_i_pin {"
for(i in ipins) {
printf "%s ", i
}
printf "}\n"
printf "set gensch_o_pin {"
for(i in opins) {
for(i in opins) {
printf "%s ", i
}
printf "}\n"
printf "set gensch_io_pin {"
for(i in iopins) {
for(i in iopins) {
printf "%s ", i
}
printf "}\n"

12
src/in_memory_undo.c
View File

@ -142,7 +142,7 @@ static void free_undo_symbols(int slot)
}
my_free(_ALLOC_ID_, &sym->poly[c]);
sym->polygons[c] = 0;
for(j = 0;j<sym->lines[c]; ++j) {
if(sym->line[c][j].prop_ptr != NULL) {
my_free(_ALLOC_ID_, &sym->line[c][j].prop_ptr);
@ -150,7 +150,7 @@ static void free_undo_symbols(int slot)
}
my_free(_ALLOC_ID_, &sym->line[c]);
sym->lines[c] = 0;
for(j = 0;j<sym->arcs[c]; ++j) {
if(sym->arc[c][j].prop_ptr != NULL) {
my_free(_ALLOC_ID_, &sym->arc[c][j].prop_ptr);
@ -158,7 +158,7 @@ static void free_undo_symbols(int slot)
}
my_free(_ALLOC_ID_, &sym->arc[c]);
sym->arcs[c] = 0;
for(j = 0;j<sym->rects[c]; ++j) {
if(sym->rect[c][j].prop_ptr != NULL) {
my_free(_ALLOC_ID_, &sym->rect[c][j].prop_ptr);
@ -333,7 +333,7 @@ void mem_push_undo(void)
xctx->uslot[slot].pptr[c][i].selected_point = my_malloc(_ALLOC_ID_, points * sizeof(unsigned short));
memcpy(xctx->uslot[slot].pptr[c][i].x, xctx->poly[c][i].x, points * sizeof(double));
memcpy(xctx->uslot[slot].pptr[c][i].y, xctx->poly[c][i].y, points * sizeof(double));
memcpy(xctx->uslot[slot].pptr[c][i].selected_point, xctx->poly[c][i].selected_point,
memcpy(xctx->uslot[slot].pptr[c][i].selected_point, xctx->poly[c][i].selected_point,
points * sizeof(unsigned short));
my_strdup(_ALLOC_ID_, &xctx->uslot[slot].pptr[c][i].prop_ptr, xctx->poly[c][i].prop_ptr);
}
@ -386,7 +386,7 @@ void mem_push_undo(void)
}
/* redo:
* 0: undo (with push current state for allowing following redo)
* 0: undo (with push current state for allowing following redo)
* 4: undo, do not push state for redo
* 1: redo
* 2: read top data from undo stack without changing undo stack
@ -480,7 +480,7 @@ void mem_pop_undo(int redo, int set_modify_status)
xctx->poly[c][i].selected_point = my_malloc(_ALLOC_ID_, points * sizeof(unsigned short));
memcpy(xctx->poly[c][i].x, xctx->uslot[slot].pptr[c][i].x, points * sizeof(double));
memcpy(xctx->poly[c][i].y, xctx->uslot[slot].pptr[c][i].y, points * sizeof(double));
memcpy(xctx->poly[c][i].selected_point, xctx->uslot[slot].pptr[c][i].selected_point,
memcpy(xctx->poly[c][i].selected_point, xctx->uslot[slot].pptr[c][i].selected_point,
points * sizeof(unsigned short));
}
}

12
src/label_compactor.awk
View File

@ -45,7 +45,7 @@ function compact_label(lab)
if( start!=-1 && lab_array[i] != name )
print_signal()
if( (startbus!=-1) && (lab_name(lab_array[i]) != busname) )
if( (startbus!=-1) && (lab_name(lab_array[i]) != busname) )
print_bus()
# 09032004 fix for errors on buses like D[5],D[4],D[2],D[1]
if( (startbus!=-1) && (lab_name(lab_array[i]) == busname) && (bus_current+1!=last) )
@ -58,7 +58,7 @@ function compact_label(lab)
print_bus()
}
else {
if(lab_name(lab_array[i]) != busname&& startbus!=-1)
if(lab_name(lab_array[i]) != busname&& startbus!=-1)
print_bus()
if( (start!=-1) && ( lab_array[i] != name) )
print_signal()
@ -97,7 +97,7 @@ function lab_name(lab)
}
function lab_index(lab)
function lab_index(lab)
{
sub(/.*\[/,"",lab)
sub(/\].*/,"",lab)
@ -107,7 +107,7 @@ function lab_index(lab)
# end user code
{
a[lines++] = $0
a[lines++] = $0
}
function beginfile(f)
@ -123,8 +123,8 @@ function endfile(f)
print a[i] > f
}
close(f)
}
}
' $@
' $@

4
src/main.c
View File

@ -45,7 +45,7 @@ static void sig_handler(int s){
fprintf(errfp, "xinit(): problems creating emergency save dir\n");
tcleval("exit 1");
}
if(rename(xctx->undo_dirname, emergency_dir)) {
fprintf(errfp, "rename dir %s to %s failed\n", xctx->undo_dirname, emergency_dir);
}
@ -101,7 +101,7 @@ int main(int argc, char **argv)
setvbuf(stdout, NULL, _IOLBF, 0); /* set to line buffer mode */
if(statbuf.st_mode & S_IFIFO) stdin_is_a_fifo = 1; /* input coming from a command pipe */
}
if(!stdin_is_a_fifo && getpgrp() != tcgetpgrp(STDOUT_FILENO) && !cli_opt_no_readline) {
cli_opt_detach = 1;
}

2
src/make_edif.awk
View File

@ -6,7 +6,7 @@
# Warning:
# can be used on vhdl entities that have std_logic/std_logic_vector
# pins, any other types not recognized
# Also, types and ranges must NOT be referenced in packages or
# Also, types and ranges must NOT be referenced in packages or
# as constants/variables, if this is the case use the design_analyzer
# "EDIF save as" facility
#

34
src/make_sch_from_cadence_pin.awk
View File

@ -24,7 +24,7 @@ END { endfile(_filename_) }
#-----------------------------------------------------
function beginfile(fname)
function beginfile(fname)
{
ip=0; op=0; i=0
delete pin
@ -34,36 +34,36 @@ function beginfile(fname)
}
{
gsub(/</,"[",$0)
gsub(/>/,"]",$0)
gsub(/</,"[",$0)
gsub(/>/,"]",$0)
}
/ inputOutput *$/{
op++;
op++;
i++
pin[i] = $1
dir[i] = "B"
}
/ output *$/{
op++;
op++;
i++
pin[i] = $1
dir[i] = "O"
}
/ input *$/{
ip++;
ip++;
i++
pin[i] = $1
dir[i] = "I"
}
function endfile(fname)
function endfile(fname)
{
sub(/\/pin\/text\.txt/,"",fname)
sub(/.*\//,"",fname)
fname = fname ".sch"
sub(/.*\//,"",fname)
fname = fname ".sch"
dir["n"] = pin["n"] = i
compact_pinlist(pin,dir)
@ -129,24 +129,24 @@ function compact_pinlist(pin, dir ,i,ii,base,curr,curr_n,np)
delete pin_ret
delete net_ret
delete dir_ret
np=pin["n"]
if(np) {
ii=1
for(i=1;i<=np;i++) {
base =lab_name( pin[i] )
if(i==1) {curr=base; curr_n=i}
else {
else {
if(base != curr) {
pin_ret[ii] = compact_label(pin,curr_n,i-1)
dir_ret[ii] = dir[i-1]
dir_ret[ii] = dir[i-1]
ii++
curr=base;curr_n=i
}
}
}
pin_ret[ii] = compact_label(pin,curr_n,np)
dir_ret[ii] = dir[np]
dir_ret[ii] = dir[np]
pin_ret["n"] = dir_ret["n"] = ii
}
}
@ -165,10 +165,10 @@ function compact_label(ar,a,b, ret,start,i)
else {ret = ret ar[i-1] ","; start=i }
}
}
else if(lab_name(ar[i])!=lab_name(ar[i-1]) ||
( lab_index(ar[i]) != lab_index(ar[i-1])-1 &&
else if(lab_name(ar[i])!=lab_name(ar[i-1]) ||
( lab_index(ar[i]) != lab_index(ar[i-1])-1 &&
lab_index(ar[i]) != lab_index(ar[i-1])+1) ) {
if(start<i-1)
if(start<i-1)
ret = ret lab_name(ar[start]) "[" lab_index(ar[start]) ":" lab_index(ar[i-1]) "],"
else
ret = ret lab_name(ar[start]) "[" lab_index(ar[start]) "],"
@ -180,7 +180,7 @@ function compact_label(ar,a,b, ret,start,i)
if(start < b) ret = ret (b-start+1) "*" ar[b]
else ret = ret ar[b]
}
else if(start<b)
else if(start<b)
ret = ret lab_name(ar[start]) "[" lab_index(ar[start]) ":" lab_index(ar[b]) "]"
else
ret = ret lab_name(ar[b]) "[" lab_index(ar[b]) "]"

136
src/make_sch_from_spice.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: make_sch_from_spice.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -39,8 +39,8 @@ BEGIN{
while ( "ls $HOME/.xschem/xschem_library/xschem_sky130/sky130_stdcells/*.sym"|getline sym )
{
insert_symbol(sym, "sky130_stdcells")
}
}
# while ( "ls $HOME/share/xschem/xschem_library/devices/*.sym"|getline sym )
# {
@ -55,7 +55,7 @@ BEGIN{
inherited_pin["VPWR"]=1
inherited_pin["VNB"]=1
inherited_pin["VPB"]=1
skip_symbol_prefix= "sky130_fd_sc_hd__"
# sym_type = "subcircuit"
sym_type = "primitive" # do not use schematics although they will be generated
@ -82,19 +82,19 @@ BEGIN{
########################## END JOIN ##########################
skip=0
for(i=0;i<netlist_lines; i++) {
for(i=0;i<netlist_lines; i++) {
$0=netlist[i]
process_subckts()
}
skip=0
for(i=0;i<netlist_lines; i++) {
for(i=0;i<netlist_lines; i++) {
$0=netlist[i]
process()
}
}
function translate(cellname)
function translate(cellname)
{
if (cellname=="nmos") return "enbsim3"
else if(cellname=="pmos") return "epbsim3"
@ -136,7 +136,7 @@ function insert_symbol(sym, lib, n,cellname, name, dir, tmp)
function process_subckts( j, i,name)
{
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
if(skip==1) return
if(toupper($1) ==".SUBCKT") {
curr_subckt=$2
@ -155,7 +155,7 @@ function process_subckts( j, i,name)
pin_ar[curr_subckt,"format"]=pin_ar[curr_subckt,"format"] " @@" $i
j++
} else {
if(pin_ar[curr_subckt,"extra"])
if(pin_ar[curr_subckt,"extra"])
pin_ar[curr_subckt,"extra"] = pin_ar[curr_subckt,"extra"] " " $i
else
pin_ar[curr_subckt,"extra"] = $i
@ -167,10 +167,10 @@ function process_subckts( j, i,name)
pin_ar[curr_subckt,"n"]=j-1
if(skip_symbol_prefix)
pin_ar[curr_subckt,"template"] = pin_ar[curr_subckt,"template"] " prefix=" skip_symbol_prefix
get_template(template)
get_template(template)
if(skip_symbol_prefix)
pin_ar[curr_subckt,"extra"] = pin_ar[curr_subckt,"extra"] " prefix"
print "\n\n\n process_subckt() : " curr_subckt "--> "
print "\n\n\n process_subckt() : " curr_subckt "--> "
for(i=1; i<= pin_ar[curr_subckt,"n"]; i++) printf "%s ", pin_ar[curr_subckt,i]; printf "\n"
}
else if($1 ~ /^\*\.PININFO/) {
@ -179,27 +179,27 @@ function process_subckts( j, i,name)
if($i ~ /:I$/ ) pin_ar[curr_subckt, "dir", name] = "I"
else if($i ~ /:O$/ ) pin_ar[curr_subckt, "dir", name] = "O"
else if($i ~ /:B$/ ) pin_ar[curr_subckt, "dir", name] = "B"
else { print "ERROR in .PININFO: ", $i " --> " $0 ; exit}
else { print "ERROR in .PININFO: ", $i " --> " $0 ; exit}
}
}
else if(toupper($1) ~ /^\*\.(I|O|IO)PIN/) {
if($1 ~ /^\*\.ipin/) { pin_ar[curr_subckt, "dir", $2] = "I" }
else if($1 ~ /^\*\.opin/) { pin_ar[curr_subckt, "dir", $2] = "O" }
else if($1 ~ /^\*\.iopin/) { pin_ar[curr_subckt, "dir", $2] = "B" }
if($1 ~ /^\*\.ipin/) { pin_ar[curr_subckt, "dir", $2] = "I" }
else if($1 ~ /^\*\.opin/) { pin_ar[curr_subckt, "dir", $2] = "O" }
else if($1 ~ /^\*\.iopin/) { pin_ar[curr_subckt, "dir", $2] = "B" }
}
}
function get_template(t, templ, i)
function get_template(t, templ, i)
{
templ=""
if(t) for(i=t;i<=NF;i++) {
templ = templ $i " "
templ = templ $i " "
}
pin_ar[curr_subckt,"template"] = pin_ar[curr_subckt,"template"] " " templ
}
function process( i,name,param)
{
print "process(): skip = " skip " --> " $0
@ -223,7 +223,7 @@ function process( i,name,param)
sp=ip=op=n_pin=0
all_signals=""
delete net_ar
subckt_netlist = "" # 20111009 all netlist lines except component instances (X)
subckt_netlist = "" # 20111009 all netlist lines except component instances (X)
}
else if(toupper($1) ~ /^.ENDS/) {
@ -231,12 +231,12 @@ function process( i,name,param)
compact_pinlist( "" , curr_subckt)
print "----------------------------------------------------------"
for(i=1;i<= dir_ret["n"] ; i++) {
print dir_ret[i] " " pin_ret[i]
}
}
print "\n\n"
print_sch(curr_subckt, dir_ret, pin_ret)
print_sym(curr_subckt, pin_ar[curr_subckt,"template"], \
pin_ar[curr_subckt,"format"], pin_ar[curr_subckt,"name"], \
@ -303,7 +303,7 @@ function process( i,name,param)
#print " dir_ret " i " ------> " dir_ret[i] " " pin_ret[i] " <-- " net_ret[i]
}
#print "\n\n"
param = get_param(param)
param = get_param(param)
print_signals( inst, inst_sub, param, pin_ret, dir_ret, net_ret )
}
else { # other components, M, R, C, D, .... 20111009
@ -327,7 +327,7 @@ function compact_pinlist(inst,inst_sub , prevgroup, group,i,ii,
delete pin_ret
delete net_ret
delete dir_ret
np=pin_ar[inst_sub,"n"]
# print " compact_pinlist: inst=" inst " np= " np " inst_sub=" inst_sub
if(np) {
@ -340,7 +340,7 @@ function compact_pinlist(inst,inst_sub , prevgroup, group,i,ii,
base =lab_name( pin_ar[inst_sub,i] )
if(i==1) {prevgroup=group; curr=base; curr_n=i}
else {
else {
if(prevgroup || base != curr) {
if(prevgroup) pin_ret[ii] = pin_ar[inst_sub,i-1]
else pin_ret[ii] = compact_label(inst_sub,pin_ar,curr_n,i-1)
@ -407,7 +407,7 @@ function compact_label_str(str, a, b, ar, ret,start,i)
}
else if( lab_index(ar[start])!=lab_index(ar[i]) && # range count != element count
abs(start-i)!=abs(lab_index(ar[start])-lab_index(ar[i]))) {
abs(start-i)!=abs(lab_index(ar[start])-lab_index(ar[i]))) {
if(start<i-1 && lab_index(ar[start]) == lab_index(ar[i-1]) )
ret = ret (i-start) "*" ar[i-1] ",";
else if(start<i-1)
@ -463,14 +463,14 @@ function compact_label(name, ar,a,b, ret,start,i)
else if(lab_name(ar[name,i])!=lab_name(ar[name,i-1])) {
if(start<i-1 && lab_index(ar[name,start]) == lab_index(ar[name,i-1]) )
ret = ret (i-start) "*" ar[name,i-1] ",";
else if(start<i-1)
else if(start<i-1)
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) ":" lab_index(ar[name,i-1]) "],"
else
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) "],"
start=i
}
else if(lab_index(ar[name,i]) != lab_index(ar[name,i-1])-1 &&
lab_index(ar[name,i]) != lab_index(ar[name,i-1])+1 ) {
lab_index(ar[name,i]) != lab_index(ar[name,i-1])+1 ) {
if(start<i-1 && lab_index(ar[name,start]) == lab_index(ar[name,i-1]) )
ret = ret (i-start) "*" ar[name,i-1] ",";
else if(start<i-1)
@ -495,9 +495,9 @@ function compact_label(name, ar,a,b, ret,start,i)
if(start < b) ret = ret (b-start+1) "*" ar[name,b]
else ret = ret ar[name,b]
}
else if(start<b && lab_index(ar[name,start]) == lab_index(ar[name,b]))
ret = ret (b-start+1) "*" ar[name,b]
else if(start<b)
else if(start<b && lab_index(ar[name,start]) == lab_index(ar[name,b]))
ret = ret (b-start+1) "*" ar[name,b]
else if(start<b)
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) ":" lab_index(ar[name,b]) "]"
else
ret = ret lab_name(ar[name,b]) "[" lab_index(ar[name,b]) "]"
@ -537,11 +537,11 @@ function print_sch(schname, dir, pin,
else if(dir[i]=="O" || dir[i]=="B") op++
else {print "ERROR: print_sch(): undefined dir[i], i=",i, "schname=", schname, "pin[i]=", pin[i]; exit}
}
y=0
x=-40
sch_x_offset=230
for(i=1;i<=n_pin;i++)
{
pin_dir=dir[i]
@ -580,12 +580,12 @@ function print_signals( inst_name, component_name, param, pin,dir,net,
n_pin=pin["n"]
n_net=net["n"]
n_dir=dir["n"]
print " print_signals() : component_name = ", component_name
if(n_dir != n_pin) { print " n_dir vs n_pin mismatch: inst / comp = " inst_name " / " component_name ; exit }
if(n_net != n_pin) { print " n_net vs n_pin mismatch: inst / comp = " inst_name " / " component_name ; exit }
ip=op=0
ip=op=0
for(i=1; i<=n_net; i++) {
if(dir[i] ~ /[OB]/) {
op++
@ -604,7 +604,7 @@ function print_signals( inst_name, component_name, param, pin,dir,net,
{
yoffset=prev_size=0
xoffset+=920
}
}
yoffset += ((prev_size+n)/2+1)*space
inum =onum=0
@ -614,44 +614,44 @@ function print_signals( inst_name, component_name, param, pin,dir,net,
idx=(component_name SUBSEP pin[i])
if( idx in pin_x)
{
#print "print_signals() : " idx " found in library"
#print "print_signals() : " idx " found in library"
xpin=xoffset+pin_x[idx]
ypin=yoffset+pin_y[idx]
}
else
{
#print "print_signals() : " idx " NOT found in library"
#print "print_signals() : " idx " NOT found in library"
if(curr_dir=="O" || curr_dir=="B") {
xpin=-x+xoffset
ypin=y+onum*space+yoffset
onum++
}
else {
xpin=x+xoffset
xpin=x+xoffset
ypin=y+inum*space+yoffset
inum++
}
}
if(curr_dir=="I")
{
all_signals = all_signals "C {" devices_prefix "lab_pin.sym} " xpin " " ypin " 0 0 " \
" {name=p" p_pin++ " lab=" net[i] " "
all_signals = all_signals "}\n"
" {name=p" p_pin++ " lab=" net[i] " "
all_signals = all_signals "}\n"
}
if(curr_dir=="O")
{
all_signals = all_signals "C {" devices_prefix "lab_pin.sym} " xpin " " ypin " 0 1 " \
" {name=p" p_pin++ " lab=" net[i] " "
all_signals = all_signals "}\n"
" {name=p" p_pin++ " lab=" net[i] " "
all_signals = all_signals "}\n"
}
if(curr_dir=="B")
{
all_signals = all_signals "C {" devices_prefix "lab_pin.sym} " xpin " " ypin " 0 1 " \
" {name=p" p_pin++ " lab=" net[i] " "
all_signals = all_signals "}\n"
" {name=p" p_pin++ " lab=" net[i] " "
all_signals = all_signals "}\n"
}
}
@ -667,7 +667,7 @@ function print_signals( inst_name, component_name, param, pin,dir,net,
prev_size=n
if( idx in pin_x) prev_size+=8
}
}
@ -676,7 +676,7 @@ function print_signals( inst_name, component_name, param, pin,dir,net,
function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin,
size,space,width,lwidth,textdist,labsize,titlesize,
i,name,text_voffset,lab_voffset,ip,op,n_pin ,m,x,y,n,
iii,ooo)
iii,ooo)
{
size=2.5
space=20
@ -706,9 +706,9 @@ function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin
iii = format_translate(template, extra)
if(iii) iii = " " iii
# since awk strings use backslash escapes and sub also uses backslash escapes (example for \& substitution)
# since awk strings use backslash escapes and sub also uses backslash escapes (example for \& substitution)
# there are 2 levels of escape substitutions, we need \\\\ to generate one \.
# in the xschem file \\\\ is reduced to \\ in the format string and finally format contains one \
# in the xschem file \\\\ is reduced to \\ in the format string and finally format contains one \
if(skip_symbol_prefix) sub(skip_symbol_prefix, "@prefix\\\\\\\\\\\\\\\\", subckt_name)
print "format=\"@name" format " " subckt_name iii "\"" > sym
print "template=\"name=x1" template "\"" > sym
@ -717,18 +717,18 @@ function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin
# titlesize, titlesize, "{}" >sym
print "T {@symname}" ,0, -text_voffset*titlesize,0,0,
titlesize, titlesize, "{hcenter=true}" >sym
n_pin=pin["n"]
ip=op=0
ip=op=0
for(i=1; i<=n_pin; i++) {
if(dir[i] ~ /[OB]/) {
op++
}
op++
}
else if(dir[i] ~ /I/) ip++
else {print "ERROR: print_sym(): undefined dir[] i=" i " inst=" inst " sub=" component_name ; exit}
}
}
n=ip;if(op>n) n=op
@ -776,7 +776,7 @@ function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin
}
close(sym)
}
#------------------------------
@ -787,12 +787,12 @@ function escape_brackets(s , ss)
return ss
}
function abs(a)
function abs(a)
{
return a>0 ? a: -a
}
function format_translate(s, extra, n_extra, extra_arr, extra_hash, c,quote,str,n,i,ss,sss)
function format_translate(s, extra, n_extra, extra_arr, extra_hash, c,quote,str,n,i,ss,sss)
{
# 20140321
@ -810,19 +810,19 @@ function format_translate(s, extra, n_extra, extra_arr, extra_hash, c
str=""
n_extra = split(extra, extra_arr)
for(i = 1; i <= n_extra; i++) extra_hash[ extra_arr[i] ] = 1
n=split(s,ss)
for(i=1;i<=n;i++) {
gsub(SUBSEP," ", ss[i])
print "subckt params: " ss[i]
if(ss[i] ~ /[^=]+=[^=]+/) {
split(ss[i],sss,"=")
split(ss[i],sss,"=")
if(!(sss[1] in extra_hash)) ss[i] = sss[1] "=@" sss[1]
else ss[i] = ""
}
str = str ss[i]
if(i<n && ss[i] ) str=str " "
if(i<n && ss[i] ) str=str " "
}
delete extra_hash
return str

138
src/make_sch_from_vhdl.awk
View File

@ -133,7 +133,7 @@ BEGIN{
}
(package_body>0 || package_decl) { next }
@ -188,7 +188,7 @@ BEGIN{
gsub(/[ \t]+/,"",index_high)
}
else
else
{
index_high=index_low=0
}
@ -200,7 +200,7 @@ BEGIN{
# A_READ(21) => ADD_READ2_N(21),
# where A_READ is a component pin declared as:
# A_READ : IN std_logic_vector(21 TO 22);
#
#
# then in the schematic the assignment will look like:
#
# |
@ -223,17 +223,17 @@ BEGIN{
if(is_bus) pin_label=pin_label "[" index_high ":" index_low "]"
if($0 ~ /:=/)
{
if($0 ~ /:=/)
{
value=$0
sub(/^.*:= */,"", value) #15122003 added spaces after :=
sub(/;/,"", value)
gsub(/"/,"\\\\\"", value)
value= "\"" value "\""
}
type=$3
if(type=="in")
if(type=="in")
{
type="ipin"
type_pin[n_pin]=sig_type
@ -284,8 +284,8 @@ BEGIN{
if(sig_type ~ /[ \t]+/) sig_type="\"" sig_type "\""
pin_label=$1
if($0 ~ /:=/)
{
if($0 ~ /:=/)
{
value=$0
sub(/^.*:= */,"", value) #15122003 spaces after := added
sub(/;/,"", value)
@ -306,11 +306,11 @@ BEGIN{
# end component
( $1=="end" && $2 ~ "component" && !package_decl){
end_component=1
end_component=1
if(!(toupper(name) in cell))
{
#print ">>>>> end component: " name
print "G {}" > schname
print "G {}" > schname
print_sch(schname,type_pin, dir_pin, value_pin, class_pin, num_pin, opin, ipin,spin,
n_pin, ip, op, sp)
close(schname)
@ -448,8 +448,8 @@ inline_function==1{
#print "port assignment: " component_hi[component_name,formal_basename], component_low[component_name,formal_basename]
#
# This piece of code deals with single bit assignments on
# vector ports, so we group the single bits in a unique node label,
# preserving the right order
# vector ports, so we group the single bits in a unique node label,
# preserving the right order
#
if(doing_slice && prev_formal_basename!=formal_basename)
{
@ -457,16 +457,16 @@ inline_function==1{
}
if(formal_index ~ /^[0-9]+$/ && component_pins[component_name,formal_basename]>1)
{
{
#print "port assignment: slice port assign: " pin_label, "formal_index=" formal_index
prev_formal_basename=formal_basename
doing_slice=1
slice_pin_array[formal_index]=pin_label
next
}
}
else if(formal_index ~ /[0-9]+:[0-9]+/ && component_pins[component_name,formal_basename]>1)
{
#print "port assignment: slice bus port assign"
#print "port assignment: slice bus port assign"
split(formal_index, formal_index_array,":")
formal_index_array[1]= formal_index_array[1]+0
formal_index_array[0]= formal_index_array[0]+0
@ -496,8 +496,8 @@ inline_function==1{
#
# This piece of code deals with single bit assignments on
# vector ports, so we group the single bits in a unique node label,
# preserving the right order
# vector ports, so we group the single bits in a unique node label,
# preserving the right order
#
function print_slice( c_h,c_l, slice, slice_pin )
{
@ -586,9 +586,9 @@ function add_inst_pin(pin_label)
{
if($2=="architecture") tmp=$3 # 20071213 handle "end arhitecture name" vs "end name"
else tmp=$2
}
if(tmp==arch_label)
if(tmp==arch_label)
{
start_code=0
next
@ -605,12 +605,12 @@ function add_inst_pin(pin_label)
if(doing_slice)
{
#print " slice port assign 3"
#print " slice port assign 3"
print_slice()
}
start_inst=0
print_signals(inst_name, component_name, i_name_pin, i_type_pin, i_dir_pin, i_value_pin,i_class_pin, i_num_pin,
print_signals(inst_name, component_name, i_name_pin, i_type_pin, i_dir_pin, i_value_pin,i_class_pin, i_num_pin,
i_opin, i_ipin,i_n_pin, i_ip, i_op)
}
@ -679,17 +679,17 @@ function add_inst_pin(pin_label)
}
pin_label=$1 #toupper
if(is_bus) pin_label=pin_label "[" index_high ":" index_low "]"
if($0 ~ /:=/)
{
if($0 ~ /:=/)
{
value=$0
sub(/^.*:= */,"", value) #15122003 spaces after := added
sub(/;/,"", value)
gsub(/"/,"\\\\\"", value)
value= "\"" value "\""
}
type=$3
if(type=="in")
if(type=="in")
{
type="ipin"
e_type_pin[e_n_pin]=sig_type
@ -737,8 +737,8 @@ function add_inst_pin(pin_label)
sub(/[ \t]*(:=|;).*$/,"",sig_type)
if(sig_type ~ /[ \t]+/) sig_type="\"" sig_type "\""
pin_label=$1
if($0 ~ /:=/)
{
if($0 ~ /:=/)
{
value=$0
sub(/^.*:= */,"", value) # 15122003 spaces after := added
sub(/;/,"", value)
@ -759,7 +759,7 @@ function add_inst_pin(pin_label)
# end entity
( $1=="end" && $2 ~ name) || ( $1=="end" && $2=="entity" && $3 ~ name) { # 20071213 handle "end entity name"
print "end entity: " $0
end_entity=1
end_entity=1
}
@ -769,26 +769,26 @@ function add_inst_pin(pin_label)
/^[ \t]*signal[ \t]/,/;/ {
if(start_arch==1)
{
if($1=="signal" || $1=="constant" )
if($1=="signal" || $1=="constant" )
{
list=""
class=$1
}
list= list " " $0 " "
list= list " " $0 " "
if($0 ~ /;/)
{
signals = list
sub(class,"",signals)
sub(/:.*$/,"",signals)
gsub(/[ \t,]+/, " ", signals)
sig_type=list
sub(/[ \t]*:=.*$/,"", sig_type)
sub(/^.*:[ \t]*/,"", sig_type)
sub(/[ \t]*;.*$/,"", sig_type)
if(list ~ /:=/)
{
value=list
@ -798,11 +798,11 @@ function add_inst_pin(pin_label)
value= "\"" value "\""
}
n_sig=split(signals,pin_label_array)
for(i=1;i<=n_sig;i++)
{
pin_label=pin_label_array[i] #toupper
#print "encountered signal\n"
s_type=sig_type
sub(/_vector.*/,"",s_type)
@ -821,9 +821,9 @@ function add_inst_pin(pin_label)
gsub(/[ \t]+/,"",index_low) #23122003 remove spaces in indexes
gsub(/[ \t]+/,"",index_high)
}
if(is_bus) pin_label=pin_label "[" index_high ":" index_low "]"
type="signal"
e_type_pin[e_n_pin]=s_type
e_class_pin[e_n_pin]=class
@ -834,23 +834,23 @@ function add_inst_pin(pin_label)
entity_full_name[basename(pin_label)]=pin_label
entity_pin_type[basename(pin_label)]=s_type
}
}
}
}
}
}
END{
for( i in entity_pin_type ) { print i " - " entity_pin_type[i] }
print "G {" code_lines "}" >entname
if(attribute !~/^[ \t]*$/) print "C {devices/attributes} 0 -200 0 0 {" attribute " }" >entname
if(port_attribute !~/^[ \t]*$/) print "C {devices/port_attributes} 0 -400 0 0 {" port_attribute " }" >entname
if(use !~/^[ \t]*$/) print "C {devices/use} 400 -400 0 0 {" use " }" >entname
@ -864,9 +864,9 @@ END{
function vhdl_to_cad(s)
{
sub(/[ \t]*\([ \t]*/,"[",s)
sub(/[ \t]+(to|downto)[ \t]+/,":",s)
sub(/[ \t]+(to|downto)[ \t]+/,":",s)
sub(/[ \t]*\)[ \t]*/,"]",s)
gsub(/[ \t]/,"",s)
if(s in entity_full_name) s=entity_full_name[s]
@ -903,7 +903,7 @@ function print_sch(schname,type_pin, dir_pin, value_pin, class_pin, num_pin, opi
y=0
x=-40
sch_x_offset=230
for(i=0;i<n_pin;i++)
{
dir=dir_pin[i]
@ -963,7 +963,7 @@ function print_sch(schname,type_pin, dir_pin, value_pin, class_pin, num_pin, opi
}
}
function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
value_pin,class_pin, num_pin, i_opin, i_ipin, n_pin, ip, op, # 20090407 ioin and opin renamed to i_ipin and i_opin
n,m,y,x,i,value, num,sig_type,dir) #local vars to avoid clash with component arrays
{
@ -977,11 +977,11 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
{
yoffset=prev_size=0
xoffset+=920
}
}
yoffset += ((prev_size+n)/2+1)*space
for(i=0;i<n_pin;i++)
{
dir=dir_pin[i]
@ -1018,7 +1018,7 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
# ypin=y+num*space+yoffset
# /20090407
}
if(dir=="generic")
{
pin_lower=basename(tolower(i_ipin[num]))
@ -1028,15 +1028,15 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
sig_type = entity_pin_type[pin_lower]
}
all_signals = all_signals "C {devices/lab_pin} " xpin " " ypin " 0 0" \
" {name=g" g_pin++ " type=" sig_type " lab=" i_ipin[num] " "
" {name=g" g_pin++ " type=" sig_type " lab=" i_ipin[num] " "
# if(value !="") all_signals = all_signals "value=" value "}\n"
# else all_signals = all_signals "}\n"
# if(value !="") all_signals = all_signals "value=" value "}\n"
# else all_signals = all_signals "}\n"
# bug fix: since generics assigned to instances are not declared elsewhere
# use the generic name also for the value property
all_signals = all_signals "value=" i_ipin[num] "}\n" # <<< 21042002
}
if(dir=="ipin")
{
pin_lower=basename(tolower(i_ipin[num]))
@ -1046,11 +1046,11 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
sig_type = entity_pin_type[pin_lower]
}
all_signals = all_signals "C {devices/lab_pin} " xpin " " ypin " 0 0 " \
" {name=p" p_pin++ " sig_type=" sig_type " lab=" i_ipin[num] " "
if(value !="") all_signals = all_signals "value=" value "}\n"
else all_signals = all_signals "}\n"
" {name=p" p_pin++ " sig_type=" sig_type " lab=" i_ipin[num] " "
if(value !="") all_signals = all_signals "value=" value "}\n"
else all_signals = all_signals "}\n"
}
if(dir=="opin")
{
pin_lower=basename(tolower(i_opin[num]))
@ -1060,11 +1060,11 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
sig_type = entity_pin_type[pin_lower]
}
all_signals = all_signals "C {devices/lab_pin} " xpin " " ypin " 0 1 " \
" {name=p" p_pin++ " sig_type=" sig_type " lab=" i_opin[num] " "
if(value !="") all_signals = all_signals "value=" value "}\n"
else all_signals = all_signals "}\n"
" {name=p" p_pin++ " sig_type=" sig_type " lab=" i_opin[num] " "
if(value !="") all_signals = all_signals "value=" value "}\n"
else all_signals = all_signals "}\n"
}
if(dir=="iopin")
{
pin_lower=basename(tolower(i_opin[num]))
@ -1074,9 +1074,9 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
sig_type = entity_pin_type[pin_lower]
}
all_signals = all_signals "C {devices/lab_pin} " xpin " " ypin " 0 1 " \
" {name=p" p_pin++ " sig_type=" sig_type " lab=" i_opin[num] " "
if(value !="") all_signals = all_signals "value=" value "}\n"
else all_signals = all_signals "}\n"
" {name=p" p_pin++ " sig_type=" sig_type " lab=" i_opin[num] " "
if(value !="") all_signals = all_signals "value=" value "}\n"
else all_signals = all_signals "}\n"
}
}
@ -1091,7 +1091,7 @@ function print_signals(inst_name, component_name, name_pin, type_pin, dir_pin,
prev_size=n
if( idx in cell_pin_x) prev_size+=8
}
}
function sign(x)
{

36
src/make_sym.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: make_sym.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -38,10 +38,10 @@ FNR == 1 {
_filename_ = FILENAME
beginfile(FILENAME)
}
END { endfile(_filename_) }
function beginfile(f)
{
sym=name=f
@ -57,8 +57,8 @@ function beginfile(f)
if(symline ~ /\} *$/) start=0
}
close(sym)
size=2.5
space=20
lwidth=20
@ -73,11 +73,11 @@ function beginfile(f)
printf "%s", "K {type=subcircuit\nformat=\"@name @pinlist @symname\"\n" >sym
printf "%s\n", "template=\"name=x1\"" >sym
printf "%s", "}\n" >sym
}
}
else print template >sym
print "T {@symname}" ,-length(name_ext)/2*titlesize*30, -text_voffset*titlesize,0,0,
titlesize, titlesize, "{}" >sym
}
@ -165,7 +165,7 @@ function process_line()
pin_label=""
value=""
generic_type=""
if($0 ~ /^.*lab=/)
{
pin_label=$0
@ -180,14 +180,14 @@ function process_line()
sub(/[}].*$/,"",verilog_type)
sub(/ $/,"",verilog_type)
}
if($0 ~ /^.*sig_type=/)
{
sig_type=$0
sub(/^.*sig_type=/,"",sig_type)
sub(/[ }].*$/,"",sig_type)
}
if($0 ~ /^.*generic_type=/)
{
generic_type=$0
@ -200,7 +200,7 @@ function process_line()
if($0 ~ /^.*value=/)
{
value=$0
if(value ~ /value="/)
if(value ~ /value="/)
{
sub(/^.*value="/,"",value)
value= "\"" substr(value,1, match(value, /[^\\]"/) ) "\""
@ -250,7 +250,7 @@ function endfile(f) {
for(ii=0;ii<n_pin;ii++)
{
i = index_pin[ii] # 20140519
dir=dir_pin[i]
value=value_pin[i]
@ -361,4 +361,4 @@ function comp(a,b)
return a<b
}

82
src/make_sym_from_spice.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: make_sym_from_spice.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -56,12 +56,12 @@ BEGIN{
########################## END JOIN ##########################
skip=0
for(i=0;i<netlist_lines; i++) {
for(i=0;i<netlist_lines; i++) {
$0=netlist[i]
process_subckts()
}
skip=0
for(i=0;i<netlist_lines; i++) {
for(i=0;i<netlist_lines; i++) {
$0=netlist[i]
process()
}
@ -70,7 +70,7 @@ BEGIN{
function process_subckts( j, i,name)
{
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
if(skip==1) return
if(toupper($1) ==".SUBCKT") {
curr_subckt=$2
@ -88,7 +88,7 @@ function process_subckts( j, i,name)
pin_ar[curr_subckt,"format"]=pin_ar[curr_subckt,"format"] " @@" $i
j++
} else {
if(pin_ar[curr_subckt,"extra"])
if(pin_ar[curr_subckt,"extra"])
pin_ar[curr_subckt,"extra"] = pin_ar[curr_subckt,"extra"] " " $i
else
pin_ar[curr_subckt,"extra"] = $i
@ -100,7 +100,7 @@ function process_subckts( j, i,name)
pin_ar[curr_subckt,"n"]=j-1
if(skip_symbol_prefix)
pin_ar[curr_subckt,"template"] = pin_ar[curr_subckt,"template"] " prefix=" skip_symbol_prefix
get_template(template)
get_template(template)
if(skip_symbol_prefix)
pin_ar[curr_subckt,"extra"] = pin_ar[curr_subckt,"extra"] " prefix"
}
@ -110,27 +110,27 @@ function process_subckts( j, i,name)
if($i ~ /:I$/ ) pin_ar[curr_subckt, "dir", name] = "I"
else if($i ~ /:O$/ ) pin_ar[curr_subckt, "dir", name] = "O"
else if($i ~ /:B$/ ) pin_ar[curr_subckt, "dir", name] = "B"
else { print "ERROR in .PININFO: ", $i " --> " $0 ; exit}
else { print "ERROR in .PININFO: ", $i " --> " $0 ; exit}
}
}
else if(toupper($1) ~ /^\*\.(I|O|IO)PIN/) {
if($1 ~ /^\*\.ipin/) { pin_ar[curr_subckt, "dir", $2] = "I" }
else if($1 ~ /^\*\.opin/) { pin_ar[curr_subckt, "dir", $2] = "O" }
else if($1 ~ /^\*\.iopin/) { pin_ar[curr_subckt, "dir", $2] = "B" }
if($1 ~ /^\*\.ipin/) { pin_ar[curr_subckt, "dir", $2] = "I" }
else if($1 ~ /^\*\.opin/) { pin_ar[curr_subckt, "dir", $2] = "O" }
else if($1 ~ /^\*\.iopin/) { pin_ar[curr_subckt, "dir", $2] = "B" }
}
}
function get_template(t, templ, i)
function get_template(t, templ, i)
{
templ=""
if(t) for(i=t;i<=NF;i++) {
templ = templ $i " "
templ = templ $i " "
}
pin_ar[curr_subckt,"template"] = pin_ar[curr_subckt,"template"] " " templ
}
function process( i,name,param)
{
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
@ -153,14 +153,14 @@ function process( i,name,param)
sp=ip=op=n_pin=0
all_signals=""
delete net_ar
subckt_netlist = "" # 20111009 all netlist lines except component instances (X)
subckt_netlist = "" # 20111009 all netlist lines except component instances (X)
}
else if(toupper($1) ~ /^.ENDS/) {
compact_pinlist( "" , curr_subckt)
print_sym(curr_subckt, pin_ar[curr_subckt,"template"], \
pin_ar[curr_subckt,"format"], pin_ar[curr_subckt,"name"], \
sym_type, pin_ar[curr_subckt,"extra"], dir_ret, pin_ret)
@ -181,7 +181,7 @@ function compact_pinlist(inst,inst_sub , prevgroup, group,i,ii,
delete pin_ret
delete net_ret
delete dir_ret
np=pin_ar[inst_sub,"n"]
# print " compact_pinlist: inst=" inst " np= " np " inst_sub=" inst_sub
if(np) {
@ -194,7 +194,7 @@ function compact_pinlist(inst,inst_sub , prevgroup, group,i,ii,
base =lab_name( pin_ar[inst_sub,i] )
if(i==1) {prevgroup=group; curr=base; curr_n=i}
else {
else {
if(prevgroup || base != curr) {
if(prevgroup) pin_ret[ii] = pin_ar[inst_sub,i-1]
else pin_ret[ii] = compact_label(inst_sub,pin_ar,curr_n,i-1)
@ -261,7 +261,7 @@ function compact_label_str(str, a, b, ar, ret,start,i)
}
else if( lab_index(ar[start])!=lab_index(ar[i]) && # range count != element count
abs(start-i)!=abs(lab_index(ar[start])-lab_index(ar[i]))) {
abs(start-i)!=abs(lab_index(ar[start])-lab_index(ar[i]))) {
if(start<i-1 && lab_index(ar[start]) == lab_index(ar[i-1]) )
ret = ret (i-start) "*" ar[i-1] ",";
else if(start<i-1)
@ -317,14 +317,14 @@ function compact_label(name, ar,a,b, ret,start,i)
else if(lab_name(ar[name,i])!=lab_name(ar[name,i-1])) {
if(start<i-1 && lab_index(ar[name,start]) == lab_index(ar[name,i-1]) )
ret = ret (i-start) "*" ar[name,i-1] ",";
else if(start<i-1)
else if(start<i-1)
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) ":" lab_index(ar[name,i-1]) "],"
else
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) "],"
start=i
}
else if(lab_index(ar[name,i]) != lab_index(ar[name,i-1])-1 &&
lab_index(ar[name,i]) != lab_index(ar[name,i-1])+1 ) {
lab_index(ar[name,i]) != lab_index(ar[name,i-1])+1 ) {
if(start<i-1 && lab_index(ar[name,start]) == lab_index(ar[name,i-1]) )
ret = ret (i-start) "*" ar[name,i-1] ",";
else if(start<i-1)
@ -349,9 +349,9 @@ function compact_label(name, ar,a,b, ret,start,i)
if(start < b) ret = ret (b-start+1) "*" ar[name,b]
else ret = ret ar[name,b]
}
else if(start<b && lab_index(ar[name,start]) == lab_index(ar[name,b]))
ret = ret (b-start+1) "*" ar[name,b]
else if(start<b)
else if(start<b && lab_index(ar[name,start]) == lab_index(ar[name,b]))
ret = ret (b-start+1) "*" ar[name,b]
else if(start<b)
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) ":" lab_index(ar[name,b]) "]"
else
ret = ret lab_name(ar[name,b]) "[" lab_index(ar[name,b]) "]"
@ -377,7 +377,7 @@ function lab_index(lab)
function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin,
size,space,width,lwidth,textdist,labsize,titlesize,
i,name,text_voffset,lab_voffset,ip,op,n_pin ,m,x,y,n,
iii,ooo)
iii,ooo)
{
size=2.5
space=20
@ -407,9 +407,9 @@ function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin
iii = format_translate(template, extra)
if(iii) iii = " " iii
# since awk strings use backslash escapes and sub also uses backslash escapes (example for \& substitution)
# since awk strings use backslash escapes and sub also uses backslash escapes (example for \& substitution)
# there are 2 levels of escape substitutions, we need \\\\ to generate one \.
# in the xschem file \\\\ is reduced to \\ in the format string and finally format contains one \
# in the xschem file \\\\ is reduced to \\ in the format string and finally format contains one \
if(skip_symbol_prefix) sub(skip_symbol_prefix, "@prefix\\\\\\\\\\\\\\\\", subckt_name)
print "format=\"@name" format " " subckt_name iii "\"" > sym
print "template=\"name=x1" template "\"" > sym
@ -418,16 +418,16 @@ function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin
# titlesize, titlesize, "{}" >sym
print "T {@symname}" ,0, -text_voffset*titlesize,0,0,
titlesize, titlesize, "{hcenter=true}" >sym
n_pin=pin["n"]
ip=op=0
ip=op=0
for(i=1; i<=n_pin; i++) {
if(dir[i] ~ /[OB]/) {
op++
}
op++
}
else if(dir[i] ~ /I/) ip++
else {print "ERROR: print_sym(): undefined dir[] i=" i " inst=" inst " sub=" component_name ; exit}
}
}
n=ip;if(op>n) n=op
if(n==0) n=1
@ -474,7 +474,7 @@ function print_sym(sym, template, format, subckt_name, sym_type, extra, dir, pin
}
close(sym)
}
#------------------------------
@ -485,12 +485,12 @@ function escape_brackets(s , ss)
return ss
}
function abs(a)
function abs(a)
{
return a>0 ? a: -a
}
function format_translate(s, extra, n_extra, extra_arr, extra_hash, c,quote,str,n,i,ss,sss)
function format_translate(s, extra, n_extra, extra_arr, extra_hash, c,quote,str,n,i,ss,sss)
{
# 20140321
@ -508,18 +508,18 @@ function format_translate(s, extra, n_extra, extra_arr, extra_hash, c
str=""
n_extra = split(extra, extra_arr)
for(i = 1; i <= n_extra; i++) extra_hash[ extra_arr[i] ] = 1
n=split(s,ss)
for(i=1;i<=n;i++) {
gsub(SUBSEP," ", ss[i])
if(ss[i] ~ /[^=]+=[^=]+/) {
split(ss[i],sss,"=")
split(ss[i],sss,"=")
if(!(sss[1] in extra_hash)) ss[i] = sss[1] "=@" sss[1]
else ss[i] = ""
}
str = str ss[i]
if(i<n && ss[i] ) str=str " "
if(i<n && ss[i] ) str=str " "
}
delete extra_hash
return str

64
src/make_vhdl_from_spice.awk
View File

@ -2,7 +2,7 @@
gawk '
BEGIN{
# ar["a", 1] = "A[3]"
# ar["a", 2] = "A[3]"
# ar["a", 3] = "A[3]"
@ -49,13 +49,13 @@ BEGIN{
########################## END JOIN ##########################
skip=0
for(i=0;i<netlist_lines; i++) {
for(i=0;i<netlist_lines; i++) {
$0=netlist[i]
process_subckts()
}
skip=0
for(i=0;i<netlist_lines; i++) {
for(i=0;i<netlist_lines; i++) {
$0=netlist[i]
process()
}
@ -66,7 +66,7 @@ BEGIN{
function process_subckts( i,name)
{
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
if(skip==1 && toupper($1) ==".ENDS") { skip=0; return }
if(skip==1) return
if(toupper($1) ==".SUBCKT") {
curr_subckt=$2
@ -79,8 +79,8 @@ function process_subckts( i,name)
pin_ar[curr_subckt,i-2]=$i
}
pin_ar[curr_subckt,"n"]=i-3
pin_ar[curr_subckt,"template"] = get_template(template)
print "\n\n\n process_subckt() : " curr_subckt "--> "
pin_ar[curr_subckt,"template"] = get_template(template)
print "\n\n\n process_subckt() : " curr_subckt "--> "
for(i=1; i<= pin_ar[curr_subckt,"n"]; i++) printf "%s ", pin_ar[curr_subckt,i]; printf "\n"
}
else if(toupper($1) ~ /^\*\.PININFO/) {
@ -89,27 +89,27 @@ function process_subckts( i,name)
if($i ~ /:I$/ ) pin_ar[curr_subckt, "dir", name] = "I"
else if($i ~ /:O$/ ) pin_ar[curr_subckt, "dir", name] = "O"
else if($i ~ /:B$/ ) pin_ar[curr_subckt, "dir", name] = "B"
else { print "ERROR" ; exit}
else { print "ERROR" ; exit}
}
}
else if(toupper($1) ~ /^\*\.(I|O|IO)PIN/) {
if($1 ~ /^\*\.ipin/) { pin_ar[curr_subckt, "dir", $2] = "I" }
else if($1 ~ /^\*\.opin/) { pin_ar[curr_subckt, "dir", $2] = "O" }
else if($1 ~ /^\*\.iopin/) { pin_ar[curr_subckt, "dir", $2] = "B" }
if($1 ~ /^\*\.ipin/) { pin_ar[curr_subckt, "dir", $2] = "I" }
else if($1 ~ /^\*\.opin/) { pin_ar[curr_subckt, "dir", $2] = "O" }
else if($1 ~ /^\*\.iopin/) { pin_ar[curr_subckt, "dir", $2] = "B" }
}
}
function get_template(t, templ, i)
function get_template(t, templ, i)
{
templ=""
if(t) for(i=t;i<=NF;i++) {
templ = templ $i " "
templ = templ $i " "
}
return templ
}
function process( i,name,param)
{
print "process(): skip = " skip " --> " $0
@ -128,12 +128,12 @@ function process( i,name,param)
compact_pinlist( "" , curr_subckt)
print "----------------------------------------------------------"
for(i=1;i<= dir_ret["n"] ; i++) {
print dir_ret[i] " " pin_ret[i]
}
}
print "\n\n"
print_sch(curr_subckt, dir_ret, pin_ret)
print "----------------------------------------------------------"
@ -178,7 +178,7 @@ function process( i,name,param)
print " dir_ret " i " ------> " dir_ret[i] " " pin_ret[i] " <-- " net_ret[i]
}
print "\n\n"
param = get_param(param)
param = get_param(param)
print_signals( inst, inst_sub, param, pin_ret, dir_ret, net_ret )
}
}
@ -197,7 +197,7 @@ function compact_pinlist(inst,inst_sub ,i,ii,base,curr,curr_n,n
delete pin_ret
delete net_ret
delete dir_ret
np=pin_ar[inst_sub,"n"]
print " compact_pinlist: np= " np
if(np) {
@ -205,7 +205,7 @@ function compact_pinlist(inst,inst_sub ,i,ii,base,curr,curr_n,n
for(i=1;i<=np;i++) {
base =lab_name( pin_ar[inst_sub,i] )
if(i==1) {curr=base; curr_n=i}
else {
else {
if(base != curr) {
pin_ret[ii] = compact_label(inst_sub,pin_ar,curr_n,i-1)
if(inst) net_ret[ii] = compact_label(inst,net_ar,curr_n,i-1)
@ -252,7 +252,7 @@ function compact_label(name, ar,a,b, ret,start,i)
lab_index(ar[name,i]) != lab_index(ar[name,start]) ) ) {
if(start<i-1 && lab_index(ar[name,start]) == lab_index(ar[name,i-1]) )
ret = ret (i-start) "*" ar[name,i-1] ",";
else if(start<i-1)
else if(start<i-1)
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) ":" lab_index(ar[name,i-1]) "],"
else
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) "],"
@ -264,9 +264,9 @@ function compact_label(name, ar,a,b, ret,start,i)
if(start < b) ret = ret (b-start+1) "*" ar[name,b]
else ret = ret ar[name,b]
}
else if(start<b && lab_index(ar[name,start]) == lab_index(ar[name,b]))
ret = ret (b-start+1) "*" ar[name,b]
else if(start<b)
else if(start<b && lab_index(ar[name,start]) == lab_index(ar[name,b]))
ret = ret (b-start+1) "*" ar[name,b]
else if(start<b)
ret = ret lab_name(ar[name,start]) "[" lab_index(ar[name,start]) ":" lab_index(ar[name,b]) "]"
else
ret = ret lab_name(ar[name,b]) "[" lab_index(ar[name,b]) "]"
@ -303,7 +303,7 @@ function print_sch(schname, dir, pin,
else if(dir[i]=="O" || dir[i]=="B") op++
else {print "ERROR: print_sch(): undefined dir[]"; exit}
}
for(i=1;i<=n_pin;i++)
{
pin_dir=dir[i]
@ -336,45 +336,45 @@ function print_signals( inst_name, component_name, param, pin,dir,net,
n_pin=pin["n"]
n_net=net["n"]
n_dir=dir["n"]
print " print_signals() : component_name = ", component_name
if(n_dir != n_pin) { print " n_dir vs n_pin mismatch: inst / comp = " inst_name " / " component_name ; exit }
if(n_net != n_pin) { print " n_net vs n_pin mismatch: inst / comp = " inst_name " / " component_name ; exit }
all_signals=all_signals inst_name " : " component_name "\nPORT MAP(\n"
all_signals=all_signals inst_name " : " component_name "\nPORT MAP(\n"
for(i=1;i<=n_net;i++)
{
curr_dir=dir[i]
all_signals = all_signals " " pin[i] " => " net[i]
all_signals = all_signals " " pin[i] " => " net[i]
if(i<n_net) all_signals = all_signals ",\n"
else all_signals = all_signals "\n"
}
all_signals=all_signals ");\n\n"
}
}
#------------------------------
function abs(a)
function abs(a)
{
return a>0 ? a: -a
}
function format_translate(s, str,n,i,ss,sss)
function format_translate(s, str,n,i,ss,sss)
{
str=""
n=split(s,ss)
for(i=1;i<=n;i++) {
if(ss[i] ~ /.+=.+/) {
split(ss[i],sss,"=")
split(ss[i],sss,"=")
ss[i] = sss[i] "=@" sss[1]
}
str = str ss[i]
if(i<n) str=str " "
if(i<n) str=str " "
}
return str
}

2
src/mouse_bindings.tcl
View File

@ -107,7 +107,7 @@ proc mouse_buttons { b m } {
}
}
# the global variable 'has_x' is provided by xschem. It is defined to '1'
# the global variable 'has_x' is provided by xschem. It is defined to '1'
# if graphics has been initialized.
if { [ info exists has_x ] } {

112
src/move.c
View File

@ -238,7 +238,7 @@ void draw_selection(GC g, int interruptable)
{
case xTEXT:
if(xctx->rotatelocal) {
ROTATION(xctx->move_rot, xctx->move_flip, xctx->text[n].x0, xctx->text[n].y0,
ROTATION(xctx->move_rot, xctx->move_flip, xctx->text[n].x0, xctx->text[n].y0,
xctx->text[n].x0, xctx->text[n].y0, xctx->rx1,xctx->ry1);
} else {
ROTATION(xctx->move_rot, xctx->move_flip, xctx->x1, xctx->y1,
@ -545,7 +545,7 @@ void update_attached_floaters(const char *from_name, int inst, int sel)
new_attach = str_replace(attach, from_name, to_name, 1, 1);
my_strdup(_ALLOC_ID_, &xctx->inst[inst].prop_ptr,
subst_token(xctx->inst[inst].prop_ptr, "attach", new_attach) );
for(c = 0; c < cadlayers; c++) {
for(i = 0; i < xctx->rects[c]; i++) {
if(!sel || xctx->rect[c][i].sel == SELECTED) {
@ -564,40 +564,40 @@ void update_attached_floaters(const char *from_name, int inst, int sel)
}
}
for(i = 0; i < xctx->lines[c]; i++) {
if((!sel || xctx->line[c][i].sel == SELECTED) &&
if((!sel || xctx->line[c][i].sel == SELECTED) &&
!strcmp(from_name, get_tok_value(xctx->line[c][i].prop_ptr, "name", 0))) {
my_strdup(_ALLOC_ID_, &xctx->line[c][i].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->line[c][i].prop_ptr,
subst_token(xctx->line[c][i].prop_ptr, "name", to_name) );
}
}
for(i = 0; i < xctx->polygons[c]; i++) {
if((!sel || xctx->poly[c][i].sel == SELECTED) &&
if((!sel || xctx->poly[c][i].sel == SELECTED) &&
!strcmp(from_name, get_tok_value(xctx->poly[c][i].prop_ptr, "name", 0))) {
my_strdup(_ALLOC_ID_, &xctx->poly[c][i].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->poly[c][i].prop_ptr,
subst_token(xctx->poly[c][i].prop_ptr, "name", to_name) );
}
}
for(i = 0; i < xctx->arcs[c]; i++) {
if((!sel || xctx->arc[c][i].sel == SELECTED) &&
if((!sel || xctx->arc[c][i].sel == SELECTED) &&
!strcmp(from_name, get_tok_value(xctx->arc[c][i].prop_ptr, "name", 0))) {
my_strdup(_ALLOC_ID_, &xctx->arc[c][i].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->arc[c][i].prop_ptr,
subst_token(xctx->arc[c][i].prop_ptr, "name", to_name) );
}
}
}
for(i = 0; i < xctx->wires; i++) {
if((!sel || xctx->wire[i].sel == SELECTED) &&
if((!sel || xctx->wire[i].sel == SELECTED) &&
!strcmp(from_name, get_tok_value(xctx->wire[i].prop_ptr, "name", 0))) {
my_strdup(_ALLOC_ID_, &xctx->wire[i].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->wire[i].prop_ptr,
subst_token(xctx->wire[i].prop_ptr, "name", to_name) );
}
}
for(i = 0; i < xctx->texts; i++) {
if((!sel || xctx->text[i].sel == SELECTED) &&
if((!sel || xctx->text[i].sel == SELECTED) &&
!strcmp(from_name, get_tok_value(xctx->text[i].prop_ptr, "name", 0))) {
my_strdup(_ALLOC_ID_, &xctx->text[i].prop_ptr,
my_strdup(_ALLOC_ID_, &xctx->text[i].prop_ptr,
subst_token(xctx->text[i].prop_ptr, "name", to_name) );
set_text_flags(&xctx->text[i]);
}
@ -612,11 +612,11 @@ void copy_objects(int what)
int newpropcnt;
double tmpx, tmpy;
char *estr = NULL;
#if HAS_CAIRO==1
int customfont;
#endif
if(what & START)
{
xctx->rotatelocal=0;
@ -684,7 +684,7 @@ void copy_objects(int what)
if(xctx->drag_elements && xctx->deltax==0 && xctx->deltay == 0) {
xctx->ui_state &= ~STARTCOPY;
return;
}
}
if( !xctx->kissing ) {
dbg(1, "copy_objects(): push undo state\n");
@ -736,11 +736,11 @@ void copy_objects(int what)
xctx->sel_array[i].n=xctx->wires;
storeobject(-1, xctx->rx1,xctx->ry1,xctx->rx2,xctx->ry2,WIRE,0,xctx->wire[n].sel,xctx->wire[n].prop_ptr);
xctx->wire[n].sel=0;
l = xctx->wires -1;
}
}
for(k=0;k<cadlayers; ++k)
{
for(i=0;i<xctx->lastsel; ++i)
@ -783,10 +783,10 @@ void copy_objects(int what)
storeobject(-1, xctx->rx1, xctx->ry1, xctx->rx2, xctx->ry2, LINE, c,
xctx->line[c][n].sel, xctx->line[c][n].prop_ptr);
xctx->line[c][n].sel=0;
l = xctx->lines[c] - 1;
break;
case POLYGON:
if(c!=k) break;
{
@ -840,13 +840,13 @@ void copy_objects(int what)
if(angle<0.) angle+=360.;
xctx->arc[c][n].sel=0;
xctx->sel_array[i].n=xctx->arcs[c];
store_arc(-1, xctx->rx1+xctx->deltax, xctx->ry1+xctx->deltay,
xctx->arc[c][n].r, angle, xctx->arc[c][n].b, c, SELECTED, xctx->arc[c][n].prop_ptr);
l = xctx->arcs[c] - 1;
break;
case xRECT:
if(c!=k) break;
if(xctx->rotatelocal) {
@ -869,7 +869,7 @@ void copy_objects(int what)
l = xctx->rects[c] - 1;
flip_rotate_ellipse(&xctx->rect[c][l], xctx->move_rot, xctx->move_flip);
break;
case xTEXT:
if(k!=TEXTLAYER) break;
check_text_storage();
@ -902,15 +902,15 @@ void copy_objects(int what)
set_text_flags(&xctx->text[xctx->texts]);
xctx->text[xctx->texts].xscale=xctx->text[n].xscale;
xctx->text[xctx->texts].yscale=xctx->text[n].yscale;
l = xctx->texts;
#if HAS_CAIRO==1 /* bbox after copy */
customfont = set_text_custom_font(&xctx->text[l]);
#endif
estr = my_expand(get_text_floater(l), tclgetintvar("tabstop"));
text_bbox(estr, xctx->text[l].xscale,
xctx->text[l].yscale, xctx->text[l].rot,xctx->text[l].flip,
xctx->text[l].yscale, xctx->text[l].rot,xctx->text[l].flip,
xctx->text[l].hcenter, xctx->text[l].vcenter,
xctx->text[l].x0, xctx->text[l].y0,
&xctx->rx1,&xctx->ry1, &xctx->rx2,&xctx->ry2, &tmpi, &dtmp);
@ -920,7 +920,7 @@ void copy_objects(int what)
cairo_restore(xctx->cairo_ctx);
}
#endif
xctx->sel_array[i].n=xctx->texts;
xctx->texts++;
dbg(2, "copy_objects(): done copy string\n");
@ -929,10 +929,10 @@ void copy_objects(int what)
break;
} /* end switch(xctx->sel_array[i].type) */
} /* end for(i=0;i<xctx->lastsel; ++i) */
} /* end for(k=0;k<cadlayers; ++k) */
for(i = 0; i < xctx->lastsel; ++i) {
n = xctx->sel_array[i].n;
if(xctx->sel_array[i].type == ELEMENT) {
@ -963,7 +963,7 @@ void copy_objects(int what)
xctx->inst[xctx->instances].y0 = xctx->ry1+xctx->deltay;
set_first_sel(ELEMENT, xctx->instances, 0);
xctx->inst[xctx->instances].sel = SELECTED;
xctx->inst[xctx->instances].rot = (xctx->inst[xctx->instances].rot + ( (xctx->move_flip &&
xctx->inst[xctx->instances].rot = (xctx->inst[xctx->instances].rot + ( (xctx->move_flip &&
(xctx->inst[xctx->instances].rot & 1) ) ? xctx->move_rot+2 : xctx->move_rot) ) & 0x3;
xctx->inst[xctx->instances].flip = (xctx->move_flip? !xctx->inst[n].flip:xctx->inst[n].flip);
my_strdup2(_ALLOC_ID_, &xctx->inst[xctx->instances].instname, xctx->inst[n].instname);
@ -1094,7 +1094,7 @@ static void place_moved_wire(int n, int orthogonal_wiring)
* |
* (V)|
* (H) selected |
* o-----------------------------------
* o-----------------------------------
* rx1,ry1(new)
*/
else if(wire[n].sel == SELECTED1 && (xctx->manhattan_lines & 2)) /* V - H */
@ -1160,7 +1160,7 @@ void move_objects(int what, int merge, double dx, double dy)
#endif
xLine ** const line = xctx->line;
xWire * const wire = xctx->wire;
dbg(1, "move_objects: what=%d, dx=%g, dy=%g\n", what, dx, dy);
if(what & START)
{
@ -1189,7 +1189,7 @@ void move_objects(int what, int merge, double dx, double dy)
pop_undo(0, 0);
if(xctx->connect_by_kissing == 2) xctx->connect_by_kissing = 0;
}
xctx->move_rot=xctx->move_flip=0;
xctx->deltax=xctx->deltay=0.;
xctx->ui_state &= ~STARTMOVE;
@ -1286,10 +1286,10 @@ void move_objects(int what, int merge, double dx, double dy)
}
place_moved_wire(n, orthogonal_wiring);
}
break;
case LINE:
if(c!=k) break;
if(xctx->rotatelocal) {
@ -1303,7 +1303,7 @@ void move_objects(int what, int merge, double dx, double dy)
ROTATION(xctx->move_rot, xctx->move_flip, xctx->x1, xctx->y1,
line[c][n].x2, line[c][n].y2, xctx->rx2,xctx->ry2);
}
if( line[c][n].sel & (SELECTED|SELECTED1) )
{
xctx->rx1+=xctx->deltax;
@ -1327,7 +1327,7 @@ void move_objects(int what, int merge, double dx, double dy)
line[c][n].x2=xctx->rx2;
line[c][n].y2=xctx->ry2;
break;
case POLYGON:
if(c!=k) break;
{
@ -1342,7 +1342,7 @@ void move_objects(int what, int merge, double dx, double dy)
if(j==0 || p->y[j] < by1) by1 = p->y[j];
if(j==0 || p->x[j] > bx2) bx2 = p->x[j];
if(j==0 || p->y[j] > by2) by2 = p->y[j];
if( p->sel==SELECTED || p->selected_point[j]) {
if(xctx->rotatelocal) {
ROTATION(xctx->move_rot, xctx->move_flip, savex0, savey0, p->x[j], p->y[j],
@ -1351,7 +1351,7 @@ void move_objects(int what, int merge, double dx, double dy)
ROTATION(xctx->move_rot, xctx->move_flip, xctx->x1, xctx->y1, p->x[j], p->y[j],
xctx->rx1,xctx->ry1);
}
p->x[j] = xctx->rx1+xctx->deltax;
p->y[j] = xctx->ry1+xctx->deltay;
}
@ -1364,7 +1364,7 @@ void move_objects(int what, int merge, double dx, double dy)
}
}
break;
case ARC:
if(c!=k) break;
if(xctx->rotatelocal) {
@ -1408,7 +1408,7 @@ void move_objects(int what, int merge, double dx, double dy)
}
break;
case xRECT:
if(c!=k) break;
/* bbox before move */
@ -1423,7 +1423,7 @@ void move_objects(int what, int merge, double dx, double dy)
ROTATION(xctx->move_rot, xctx->move_flip, xctx->x1, xctx->y1,
xctx->rect[c][n].x2, xctx->rect[c][n].y2, xctx->rx2,xctx->ry2);
}
flip_rotate_ellipse(&xctx->rect[c][n], xctx->move_rot, xctx->move_flip);
if( xctx->rect[c][n].sel == SELECTED) {
@ -1464,11 +1464,11 @@ void move_objects(int what, int merge, double dx, double dy)
{
xctx->rx2+=xctx->deltax;
}
tx1 = xctx->rx1;
ty1 = xctx->ry1;
RECTORDER(xctx->rx1,xctx->ry1,xctx->rx2,xctx->ry2);
if( xctx->rx2 == tx1) {
if(xctx->rect[c][n].sel==SELECTED1) xctx->rect[c][n].sel = SELECTED2;
else if(xctx->rect[c][n].sel==SELECTED2) xctx->rect[c][n].sel = SELECTED1;
@ -1481,15 +1481,15 @@ void move_objects(int what, int merge, double dx, double dy)
else if(xctx->rect[c][n].sel==SELECTED2) xctx->rect[c][n].sel = SELECTED4;
else if(xctx->rect[c][n].sel==SELECTED4) xctx->rect[c][n].sel = SELECTED2;
}
xctx->rect[c][n].x1 = xctx->rx1;
xctx->rect[c][n].y1 = xctx->ry1;
xctx->rect[c][n].x2 = xctx->rx2;
xctx->rect[c][n].y2 = xctx->ry2;
/* bbox after move */
break;
case xTEXT:
if(k!=TEXTLAYER) break;
#if HAS_CAIRO==1 /* bbox before move */
@ -1518,7 +1518,7 @@ void move_objects(int what, int merge, double dx, double dy)
xctx->text[n].rot=(xctx->text[n].rot +
( (xctx->move_flip && (xctx->text[n].rot & 1) ) ? xctx->move_rot+2 : xctx->move_rot) ) & 0x3;
xctx->text[n].flip=xctx->move_flip^xctx->text[n].flip;
#if HAS_CAIRO==1 /* bbox after move */
customfont = set_text_custom_font(&xctx->text[n]);
#endif
@ -1533,15 +1533,15 @@ void move_objects(int what, int merge, double dx, double dy)
cairo_restore(xctx->cairo_ctx);
}
#endif
break;
default:
break;
} /* end switch(xctx->sel_array[i].type) */
} /* end for(i=0;i<xctx->lastsel; ++i) */
} /*end for(k=0;k<cadlayers; ++k) */
for(i = 0; i < xctx->lastsel; ++i) {
n = xctx->sel_array[i].n;
if(xctx->sel_array[i].type == ELEMENT) {
@ -1562,7 +1562,7 @@ void move_objects(int what, int merge, double dx, double dy)
symbol_bbox(n,
&xctx->inst[n].x1, &xctx->inst[n].y1,
&xctx->inst[n].x2, &xctx->inst[n].y2);
}
}
}
if(!firsti || !firstw) {
xctx->prep_net_structs=0;
@ -1572,11 +1572,11 @@ void move_objects(int what, int merge, double dx, double dy)
check_collapsing_objects();
unselect_partial_sel_wires();
if(tclgetboolvar("autotrim_wires")) trim_wires();
if(xctx->hilight_nets) {
propagate_hilights(1, 1, XINSERT_NOREPLACE);
}
xctx->ui_state &= ~STARTMOVE;
if(xctx->ui_state & STARTMERGE) xctx->ui_state |= SELECTION; /* leave selection state so objects can be deleted */
xctx->ui_state &= ~STARTMERGE;

84
src/netlist.c
View File

@ -163,7 +163,7 @@ void del_object_table(void)
static void objectdelete(int type, int n, int c, int x, int y)
{
Objectentry *saveptr, **prevptr, *ptr;
prevptr = &xctx->object_spatial_table[x][y];
ptr = *prevptr;
while(ptr) {
@ -176,8 +176,8 @@ static void objectdelete(int type, int n, int c, int x, int y)
prevptr = &ptr->next;
ptr = *prevptr;
}
}
}
static void objectinsert(int type, int n, int c, int x, int y)
{
Objectentry *ptr, *newptr;
@ -301,7 +301,7 @@ void hash_objects(void) /* 20171203 insert object bbox in spatial hash table */
hash_object(XINSERT, xTEXT, n, 0);
}
for(c=0;c<cadlayers; ++c)
{
{
for(n=0; n<xctx->rects[c]; n++) {
hash_object(XINSERT, xRECT, n, c);
}
@ -563,10 +563,10 @@ void hash_wires(void)
}
/* return 0 if library path of s matches any lib name in tcl variable $xschem_libs */
/* what:
/* what:
* 1: netlist exclude pattern
* 2: hierarchical print exclude pattern
* 4: hierarchical cell listing exclude pattern
* 4: hierarchical cell listing exclude pattern
*/
int check_lib(int what, const char *s)
{
@ -630,7 +630,7 @@ void netlist_options(int i)
/* fprintf(errfp, "netlist_options(): prop_ptr=%s\n", xctx->inst[i].prop_ptr); */
if(!strboolcmp(str, "true")) tclsetintvar("top_is_subckt", 1);
else tclsetintvar("top_is_subckt", 0);
}
}
str = get_tok_value(xctx->inst[i].prop_ptr, "spiceprefix", 0);
if(str[0]) {
@ -701,7 +701,7 @@ static void print_wires(void)
* 4: add ground entry (it is also a global). for Spectre
* 2: delete list only, no print
* 3: look if node is a global
* return value:
* return value:
* 1: global
* 2: ground (and global)
*/
@ -903,7 +903,7 @@ static int signal_short( const char *tag, const char *n1, const char *n2)
/* if pin or label has missing lab=... attribute get and set from attached nets */
static void set_lab_or_pin_inst_attr(int i, int j, const char *node)
{
{
int port = 0;
char *dir=NULL;
@ -968,7 +968,7 @@ static void set_inst_node(int i, int j, const char *node)
set_lab_or_pin_inst_attr(i, j, node);
if(node[0] == '#') { /* update multilicity of unnamed node */
int pin_mult;
int pin_mult;
expandlabel(get_tok_value(rect[j].prop_ptr, "name", 0), &pin_mult);
get_unnamed_node(2, pin_mult * inst_mult, atoi((inst[i].node[j]) + 4));
}
@ -992,7 +992,7 @@ static int name_attached_inst_to_net(int k, int sqx, int sqy)
if(!inst[n].node) continue;
if(touch(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, x0, y0)) {
if(!inst[n].node[p]) {
dbg(1, "name_attached_inst_to_net(): inst %s, pin %d <-- %s\n",
dbg(1, "name_attached_inst_to_net(): inst %s, pin %d <-- %s\n",
inst[n].instname, p, wire[k].node ? wire[k].node : "<NULL>");
set_inst_node(n, p, wire[k].node);
err |= instcheck(n, p);
@ -1011,7 +1011,7 @@ static int wirecheck(int k) /* recursive routine */
double x1, y1, x2, y2;
Wireentry *wptr;
xWire * const wire = xctx->wire;
dbg(1, "wirecheck: %d\n", k);
x1 = wire[k].x1; y1 = wire[k].y1;
x2 = wire[k].x2; y2 = wire[k].y2;
@ -1038,8 +1038,8 @@ static int wirecheck(int k) /* recursive routine */
if(n == k) { /* itself */
err |= name_attached_inst_to_net(k, tmpi, tmpj);
continue;
}
touches =
}
touches =
touch(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, wire[n].x1, wire[n].y1) ||
touch(wire[k].x1, wire[k].y1, wire[k].x2, wire[k].y2, wire[n].x2, wire[n].y2) ||
touch(wire[n].x1, wire[n].y1, wire[n].x2, wire[n].y2, wire[k].x1, wire[k].y1) ||
@ -1122,7 +1122,7 @@ int shorted_instance(int i, int lvs_ignore)
if((inst[i].flags & SPECTRE_SHORT) || (sym[inst[i].ptr].flags & SPECTRE_SHORT) ) shorted = 1;
} else if(xctx->netlist_type == CAD_VHDL_NETLIST) {
if((inst[i].flags & VHDL_SHORT) || (sym[inst[i].ptr].flags & VHDL_SHORT) ) shorted = 1;
} else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
} else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
if((inst[i].flags & TEDAX_SHORT) || (sym[inst[i].ptr].flags & TEDAX_SHORT) ) shorted = 1;
return shorted;
@ -1159,8 +1159,8 @@ int skip_instance(int i, int skip_short, int lvs_ignore)
}
/* what:
* Determine if given "ninst" instance has pass-through pins
/* what:
* Determine if given "ninst" instance has pass-through pins
* 0: initialize
* 1: query
* 2: cleanup
@ -1203,8 +1203,8 @@ static int find_pass_through_symbols(int what, int ninst)
return -1;
}
/*
* Given an instance pin (inst n, pin p) propagate electrical information through
/*
* Given an instance pin (inst n, pin p) propagate electrical information through
* other pins with identical "name" attribute (pass-through symbols)
*/
static int instcheck(int n, int p)
@ -1222,30 +1222,30 @@ static int instcheck(int n, int p)
if(!inst[n].node) return 0;
if( xctx->netlist_type == CAD_VERILOG_NETLIST &&
((inst[n].flags & VERILOG_IGNORE) ||
((inst[n].flags & VERILOG_IGNORE) ||
(k >= 0 && (sym[k].flags & VERILOG_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_SPECTRE_NETLIST &&
((inst[n].flags & SPECTRE_IGNORE) ||
((inst[n].flags & SPECTRE_IGNORE) ||
(k >= 0 && (sym[k].flags & SPECTRE_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_SPICE_NETLIST &&
((inst[n].flags & SPICE_IGNORE) ||
((inst[n].flags & SPICE_IGNORE) ||
(k >= 0 && (sym[k].flags & SPICE_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_VHDL_NETLIST &&
((inst[n].flags & VHDL_IGNORE) ||
((inst[n].flags & VHDL_IGNORE) ||
(k >= 0 &&(sym[k].flags & VHDL_IGNORE))) ) return 0;
if( xctx->netlist_type == CAD_TEDAX_NETLIST &&
((inst[n].flags & TEDAX_IGNORE) ||
((inst[n].flags & TEDAX_IGNORE) ||
(k >= 0 && (sym[k].flags & TEDAX_IGNORE))) ) return 0;
if( netlist_lvs_ignore &&
((inst[n].flags & LVS_IGNORE_OPEN) ||
((inst[n].flags & LVS_IGNORE_OPEN) ||
(k >= 0 && (sym[k].flags & LVS_IGNORE_OPEN))) ) return 0;
/* process bus taps : type = bus_tap
/* process bus taps : type = bus_tap
* node 1 connects to bus (DATA[15:0]) , node 0 is the tap ([2:0]) */
if(rects > 1 && bus_tap && p == 1) {
char *node_base_name = NULL;
@ -1362,7 +1362,7 @@ static int name_nodes_of_pins_labels_and_propagate()
) {
char str[2048];
if( type && /* list of devices that do not have a name= in template attribute */
strcmp(type, "package") &&
strcmp(type, "package") &&
strcmp(type, "port_attributes") &&
strcmp(type, "architecture") &&
strcmp(type, "arch_declarations") &&
@ -1434,11 +1434,11 @@ static int name_nodes_of_pins_labels_and_propagate()
record_global_node(1,NULL, inst[i].node[0]);
}
}
/* do not count multiple labels/pins with same name */
bus_node_hash_lookup(inst[i].node[0], /* insert node in hash table */
dir, XINSERT, port, sig_type, verilog_type, value, class);
get_inst_pin_coord(i, 0, &x0, &y0);
get_square(x0, y0, &sqx, &sqy);
/* name nets that touch ioin opin alias instances */
@ -1506,13 +1506,13 @@ static int set_unnamed_inst(int i, int j)
}
static int name_unlabeled_instances()
{
{
int err = 0;
int i, j;
xInstance * const inst = xctx->inst;
int const instances = xctx->instances;
int rects;
dbg(2, "name_unlabeled_instances(): naming nets that dont touch labels\n");
for (i = 0; i < instances; ++i)
{
@ -1529,7 +1529,7 @@ static int name_unlabeled_instances()
}
}
return err;
}
}
static int reset_node_data_and_rehash()
{
@ -1564,7 +1564,7 @@ void show_unconnected_pins(void)
{
int i;
for(i = 0; i < xctx->instances; ++i)
{
{
select_element(i, SELECTED, 1, 0);
}
rebuild_selected_array();
@ -1586,7 +1586,7 @@ int prepare_netlist_structs(int for_netl)
for_netlist = for_netl;
if(for_netlist>0 && xctx->prep_net_structs) return 0;
else if(!for_netlist && xctx->prep_hi_structs) return 0;
dbg(1, "prepare_netlist_structs(): extraction: %s\n", xctx->sch[xctx->currsch]);
reset_caches(); /* update cached flags: necessary if some tcleval() is used for cached attrs */
@ -1726,7 +1726,7 @@ int sym_vs_sch_pins(int all)
{
if( xctx->sym[i].type && !strcmp(xctx->sym[i].type,"subcircuit")) {
int rects = xctx->sym[i].rects[PINLAYER];
/* Determine if symbol has pass-through pins (pins with identical name)
/* Determine if symbol has pass-through pins (pins with identical name)
* if any is found do not check with schematic */
Int_hashtable pin_table = {NULL, 0};
int p;
@ -1752,7 +1752,7 @@ int sym_vs_sch_pins(int all)
switch(tag[0]) {
case 'v':
load_ascii_string(&tmp, fd);
my_snprintf(f_version, S(f_version), "%s",
my_snprintf(f_version, S(f_version), "%s",
get_tok_value(tmp, "file_version", 0));
break;
@ -1842,7 +1842,7 @@ int sym_vs_sch_pins(int all)
* arguments. This can not be done in this context (the current schematic we are looking
* into is not loaded), so skip test */
if( strchr(name, '@')) {
dbg(1, "sym_vs_sch_pins(): symbol reference %s skipped (need to translate() tokens)\n",
dbg(1, "sym_vs_sch_pins(): symbol reference %s skipped (need to translate() tokens)\n",
name);
break;
}
@ -1860,7 +1860,7 @@ int sym_vs_sch_pins(int all)
pin_cnt++;
pin_match = 0;
for(j=0; j < rects; ++j) {
my_strdup(_ALLOC_ID_, &pin_name,
my_strdup(_ALLOC_ID_, &pin_name,
expandlabel(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr, "name", 0), &mult));
my_strdup(_ALLOC_ID_, &pin_dir, get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr, "dir", 0));

16
src/ngspice_backannotate.tcl
View File

@ -1,21 +1,21 @@
#
# File: ngspice_backannotate.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -28,7 +28,7 @@ proc ngspice::read_raw_dataset {arr fp} {
set variables 0
while {[gets $fp line] >= 0} {
if {$line eq "Binary:"} break
if {[regexp {^No\. Variables:} $line]} {
set n_vars [lindex $line end]
}
@ -75,7 +75,7 @@ proc ngspice::read_raw {{f {}}} {
}
set fp [open $rawfile r]
fconfigure $fp -translation binary
set ngspice::op_point_read 0
set ngspice::op_point_read 0
## not needed: done in ngspice::read_ngspice_raw
# array unset ngspice::ngspice_data
while 1 {
@ -87,7 +87,7 @@ proc ngspice::read_raw {{f {}}} {
} else break;
}
close $fp
puts {Raw file read ...}
puts {Raw file read ...}
if { !$ngspice::op_point_read } {
puts "no operating point found!"
}

8
src/node_hash.c
View File

@ -198,7 +198,7 @@ int traverse_node_hash()
Node_hashentry *entry;
char str[2048]; /* 20161122 overflow safe */
int incr_hi;
incr_hi = tclgetboolvar("incr_hilight");
for(i=0;i<HASHSIZE; ++i)
{
@ -261,7 +261,7 @@ void print_vhdl_signals(FILE *fd)
int i, found;
int mult,j;
char *class=NULL;
found=0;
for(i=0;i<HASHSIZE; ++i) {
ptr = xctx->node_table[i];
@ -324,7 +324,7 @@ void print_verilog_signals(FILE *fd)
Node_hashentry *ptr;
int i, found;
int mult,j;
dbg(2, " print_verilog_signals(): entering routine\n");
found=0;
for(i=0;i<HASHSIZE; ++i) {
@ -401,7 +401,7 @@ void list_nets(char **result)
ptr = xctx->node_table[i];
while(ptr) {
if(!ptr->d.port) {
my_mstrcat(_ALLOC_ID_, result,
my_mstrcat(_ALLOC_ID_, result,
"{", ptr->token, " ", "net", "}\n", NULL);
}
ptr = ptr->next;

30
src/order_labels.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: order_labels.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -28,10 +28,10 @@ BEGIN{
NF=2 {
i++
pin[i]=$1
# 20111116
dir[$1] = $2
}
}
END{
pin["n"]=i
hsort(pin, pin["n"])
@ -50,14 +50,14 @@ function compact_pinlist(pin ,i,ii,base,curr,curr_n,np)
{
delete pin_ret
delete dir_ret
np=pin["n"]
if(np) {
ii=1
for(i=1;i<=np;i++) {
base =lab_name( pin[i] )
if(i==1) {curr=base; curr_n=i}
else {
else {
if(base != curr) {
pin_ret[ii] = compact_label(pin,curr_n,i-1)
dir_ret[ii] = dir[pin[i-1]] # 20111116
@ -69,7 +69,7 @@ function compact_pinlist(pin ,i,ii,base,curr,curr_n,np)
pin_ret[ii] = compact_label(pin,curr_n,np)
dir_ret[ii] = dir[pin[np]] # 20111116
pin_ret["n"] = ii
}
}
@ -87,10 +87,10 @@ function compact_label(ar,a,b, ret,start,i)
else {ret = ret ar[i-1] ","; start=i }
}
}
else if(lab_name(ar[i])!=lab_name(ar[i-1]) ||
( lab_index(ar[i]) != lab_index(ar[i-1])-1 &&
else if(lab_name(ar[i])!=lab_name(ar[i-1]) ||
( lab_index(ar[i]) != lab_index(ar[i-1])-1 &&
lab_index(ar[i]) != lab_index(ar[i-1])+1) ) {
if(start<i-1)
if(start<i-1)
ret = ret lab_name(ar[start]) "[" lab_index(ar[start]) ":" lab_index(ar[i-1]) "],"
else
ret = ret lab_name(ar[start]) "[" lab_index(ar[start]) "],"
@ -102,7 +102,7 @@ function compact_label(ar,a,b, ret,start,i)
if(start < b) ret = ret (b-start+1) "*" ar[b]
else ret = ret ar[b]
}
else if(start<b)
else if(start<b)
ret = ret lab_name(ar[start]) "[" lab_index(ar[start]) ":" lab_index(ar[b]) "]"
else
ret = ret lab_name(ar[b]) "[" lab_index(ar[b]) "]"
@ -162,7 +162,7 @@ function hsort(array,n, rarray,l,j,ir,i,rra)
}
array[i]=rarray
}
}
}
function comp(a,b)
{

10
src/parse_synopsys_vhdl.awk
View File

@ -4,7 +4,7 @@ awk '
{ $0 = tolower($0)}
/port map\(/{
/port map\(/{
while($0 !~/; *$/) {
a=$0
getline
@ -12,7 +12,7 @@ awk '
}
gsub(/ */," ",$0)
gsub(/ *;/,";",$0)
# print ">>>>" $0 "<<<<"
# print ">>>>" $0 "<<<<"
}
@ -36,9 +36,9 @@ awk '
}
(port_list==1){
if($0 ~ /\) *;/)
{
sub(/\) *;/,"",$0)
if($0 ~ /\) *;/)
{
sub(/\) *;/,"",$0)
end_port_list=1
}
gsub(/;/, ";\n ",$0 )

14
src/parselabel.l
View File

@ -1,7 +1,7 @@
/* File: parselabel.l
*
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
@ -36,7 +36,7 @@
static int parselabel_debug = 0;
#include "xschem.h"
/*
/*
extern int xctx;
extern int has_x;
extern FILE *errfp;
@ -77,8 +77,8 @@ static void str_char_replace(char s[], char chr, char repl_chr)
if(s[i]==chr)
{
s[i]=repl_chr;
}
i++;
}
i++;
}
}
@ -121,14 +121,14 @@ const char *expandlabel(const char *s, int *m)
l = strlen(s)+400;
cmd = my_malloc(_ALLOC_ID_, l);
fprintf(errfp, "syntax error in %s\n", s);
my_snprintf(cmd, l,
my_snprintf(cmd, l,
"tk_messageBox -icon error -type ok -parent [xschem get topwindow] "
"-message {Syntax error in identifier expansion: %s\nschematic:\n%s}", s, xctx->sch[xctx->currsch]);
if(has_x) tcleval(cmd);
my_free(_ALLOC_ID_, &cmd);
}
if(parselabel_debug >= 3)
if(parselabel_debug >= 3)
fprintf(errfp, "expandlabel(): returning %s from %s mult=%d\n",dest_string.str, s, dest_string.m);
if(dest_string.str) {
*m = dest_string.m;

2
src/paste.c
View File

@ -315,7 +315,7 @@ static void merge_inst(int k,FILE *fd)
/* merge selection if selection_load=1, otherwise ask for filename
* selection_load:
* 0: ask filename to merge
* if ext=="" else use ext as name
* if ext=="" else use ext as name
* 1: merge selection
* 2: merge clipboard
* if bit 3 is set do not start a move_objects(RUBBER,0,0,0)

4
src/place_pins.tcl
View File

@ -9,10 +9,10 @@
#
# place pin symbols (like ipin.sym, opin.sym, iopin.sym,
# or devices/ipin.sym depending on your search path setting) in current schematic.
# Pins are placed at growing y coordinates (going down in xschem coordinate system)
# Pins are placed at growing y coordinates (going down in xschem coordinate system)
# parameters:
# filename: name for the file holding the list of pins.
# 2 columns are assumed: pin name and pin number
# 2 columns are assumed: pin name and pin number
# symname: name of the pin to place (ipin.sym, opin.sym, devices/ipin.sym, ...).
# x, y: coordinate for first pin
# spacing: vertical spacing between one pin and the following.

4
src/place_sym_pins.tcl
View File

@ -7,10 +7,10 @@
# LDPRECH 6
#
# place pin objects (squares on layer 5) and labels in the current symbol window.
# pins are placed at growing y coordinates (going down in xschem coordinate system)
# pins are placed at growing y coordinates (going down in xschem coordinate system)
# parameters:
# filename: name for the file holding the list of pins.
# 2 columns are assumed: pin name and pin number
# 2 columns are assumed: pin name and pin number
# dir: pin direction (in, out or inout)
# x, y: coordinate for first pin
# spacing: vertical spacing between one pin and the following.

90
src/psprint.c
View File

@ -99,7 +99,7 @@ static int ps_embedded_image(xRect* r, double x1, double y1, double x2, double y
/* screen position */
sx1=X_TO_SCREEN(x1);
sy1=Y_TO_SCREEN(y1);
sy1=Y_TO_SCREEN(y1);
sx2=X_TO_SCREEN(x2);
sy2=Y_TO_SCREEN(y2);
if(RECT_OUTSIDE(sx1, sy1, sx2, sy2,
@ -125,7 +125,7 @@ static int ps_embedded_image(xRect* r, double x1, double y1, double x2, double y
if(filter) {
jpg = 2; /* svg */
}
}
}
else jpg = -1; /* some invalid data */
} else {
jpg = -1;
@ -194,16 +194,16 @@ static int ps_embedded_image(xRect* r, double x1, double y1, double x2, double y
fprintf(fd, "{ << /ImageType 1\n");
fprintf(fd, " /Width %g\n", (double)size_x);
fprintf(fd, " /Height %g\n", (double)size_y);
if(!flip)
{
if(rot==1) fprintf(fd, " /ImageMatrix [%g 0 0 %g 0 %g]\n",
(double)size_y, (double)size_x, (double)size_y);
else if(rot==2) fprintf(fd, " /ImageMatrix [%g 0 0 %g %g %g]\n",
(double)size_x, (double)size_y, (double)size_x, (double)size_y);
else if(rot==3) fprintf(fd, " /ImageMatrix [%g 0 0 %g %g 0]\n",
else if(rot==3) fprintf(fd, " /ImageMatrix [%g 0 0 %g %g 0]\n",
(double)size_y, (double)size_x, (double)size_x);
else fprintf(fd, " /ImageMatrix [%g 0 0 %g 0 0]\n", (double)size_x, (double)size_y);
else fprintf(fd, " /ImageMatrix [%g 0 0 %g 0 0]\n", (double)size_x, (double)size_y);
}
else
{
@ -214,7 +214,7 @@ static int ps_embedded_image(xRect* r, double x1, double y1, double x2, double y
else if(rot==3) fprintf(fd, " /ImageMatrix [%g 0 0 %g 0 0]\n",
-(double)size_y, (double)size_x);
else fprintf(fd, " /ImageMatrix [%g 0 0 %g %g 0]\n",
-(double)size_x, (double)size_y, (double)size_x);
-(double)size_x, (double)size_y, (double)size_x);
}
fprintf(fd, " /DataSource Data\n");
fprintf(fd, " /BitsPerComponent 8\n");
@ -240,7 +240,7 @@ static int ps_embedded_image(xRect* r, double x1, double y1, double x2, double y
fprintf(fd, "%s", ascii85EncodedJpeg);
#endif
fprintf(fd, "~>\n");
fprintf(fd, "grestore\n");
my_free(_ALLOC_ID_, &ascii85EncodedJpeg);
free(jpgData);
@ -262,7 +262,7 @@ static int ps_embedded_graph(int i, double rx1, double ry1, double rx2, double r
int d_c;
unsigned char* jpgData = NULL;
size_t fileSize = 0;
/*
/*
* FILE* fp;
* static char str[PATH_MAX];
*/
@ -340,7 +340,7 @@ static int ps_embedded_graph(int i, double rx1, double ry1, double rx2, double r
cairo_set_source_surface(ct, xctx->cairo_save_sfc, 0, 0);
cairo_set_operator(ct, CAIRO_OPERATOR_SOURCE);
cairo_paint(ct);
setup_graph_data(i, 0, &xctx->graph_struct);
setup_graph_data(i, 0, &xctx->graph_struct);
draw_graph(i, 8 + (xctx->graph_flags & (4 | 2 | 128 | 256)), &xctx->graph_struct, (void *)ct);
#endif
cairo_image_surface_write_to_jpeg_mem(png_sfc, &jpgData, &fileSize, quality);
@ -384,7 +384,7 @@ static int ps_embedded_graph(int i, double rx1, double ry1, double rx2, double r
for (j = 0; j < oLength; ++j)
{
fputc(ascii85EncodedJpeg[j],fd);
if(j > 0 && (j % 64) == 0)
if(j > 0 && (j % 64) == 0)
{
fputc('\n',fd);
/* if (ascii85Encode[i+1]=='%') idx=63; imageMagic does this for some reason?!
@ -395,11 +395,11 @@ static int ps_embedded_graph(int i, double rx1, double ry1, double rx2, double r
fprintf(fd, "%s", ascii85EncodedJpeg);
#endif
fprintf(fd, "~>\n");
fprintf(fd, "grestore\n");
my_free(_ALLOC_ID_, &ascii85EncodedJpeg);
#endif
return 1;
}
@ -447,7 +447,7 @@ static void ps_xdrawpoint(int layer, double x1, double y1)
* 1 : stippled fill
* 2 : solid fill
*
* fill_type[i]:
* fill_type[i]:
* 0 : no fill
* 1 : patterned (stippled) fill
* 2 : solid fill
@ -597,9 +597,9 @@ static void ps_filledrect(int gc, double rectx1,double recty1,double rectx2,doub
if(bus > 0.0) {
fprintf(fd, "0 setlinejoin 2 setlinecap\n");
}
if(dash) {
if(dash) {
fprintf(fd, "[%g %g] 0 setdash\n", psdash, psdash);
}
}
if(width >= 0.0) set_lw(1.2 * width);
if(e_a != -1) {
@ -619,11 +619,11 @@ static void ps_filledrect(int gc, double rectx1,double recty1,double rectx2,doub
}
if(dash) {
fprintf(fd, "[] 0 setdash\n");
}
}
if(width >= 0.0) set_lw(xctx->lw);
if(bus > 0.0) {
fprintf(fd, "1 setlinejoin 1 setlinecap\n");
}
}
}
}
@ -679,7 +679,7 @@ static void ps_drawline(int gc, double linex1,double liney1,double linex2,double
double x1,y1,x2,y2;
double psdash;
double width;
if(bus == -1.0) width = BUS_WIDTH * xctx->lw;
else if(bus > 0.0) width = bus * xctx->mooz;
else width = -1.0;
@ -694,7 +694,7 @@ static void ps_drawline(int gc, double linex1,double liney1,double linex2,double
psdash = dash / xctx->zoom;
if(bus > 0.0) {
fprintf(fd, "0 setlinejoin 2 setlinecap\n");
}
}
if(dash) {
fprintf(fd, "[%g %g] 0 setdash\n", psdash, psdash);
}
@ -712,8 +712,8 @@ static void ps_drawline(int gc, double linex1,double liney1,double linex2,double
static void ps_draw_string_line(int layer, char *s, double x, double y, double size,
short rot, short flip, int lineno, double fontheight, double fontascent,
static void ps_draw_string_line(int layer, char *s, double x, double y, double size,
short rot, short flip, int lineno, double fontheight, double fontascent,
double fontdescent, int llength, int no_of_lines, double longest_line)
{
double ix, iy;
@ -807,7 +807,7 @@ static void ps_draw_string(int layer, const char *str, short rot, short flip, in
estr = my_expand(str, tclgetintvar("tabstop"));
text_bbox(estr, xscale, yscale, rot, flip, hcenter, vcenter,
x,y, &textx1,&texty1,&textx2,&texty2, &no_of_lines, &longest_line);
if(!textclip(xctx->areax1,xctx->areay1,xctx->areax2,
xctx->areay2,textx1,texty1,textx2,texty2)) {
my_free(_ALLOC_ID_, &estr);
@ -840,7 +840,7 @@ static void ps_draw_string(int layer, const char *str, short rot, short flip, in
c=*ss;
if(c=='\n' || c==0) {
*ss='\0';
ps_draw_string_line(layer, tt, x, y, size, rot, flip, lineno,
ps_draw_string_line(layer, tt, x, y, size, rot, flip, lineno,
height, ascent, descent, llength, no_of_lines, longest_line);
++lineno;
if(c==0) break;
@ -952,7 +952,7 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
{ /* a "for(i=0;i<cadlayers; ++i)" loop */
int j, hide = 0, disabled = 0;
double x0,y0,x1,y1,x2,y2;
short flip;
short flip;
int textlayer;
xLine *line;
xRect *rect;
@ -968,7 +968,7 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
type = xctx->sym[xctx->inst[n].ptr].type;
lvs_ignore=tclgetboolvar("lvs_ignore");
if(xctx->inst[n].ptr == -1) return;
if(layer == 0) {
if(layer == 0) {
xctx->inst[n].flags &= ~IGNORE_INST; /* clear bit */
if( type && strcmp(type, "launcher") && strcmp(type, "logo") &&
strcmp(type, "probe") &&
@ -1040,12 +1040,12 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
ps_filledrect(color, xctx->inst[n].xx1, xctx->inst[n].yy1, xctx->inst[n].xx2, xctx->inst[n].yy2,
0.0, 2, 0, -1, -1);
}
/* pdfmarks, only if doing hierarchy print and if symbol has a subcircuit */
/* pdfmarks, only if doing hierarchy print and if symbol has a subcircuit */
if(what != 7) {
char fname[PATH_MAX];
if(!strcmp(xctx->sym[xctx->inst[n].ptr].type, "subcircuit")) {
get_sch_from_sym(fname, xctx->inst[n].ptr+ xctx->sym, n, 0);
fprintf(fd,
fprintf(fd,
"[ "
"/Rect [ %g %g %g %g ] "
"/Border [0 0 0] "
@ -1132,7 +1132,7 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
if(symptr->rects[layer]) {
fprintf(fd, "NP\n"); /* newpath */
set_ps_colors(c);
}
}
for(j=0;j< symptr->rects[layer]; ++j)
{
@ -1148,7 +1148,7 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
} else {
int ellipse_a = rect->ellipse_a;
int ellipse_b = rect->ellipse_b;
if(ellipse_a != -1 && ellipse_b != 360) {
if(flip) {
ellipse_a = 180 - ellipse_a - ellipse_b;
@ -1163,12 +1163,12 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
}
ellipse_a %= 360;
}
}
}
ps_filledrect(c, x0+x1, y0+y1, x0+x2, y0+y2, rect->bus, dash, rect->fill, ellipse_a, ellipse_b);
}
}
} /* if( (!hide && xctx->enable_layer[layer]) || ... */
draw_texts:
if(xctx->sym_txt && !(xctx->inst[n].flags & HIDE_SYMBOL_TEXTS) && (layer == cadlayers)) {
const char *txtptr;
@ -1178,7 +1178,7 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
for(j=0;j< (xctx->inst[n].ptr+ xctx->sym)->texts; ++j)
{
double xscale, yscale;
get_sym_text_size(n, j, &xscale, &yscale);
text = symptr->text[j];
/* if(xscale*FONTWIDTH* xctx->mooz<1) continue; */
@ -1208,7 +1208,7 @@ static void ps_draw_symbol(int c, int n,int layer, int what, short tmp_flip, sho
my_snprintf(ps_font_family, S(ps_font_family), textfont);
my_snprintf(ps_font_name, S(ps_font_name), textfont);
}
if( symptr->text[j].flags & TEXT_BOLD) {
if( symptr->text[j].flags & TEXT_BOLD) {
if( (symptr->text[j].flags & TEXT_ITALIC) || (symptr->text[j].flags & TEXT_OBLIQUE) ) {
my_snprintf(ps_font_family, S(ps_font_family), "%s-BoldOblique", ps_font_name);
} else {
@ -1334,7 +1334,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
/* this zoom only done to reset lw */
zoom_full(0, 0, 1 + 2 * tclgetboolvar("zoom_full_center"), 0.97);
/* adjust aspect ratio to paper size */
if(landscape)
if(landscape)
xctx->xrect[0].height = (short unsigned int) (xctx->xrect[0].width * pagey / pagex);
else
xctx->xrect[0].width = (short unsigned int) (xctx->xrect[0].height * pagey / pagex);
@ -1380,7 +1380,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
}
margin = 0.0;
}
if(what & 1) {/* prolog */
dbg(1, "ps_draw(): bbox: x1=%g y1=%g x2=%g y2=%g\n", boundbox.x1, boundbox.y1, boundbox.x2, boundbox.y2);
if(!eps) {
@ -1409,14 +1409,14 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
fprintf(fd, "%%%%Page 1 1\n");
}
fprintf(fd, "%%%%BeginProlog\n\n");
for(i = 0; i < sizeof(utf8_enc)/sizeof(char *); ++i) {
fprintf(fd, "%s", utf8_enc[i]);
}
for(i = 0; i < sizeof(utf8)/sizeof(char *); ++i) {
fprintf(fd, "%s", utf8[i]);
}
fprintf(fd, "/Times /Times chararr recode\n");
fprintf(fd, "/Times-Bold /Times-Bold chararr recode\n");
fprintf(fd, "/Times-Oblique /Times-Oblique chararr recode\n");
@ -1429,7 +1429,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
fprintf(fd, "/Courier-Bold /Courier-Bold chararr recode\n");
fprintf(fd, "/Courier-Oblique /Courier-Oblique chararr recode\n");
fprintf(fd, "/Courier-BoldOblique /Courier-BoldOblique chararr recode\n");
fprintf(fd,"/cm {28.346457 mul} bind def\n");
fprintf(fd,"/LT {lineto} bind def\n");
fprintf(fd,"/MT {moveto} bind def\n");
@ -1492,7 +1492,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
scale = (pagex - 2 * margin) / dx;
dbg(1, "scale=%g\n", scale);
}
fprintf(fd, "%g %g translate\n",
fprintf(fd, "%g %g translate\n",
-scale * boundbox.x1 + margin, pagey - (scaley - scale) * dy - margin + scale * boundbox.y1);
fprintf(fd, "%g %g scale\n", scale, -scale);
fprintf(fd, "1 setlinejoin 1 setlinecap\n");
@ -1511,7 +1511,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
if(xctx->rects[c]) fprintf(fd, "NP\n"); /* newpath */
for(i=0;i<xctx->rects[c]; ++i)
{
if (c == GRIDLAYER && (xctx->rect[c][i].flags & 1024)) { /* image */
xRect* r = &xctx->rect[c][i];
/* PNG Code Here */
@ -1532,7 +1532,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
if(xctx->arcs[c]) fprintf(fd, "NP\n"); /* newpath */
for(i=0;i<xctx->arcs[c]; ++i)
{
ps_drawarc(c, xctx->arc[c][i].fill, xctx->arc[c][i].x, xctx->arc[c][i].y,
ps_drawarc(c, xctx->arc[c][i].fill, xctx->arc[c][i].x, xctx->arc[c][i].y,
xctx->arc[c][i].r, xctx->arc[c][i].a, xctx->arc[c][i].b, xctx->arc[c][i].bus, xctx->arc[c][i].dash);
}
for(i=0;i<xctx->polygons[c]; ++i) {
@ -1563,7 +1563,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
ps_drawline(color, xctx->wire[i].x1,xctx->wire[i].y1,xctx->wire[i].x2,xctx->wire[i].y2,
0 ,xctx->wire[i].bus);
}
{
double x1, y1, x2, y2;
Wireentry *wireptr;
@ -1596,7 +1596,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
textlayer = xctx->text[i].layer;
if(!xctx->show_hidden_texts && (xctx->text[i].flags & HIDE_TEXT)) continue;
if(textlayer < 0 || textlayer >= cadlayers) textlayer = TEXTLAYER;
my_snprintf(ps_font_family, S(ps_font_name), "Helvetica");
my_snprintf(ps_font_name, S(ps_font_name), "Helvetica");
textfont = xctx->text[i].font;
@ -1604,7 +1604,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
my_snprintf(ps_font_family, S(ps_font_family), textfont);
my_snprintf(ps_font_name, S(ps_font_name), textfont);
}
if( xctx->text[i].flags & TEXT_BOLD) {
if( xctx->text[i].flags & TEXT_BOLD) {
if( (xctx->text[i].flags & TEXT_ITALIC) || (xctx->text[i].flags & TEXT_OBLIQUE) ) {
my_snprintf(ps_font_family, S(ps_font_family), "%s-BoldOblique", ps_font_name);
} else {
@ -1615,7 +1615,7 @@ void create_ps(char **psfile, int what, int fullzoom, int eps)
my_snprintf(ps_font_family, S(ps_font_family), "%s-Oblique", ps_font_name);
else if( xctx->text[i].flags & TEXT_OBLIQUE)
my_snprintf(ps_font_family, S(ps_font_family), "%s-Oblique", ps_font_name);
if(text_ps) {
ps_draw_string(textlayer, get_text_floater(i),
xctx->text[i].rot, xctx->text[i].flip, xctx->text[i].hcenter, xctx->text[i].vcenter,

8
src/reduce_even_odd_array_labels.awk
View File

@ -30,7 +30,7 @@ END { endfile(_filename_) }
}
# T {nDisturbL[31],nDisturbL[29],nDi..... } 125 1686 0 1 0.2 0.2 {}
# T {nDisturbL[31],nDisturbL[29],nDi..... } 125 1686 0 1 0.2 0.2 {}
# B 5 147.5 -1672.5 152.5 -1667.5 {name=ARBLEQALF[30],ARBLEQALF[28],...,ARBLEQALF[0] dir=inout }
@ -73,7 +73,7 @@ function translate()
sub(/.*\[/,"",idx)
sub(/\]/,"",idx)
idx+=0
if(ii>1 && ( (idx+2!=previdx) || (basename !=first_basename) ) ) {
evenbus=0
break
@ -91,7 +91,7 @@ function translate()
{
__a[__lines++] = $0
__a[__lines++] = $0
}
function beginfile(f)
@ -110,5 +110,5 @@ function endfile(f, i)
}
close(f)
}
}
}

18
src/resources.tcl
View File

@ -1,21 +1,21 @@
#
# File: resources.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -41,14 +41,14 @@
## # so we set white background and eliminate alpha channel (unsupported in gif).
## convert -background white -alpha remove -alpha off paste.png -transparent white gif:-|base64
##
## Following shell function (and call) converts a png base64 encoded to proper
## Following shell function (and call) converts a png base64 encoded to proper
## gif89a base64 encoded format:
## to_gif () {
## echo "image create photo $1 -data \""
## echo -n "$2" | base64 -d |convert -background white -alpha remove -alpha off - -transparent white gif:- |base64
## echo '"'
## }
##
##
## to_gif imgFileOpen "...."
##
@ -69,7 +69,7 @@
# # set light colorscheme, set transparent svg background
# # draw image inside the border in green color
# # set line with 40 disable change line width, redraw
# # move away the border, full zoom the image
# # move away the border, full zoom the image
# # export svg:
# xschem print svg 1.svg 400 400 0 0 100 100
# # edit svg, change .l4 layer from green to black (#000000)
@ -77,7 +77,7 @@
# gm convert -size 16x16 1.svg 1.png
# convert -background white -alpha remove -alpha off 1.png -transparent white 1.gif
# base64 1.gif
# # the output is the 16x16 image with transparent background, antialiasing
# # the output is the 16x16 image with transparent background, antialiasing
# # and base64 encoded
# #
# #

238
src/save.c
View File

@ -84,13 +84,13 @@ int filter_data(const char *din, const size_t ilen,
dbg(1, "p2[0] = %d\n", p2[0]);
dbg(1, "p2[1] = %d\n", p2[1]);
signal(SIGPIPE, SIG_IGN); /* so attempting write/read a broken pipe won't kill program */
/*
/*
* p2
* ------------------- p2[0] <--------- p2[1] -------------------
* | Parent program | | Child filter |
* ------------------- p1[1] ---------> p1[0] -------------------
* ------------------- p2[0] <--------- p2[1] -------------------
* | Parent program | | Child filter |
* ------------------- p1[1] ---------> p1[0] -------------------
* p1
*/
fflush(NULL); /* flush all stdio streams before process forking */
@ -130,7 +130,7 @@ int filter_data(const char *din, const size_t ilen,
fprintf(stderr, "error: conversion failed\n");
ret = 1;
}
_exit(ret); /* childs should always use _exit() to avoid
_exit(ret); /* childs should always use _exit() to avoid
* flushing open stdio streams and other unwanted side effects */
}
/* parent */
@ -213,7 +213,7 @@ char *base64_encode(const unsigned char *data, const size_t input_length, size_t
encoded_data = my_malloc(_ALLOC_ID_, alloc_length);
if (encoded_data == NULL) return NULL;
cnt = 0;
for (i = 0, j = 0; i < input_length;) {
octet_a = i < input_length ? (unsigned char)data[i++] : 0;
octet_b = i < input_length ? (unsigned char)data[i++] : 0;
@ -263,7 +263,7 @@ unsigned char *base64_decode(const char *data, const size_t input_length, size_t
unsigned char *decoded_data;
int i, j, sextet[4], triple, cnt, padding;
size_t actual_length;
actual_length = input_length;
*output_length = input_length / 4 * 3 + 4; /* add 4 more just in case... */
padding = 0;
@ -309,7 +309,7 @@ unsigned char *ascii85_encode(const unsigned char *data, const size_t input_leng
'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
'q', 'r', 's', 't', 'u'
};
int padding = (4-(input_length % 4))%4;
static unsigned int pow85[] = {1, 85, 7225, 614125, 52200625};
unsigned char *paddedData = my_calloc(_ALLOC_ID_, input_length+padding, 1);
@ -399,9 +399,9 @@ static void skip_raw_ascii_points(int npoints, FILE *fd)
dbg(1, "found empty line --> break\n");
break;
}
}
}
}
}
}
static int read_raw_ascii_point(int ac, double *tmp, FILE *fd)
{
@ -463,8 +463,8 @@ static int read_raw_ascii_point(int ac, double *tmp, FILE *fd)
/* SPICE RAWFILE ROUTINES */
/* read the ascii / binary portion of a ngspice raw simulation file
* data layout in memory arranged to maximize cache locality
* when looking up data
* data layout in memory arranged to maximize cache locality
* when looking up data
*/
static void read_raw_data_block(int binary, FILE *fd, Raw *raw, int ac)
{
@ -475,7 +475,7 @@ static void read_raw_data_block(int binary, FILE *fd, Raw *raw, int ac)
long filepos;
#else
__int3264 filepos;
#endif
#endif
int npoints;
int rawvars = raw->nvars;
@ -547,17 +547,17 @@ static void read_raw_data_block(int binary, FILE *fd, Raw *raw, int ac)
else /* magnitude */
/* avoid 0 for dB calculations */
if(tmp[vv] == 0.0 && tmp[vv + 1] == 0.0) raw->values[v][offset + p] = 1e-35f;
else raw->values[v][offset + p] =
else raw->values[v][offset + p] =
(SPICE_DATA)sqrt(tmp[vv] * tmp[vv] + tmp[vv + 1] * tmp[vv + 1]);
/* AC analysis: calculate phase */
if(tmp[vv] == 0.0 && tmp[vv + 1] == 0.0) raw->values[v + 1] [offset + p] = 0.0;
if(tmp[vv] == 0.0 && tmp[vv + 1] == 0.0) raw->values[v + 1] [offset + p] = 0.0;
else raw->values[v + 1] [offset + p] =
(SPICE_DATA)(atan2(tmp[vv + 1], tmp[vv]) * 180.0 / XSCH_PI);
raw->values[v + 2] [offset + p] = (SPICE_DATA)tmp[vv]; /* real part */
raw->values[v + 3] [offset + p] = (SPICE_DATA)tmp[vv + 1]; /* imaginary part */
}
}
}
else for(v = 0; v < raw->nvars; v++) {
raw->values[v][offset + p] = (SPICE_DATA)tmp[v];
}
@ -591,7 +591,7 @@ static void read_raw_data_block(int binary, FILE *fd, Raw *raw, int ac)
* Binary:
*/
static int read_dataset(FILE *fd, Raw **rawptr, const char *type, int no_warning)
{
{
int variables = 0, i, done_points = 0;
char *line = NULL, *varname = NULL, *lowerline = NULL;
int n = 0, done_header = 0, ac = 0;
@ -599,7 +599,7 @@ static int read_dataset(FILE *fd, Raw **rawptr, const char *type, int no_warning
int dbglev=1;
const char *sim_type = NULL;
Raw *raw;
if(!rawptr) {
dbg(0, "read_dataset(): NULL rawptr given\n");
return 0;
@ -624,7 +624,7 @@ static int read_dataset(FILE *fd, Raw **rawptr, const char *type, int no_warning
my_strdup(_ALLOC_ID_, &raw->sim_type, sim_type);
done_header = 1;
dbg(dbglev, "read_dataset(): read binary block, nvars=%d npoints=%d\n", nvars, npoints);
read_raw_data_block(0, fd, raw, ac);
read_raw_data_block(0, fd, raw, ac);
raw->datasets++;
exit_status = 1;
} else {
@ -635,7 +635,7 @@ static int read_dataset(FILE *fd, Raw **rawptr, const char *type, int no_warning
sim_type = NULL; /* ready for next header */
done_points = 0;
ac = 0;
}
}
/* after this line comes the binary blob made of nvars * npoints * sizeof(double) bytes */
else if(!strcmp(line, "Binary:\n") || !strcmp(line, "Binary:\r\n")) {
@ -643,10 +643,10 @@ static int read_dataset(FILE *fd, Raw **rawptr, const char *type, int no_warning
my_strdup(_ALLOC_ID_, &raw->sim_type, sim_type);
done_header = 1;
dbg(dbglev, "read_dataset(): read binary block, nvars=%d npoints=%d\n", nvars, npoints);
read_raw_data_block(1, fd, raw, ac);
read_raw_data_block(1, fd, raw, ac);
raw->datasets++;
exit_status = 1;
} else {
} else {
dbg(dbglev, "read_dataset(): skip binary block, nvars=%d npoints=%d\n", nvars, npoints);
xfseek(fd, nvars * npoints * sizeof(double), SEEK_CUR); /* skip binary block */
}
@ -678,7 +678,7 @@ static int read_dataset(FILE *fd, Raw **rawptr, const char *type, int no_warning
if(!type) type = "op";
if(!strcmp(type, "op")) sim_type = "op";
dbg(dbglev, "read_dataset(): op sim_type=%s\n", sim_type ? sim_type : "<NULL>");
}
}
else if(!strncmp(line, "Plotname:", 9) && strstr(lowerline, "integrated noise")) {
if(!type) type = "op";
else if(!strcmp(type, "noise")) {
@ -891,7 +891,7 @@ void free_rawfile(Raw **rawptr, int dr, int no_warning)
if(has_x) {
tclvareval("set tctx::", xctx->current_win_path, "_waves $simulate_bg", NULL);
tclvareval("catch {", xctx->top_path, ".menubar entryconfigure Waves -background $simulate_bg}", NULL);
}
}
if(dr) draw();
}
@ -1035,7 +1035,7 @@ int raw_read(const char *f, Raw **rawptr, const char *type, int no_warning, doub
raw->allpoints += raw->npoints[i];
}
dbg(0, "Raw file data read: %s\n", f);
dbg(0, "points=%d, vars=%d, datasets=%d sim_type=%s\n",
dbg(0, "points=%d, vars=%d, datasets=%d sim_type=%s\n",
raw->allpoints, raw->nvars, raw->datasets, raw->sim_type ? raw->sim_type : "<NULL>");
if(xctx->graph_flags & 4) { /* if cursor2 is enabled in first graph setup schematic annotation */
@ -1075,11 +1075,11 @@ int raw_read(const char *f, Raw **rawptr, const char *type, int no_warning, doub
}
int raw_renamevar(const char *old_name, const char *new_name)
{
{
int n, ret = 0;
Raw *raw = xctx->raw;
Raw *raw = xctx->raw;
Int_hashentry *entry;
n = get_raw_index(old_name, &entry);
if(n < 0) return ret;
dbg(1, "n=%d, %s \n", n, entry->token);
@ -1087,14 +1087,14 @@ int raw_renamevar(const char *old_name, const char *new_name)
my_strdup2(_ALLOC_ID_, &raw->names[n], new_name);
int_hash_lookup(&raw->table, raw->names[n], n, XINSERT); /* update hash table */
ret = 1;
return ret;
}
return ret;
}
int raw_deletevar(const char *name)
{
int ret = 0;
int i, n;
Raw *raw = xctx->raw;
Raw *raw = xctx->raw;
Int_hashentry *entry;
n = get_raw_index(name, &entry);
@ -1145,12 +1145,12 @@ int new_rawfile(const char *name, const char *type, const char *sweepvar,
xctx->raw = my_calloc(_ALLOC_ID_, 1, sizeof(Raw));
raw = xctx->raw;
raw->level = -1;
raw->level = -1;
raw->sweep1 = -1.0;
raw->sweep2 = -1.0;
raw->annot_p = -1;
raw->annot_sweep_idx = -1;
int_hash_init(&raw->table, HASHSIZE);
my_strdup2(_ALLOC_ID_, &raw->rawfile, name);
my_strdup2(_ALLOC_ID_, &raw->schname, xctx->sch[xctx->currsch]);
@ -1181,7 +1181,7 @@ int new_rawfile(const char *name, const char *type, const char *sweepvar,
} else { /* file found: switch to it */
dbg(1, "new_rawfile() %d read: found: switch to it\n", i);
xctx->extra_prev_idx = xctx->extra_idx;
xctx->extra_idx = i;
xctx->extra_idx = i;
xctx->raw = xctx->extra_raw_arr[xctx->extra_idx];
ret = 0;
}
@ -1194,7 +1194,7 @@ int new_rawfile(const char *name, const char *type, const char *sweepvar,
/* what == 0: do nothing and return 0
* what == 1: read another raw file and switch to it (make it the current one)
* if type == table use table_read() to read an ascii table
* what == 2: switch raw file. If filename given switch to that one,
* what == 2: switch raw file. If filename given switch to that one,
* else if filename is an integer switch to that raw file index,
* else switch to next
* what == 3: remove a raw file. If no filename given remove all
@ -1229,11 +1229,11 @@ int extra_rawfile(int what, const char *file, const char *type, double sweep1, d
dbg(1, "extra_rawfile: table_read: f=%s\n", f);
for(i = 0; i < xctx->extra_raw_n; i++) {
if( !strcmp(xctx->extra_raw_arr[i]->rawfile, f)) break;
}
}
if(i >= xctx->extra_raw_n) { /* file not already loaded: read it and switch to it */
int read_ret = 0;
Raw *save;
save = xctx->raw;
save = xctx->raw;
xctx->raw = NULL;
read_ret = table_read(f);
if(read_ret) {
@ -1255,7 +1255,7 @@ int extra_rawfile(int what, const char *file, const char *type, double sweep1, d
} else { /* file found: switch to it */
dbg(1, "extra_rawfile() %d read: found: switch to it\n", i);
xctx->extra_prev_idx = xctx->extra_idx;
xctx->extra_idx = i;
xctx->extra_idx = i;
xctx->raw = xctx->extra_raw_arr[xctx->extra_idx];
}
/* **************** read ************* */
@ -1267,7 +1267,7 @@ int extra_rawfile(int what, const char *file, const char *type, double sweep1, d
else if(!my_strcasecmp(type, "sp")) type = "ac";
}
for(i = 0; i < xctx->extra_raw_n; i++) {
if(xctx->extra_raw_arr[i]->sim_type &&
if(xctx->extra_raw_arr[i]->sim_type &&
!strcmp(xctx->extra_raw_arr[i]->rawfile, f) &&
(!type || !strcmp(xctx->extra_raw_arr[i]->sim_type, type) )
) break;
@ -1328,7 +1328,7 @@ int extra_rawfile(int what, const char *file, const char *type, double sweep1, d
i = atoi(file);
if(i >= 0 && i < xctx->extra_raw_n) { /* if file found switch to it ... */
dbg(1, "extra_rawfile() switch %d: found: switch %d to it\n", xctx->extra_idx, i);
xctx->extra_prev_idx = xctx->extra_idx;
xctx->extra_prev_idx = xctx->extra_idx;
xctx->extra_idx = i;
} else {
if(!no_warning) {
@ -1429,7 +1429,7 @@ int extra_rawfile(int what, const char *file, const char *type, double sweep1, d
dbg(1, "extra_raw_n = %d\n", xctx->extra_raw_n);
Tcl_AppendResult(interp, my_itoa(xctx->extra_idx), " current\n", NULL);
for(i = 0; i < xctx->extra_raw_n; i++) {
Tcl_AppendResult(interp, my_itoa(i), " ", xctx->extra_raw_arr[i]->rawfile, " ",
Tcl_AppendResult(interp, my_itoa(i), " ", xctx->extra_raw_arr[i]->rawfile, " ",
xctx->extra_raw_arr[i]->sim_type ? xctx->extra_raw_arr[i]->sim_type : "<NULL>", "\n", NULL);
}
}
@ -1456,7 +1456,7 @@ int update_op()
}
Tcl_SetVar2(interp, "ngspice::ngspice_data", "n\\ vars", my_itoa( xctx->raw->nvars), TCL_GLOBAL_ONLY);
Tcl_SetVar2(interp, "ngspice::ngspice_data", "n\\ points", "1", TCL_GLOBAL_ONLY);
}
}
return res;
}
@ -1504,7 +1504,7 @@ int table_read(const char *f)
xctx->raw = my_calloc(_ALLOC_ID_, 1, sizeof(Raw));
raw = xctx->raw;
raw->level = -1;
raw->level = -1;
raw->annot_p = -1;
raw->annot_sweep_idx = -1;
@ -1688,8 +1688,8 @@ int get_raw_index(const char *node, Int_hashentry **entry_ret)
return -1;
}
/* store calculated custom graph data for later retrieval as in running average calculations
* what:
/* store calculated custom graph data for later retrieval as in running average calculations
* what:
* 0: clear data
* 1: store value
* 2: retrieve value
@ -1700,7 +1700,7 @@ static double ravg_store(int what , int i, int p, int last, double value)
static double **arr = NULL;
int j;
/*
/*
dbg(0, "ravg_store: what= %d i= %d p= %d last= %d value=%g\n",
what, i, p, last, value);
*/
@ -2022,7 +2022,7 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr, c
stack1[i].prev = result;
}
ravg_store(1, i, p, last, result);
while(stack1[i].prevp <= last && x[p] - x[stack1[i].prevp] > stack2[stackptr2 - 1]) {
/* dbg(1, "%g --> %g\n", x[stack1[i].prevp], x[p]); */
stack1[i].prevp++;
@ -2071,7 +2071,7 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr, c
stack1[i].prev = stack2[stackptr2 - 1];
} else {
if((x[p] != x[first])) {
avg = stack1[i].prev * (x[p - 1] - x[first]) +
avg = stack1[i].prev * (x[p - 1] - x[first]) +
(x[p] - x[p - 1]) * (stack1[i].prevy + stack2[stackptr2 - 1]) * 0.5;
avg /= (x[p] - x[first]);
} else {
@ -2086,7 +2086,7 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr, c
stack2[stackptr2] = stack2[stackptr2 - 1];
stackptr2++;
break;
case INTEG:
case INTEG:
if( p == first ) {
result = 0;
stack1[i].prevy = stack2[stackptr2 - 1];
@ -2098,13 +2098,13 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr, c
}
stack2[stackptr2 - 1] = result;
break;
case DERIV:
case DERIV:
if( p == first ) {
result = 0;
stack1[i].prevy = stack2[stackptr2 - 1];
stack1[i].prev = 0;
} else {
if((x[p] != x[p - 1]))
if((x[p] != x[p - 1]))
result = (stack2[stackptr2 - 1] - stack1[i].prevy) / (x[p] - x[p - 1]);
else
result = stack1[i].prev;
@ -2150,7 +2150,7 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr, c
double fa = stack1[i].prevprevy;
double fb = stack1[i].prevy;
double fc = stack2[stackptr2 - 1];
if(a != 0.0)
if(a != 0.0)
result = (fa - b_on_d * fb - (1 - b_on_d) * fc ) / (a - c * b_on_d);
else
result = stack1[i].prev;
@ -2273,8 +2273,8 @@ int plot_raw_custom_data(int sweep_idx, int first, int last, const char *expr, c
stack2[stackptr2 - 1] = 20 * mylog10(stack2[stackptr2 - 1]);
break;
case SGN:
stack2[stackptr2 - 1] = stack2[stackptr2 - 1] > 0.0 ? 1 :
stack2[stackptr2 - 1] < 0.0 ? -1 : 0;
stack2[stackptr2 - 1] = stack2[stackptr2 - 1] > 0.0 ? 1 :
stack2[stackptr2 - 1] < 0.0 ? -1 : 0;
break;
} /* switch(...) */
} /* if(stackptr2 > 0) */
@ -2289,7 +2289,7 @@ double get_raw_value(int dataset, int idx, int point)
{
int i, ofs;
ofs = 0;
if(dataset >= xctx->raw->datasets) {
if(dataset >= xctx->raw->datasets) {
dbg(0, "get_raw_value(): dataset(%d) >= datasets(%d)\n", dataset, xctx->raw->datasets);
}
if(xctx->raw && xctx->raw->values && dataset < xctx->raw->datasets) {
@ -2841,7 +2841,7 @@ static void load_inst(int k, FILE *fd)
#ifdef __unix__
if(name[0] == '/') my_strdup2(_ALLOC_ID_, &xctx->inst[i].name, rel_sym_path(name));
else my_strdup2(_ALLOC_ID_, &xctx->inst[i].name, name);
#else
#else
if(isupper(name[0]) && name[1] == ':' && name[1] == '/') my_strdup2(_ALLOC_ID_, &xctx->inst[i].name, rel_sym_path(name));
else my_strdup2(_ALLOC_ID_, &xctx->inst[i].name, name);
#endif
@ -3096,10 +3096,10 @@ static void read_xschem_file(FILE *fd)
if((ptr2 = strstr(xctx->version_string, "xschem")) && (ptr2 - xctx->version_string < 50)) {
my_strdup2(_ALLOC_ID_, &ptr, subst_token(xctx->version_string, "xschem", NULL));
}
}
my_strdup2(_ALLOC_ID_, &ptr, subst_token(ptr, "version", NULL));
my_strdup2(_ALLOC_ID_, &ptr, subst_token(ptr, "file_version", NULL));
ptr2 = ptr;
while(*ptr2 == ' ' || *ptr2 =='\t') ptr2++; /* strip leading spaces */
if(*ptr2 == '\n') ptr2++; /* strip leading newline */
@ -3186,7 +3186,7 @@ static void read_xschem_file(FILE *fd)
str = read_line(fd, 1);
if(!str || !strncmp(str, "]", 1)) break;
n = fscanf(fd, " ");
(void)n; /* avoid compiler warnings if n unused. can not remove n since ignoring
(void)n; /* avoid compiler warnings if n unused. can not remove n since ignoring
* fscanf return value yields another warning */
}
}
@ -3312,7 +3312,7 @@ static int pin_compare(const void *a, const void *b)
int result;
xRect *aa = (xRect *)a;
xRect *bb = (xRect *)b;
tmp = get_tok_value(aa->prop_ptr, "sim_pinnumber", 0);
pinnumber_a = tmp[0] ? atoi(tmp) : -1;
tmp = get_tok_value(bb->prop_ptr, "sim_pinnumber", 0);
@ -3358,7 +3358,7 @@ static void sort_symbol_pins(xRect *pin_array, int npins, const char *name)
/* Caller must free returned pointer (if not NULL)
* number of i/o ports found returned into npins */
Sch_pin_record *sort_schematic_pins(int *npins)
{
{
int i, do_sort = -1;
const char *pinnumber;
Sch_pin_record *pinnumber_list = NULL;
@ -3396,9 +3396,9 @@ Sch_pin_record *sort_schematic_pins(int *npins)
}
if(do_sort) {
qsort(pinnumber_list, *npins, sizeof(Sch_pin_record), schpin_compare);
}
}
return pinnumber_list;
}
}
/* ALWAYS call with absolute path in schname!!! */
/* return value:
@ -3455,7 +3455,7 @@ int save_schematic(const char *schname, int fast) /* 20171020 added return value
my_snprintf(msg, S(msg), "get_directory {%s}", schname);
my_strncpy(xctx->current_dirname, tcleval(msg), S(xctx->current_dirname));
/* why clear all these? */
/*
/*
* xctx->prep_hi_structs=0;
* xctx->prep_net_structs=0;
* xctx->prep_hash_inst=0;
@ -3502,7 +3502,7 @@ void link_symbols_to_instances(int from)
}
else xctx->inst[i].flags &= ~PIN_OR_LABEL; /* ordinary symbol */
}
/* symbol_bbox() might call translate() that might call prepare_netlist_structs() that
/* symbol_bbox() might call translate() that might call prepare_netlist_structs() that
* needs .lab field set above, so this must be done last */
for(i = from; i < xctx->instances; ++i) {
symbol_bbox(i, &xctx->inst[i].x1, &xctx->inst[i].y1, &xctx->inst[i].x2, &xctx->inst[i].y2);
@ -3520,7 +3520,7 @@ int load_schematic(int load_symbols, const char *fname, int reset_undo, int aler
char msg[PATH_MAX+100];
struct stat buf;
int i, ret = 1; /* success */
xctx->prep_hi_structs=0;
xctx->prep_net_structs=0;
xctx->prep_hash_inst=0;
@ -3562,10 +3562,10 @@ int load_schematic(int load_symbols, const char *fname, int reset_undo, int aler
my_snprintf(sympath, S(sympath), "%s", xschem_web_dirname);
/* ffname does not begin with $XSCHEM_TMP_DIR/xschem_web and ffname does not exist */
if(strstr(ffname, sympath) != ffname /* && stat(ffname, &buf)*/) {
if(strstr(ffname, sympath) != ffname /* && stat(ffname, &buf)*/) {
my_snprintf(msg, S(msg), "get_directory {%s}", ffname);
my_strncpy(xctx->current_dirname, tcleval(msg), S(xctx->current_dirname));
}
}
/* local file name */
my_strdup2(_ALLOC_ID_, &xctx->sch[xctx->currsch], ffname);
/* local relative reference */
@ -3764,7 +3764,7 @@ void push_undo(void)
/* the following 2 statements are a replacement for dup2() which is not c89
* however these are not atomic, if another thread takes stdin
* in between we are in trouble */
#if(HAS_DUP2)
#if(HAS_DUP2)
dup2(pd[0], 0);
#else
close(0); /* close stdin */
@ -3801,7 +3801,7 @@ void push_undo(void)
}
/* redo:
* 0: undo (with push current state for allowing following redo)
* 0: undo (with push current state for allowing following redo)
* 4: undo, do not push state for redo
* 1: redo
* 2: read top data from undo stack without changing undo stack
@ -3921,7 +3921,7 @@ void pop_undo(int redo, int set_modify_status)
* return symbol type in type pointer or "" if no type or no symbol found
* if pintable given (!=NULL) hash all symbol pins
* if embed_fd is not NULL read symbol from embedded '[...]' tags using embed_fd file pointer */
void get_sym_type(const char *symname, char **type,
void get_sym_type(const char *symname, char **type,
Int_hashtable *pintable, FILE *embed_fd, int *sym_n_pins)
{
int i, c, n = 0;
@ -3953,7 +3953,7 @@ void get_sym_type(const char *symname, char **type,
if( !found ) {
dbg(1, "get_sym_type(): open file %s, pintable %s\n",name, pintable ? "set" : "<NULL>");
/* ... if not found open file and look for 'type' into the global attributes. */
if(embed_fd) fd = embed_fd;
else fd=my_fopen(name,fopen_read_mode);
@ -4417,7 +4417,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
read_line(lcc[level].fd, 0);
continue;
}
if(fscanf(lcc[level].fd, "%lf %lf %lf %lf ",&tmpline.x1, &tmpline.y1,
&tmpline.x2, &tmpline.y2) < 4 ) {
fprintf(errfp,"l_s_d(): WARNING: missing fields for LINE object, ignoring\n");
@ -4426,21 +4426,21 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
tmpline.prop_ptr = NULL;
load_ascii_string(&tmpline.prop_ptr, lcc[level].fd);
if( !strboolcmp(get_tok_value(tmpline.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmpline.prop_ptr);
continue;
}
i=lastl[c];
my_realloc(_ALLOC_ID_, &ll[c],(i+1)*sizeof(xLine));
ll[c][i].x1 = tmpline.x1;
ll[c][i].y1 = tmpline.y1;
ll[c][i].x2 = tmpline.x2;
ll[c][i].y2 = tmpline.y2;
ll[c][i].prop_ptr = tmpline.prop_ptr;
if (level>0) {
rot = lcc[level].rot; flip = lcc[level].flip;
ROTATION(rot, flip, 0.0, 0.0, ll[c][i].x1, ll[c][i].y1, rx1, ry1);
@ -4471,7 +4471,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
read_line(lcc[level].fd, 0);
continue;
}
tmppoly.x = my_calloc(_ALLOC_ID_, poly_points, sizeof(double));
tmppoly.y = my_calloc(_ALLOC_ID_, poly_points, sizeof(double));
tmppoly.selected_point = my_calloc(_ALLOC_ID_, poly_points, sizeof(unsigned short));
@ -4486,27 +4486,27 @@ int load_sym_def(const char *name, FILE *embed_fd)
tmppoly.x[k] = lcc[level].x0 + rx1; tmppoly.y[k] = lcc[level].y0 + ry1;
}
}
tmppoly.prop_ptr=NULL;
load_ascii_string( &tmppoly.prop_ptr, lcc[level].fd);
if( !strboolcmp(get_tok_value(tmppoly.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmppoly.prop_ptr);
my_free(_ALLOC_ID_, &tmppoly.x);
my_free(_ALLOC_ID_, &tmppoly.y);
my_free(_ALLOC_ID_, &tmppoly.selected_point);
continue;
continue;
}
i=lastp[c];
my_realloc(_ALLOC_ID_, &pp[c],(i+1)*sizeof(xPoly));
pp[c][i].x = tmppoly.x;
pp[c][i].y = tmppoly.y;
pp[c][i].selected_point = tmppoly.selected_point;
pp[c][i].prop_ptr = tmppoly.prop_ptr;
pp[c][i].points = poly_points;
fill_ptr = get_tok_value(pp[c][i].prop_ptr,"fill",0);
if( !strcmp(fill_ptr, "full") )
pp[c][i].fill = 2; /* bit 1: solid fill (not stippled) */
@ -4514,14 +4514,14 @@ int load_sym_def(const char *name, FILE *embed_fd)
pp[c][i].fill = 1;
else
pp[c][i].fill = 0;
attr = get_tok_value(pp[c][i].prop_ptr,"dash", 0);
if( strcmp(attr, "") ) {
int d = atoi(attr);
pp[c][i].dash = (short)(d >= 0 ? d : 0);
} else
pp[c][i].dash = 0;
pp[c][i].sel = 0;
pp[c][i].bus = get_attr_val(get_tok_value(pp[c][i].prop_ptr,"bus", 0));
dbg(2, "l_s_d(): loaded polygon: ptr=%lx\n", (unsigned long)pp[c]);
@ -4534,7 +4534,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
read_line(lcc[level].fd, 0);
continue;
}
if( fscanf(lcc[level].fd, "%lf %lf %lf %lf %lf ",&tmparc.x, &tmparc.y,
&tmparc.r, &tmparc.a, &tmparc.b) < 5 ) {
fprintf(errfp,"l_s_d(): WARNING: missing fields for ARC object, ignoring\n");
@ -4543,22 +4543,22 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
tmparc.prop_ptr = NULL;
load_ascii_string( &tmparc.prop_ptr, lcc[level].fd);
if( !strboolcmp(get_tok_value(tmparc.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmparc.prop_ptr);
continue;
}
i=lasta[c];
my_realloc(_ALLOC_ID_, &aa[c],(i+1)*sizeof(xArc));
aa[c][i].x = tmparc.x;
aa[c][i].y = tmparc.y;
aa[c][i].r = tmparc.r;
aa[c][i].a = tmparc.a;
aa[c][i].b = tmparc.b;
aa[c][i].prop_ptr = tmparc.prop_ptr;
if (level>0) {
rot = lcc[level].rot; flip = lcc[level].flip;
if (flip) {
@ -4598,7 +4598,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
read_line(lcc[level].fd, 0);
continue;
}
if(fscanf(lcc[level].fd, "%lf %lf %lf %lf ",&tmprect.x1, &tmprect.y1,
&tmprect.x2, &tmprect.y2) < 4 ) {
fprintf(errfp,"l_s_d(): WARNING: missing fields for LINE object, ignoring\n");
@ -4607,22 +4607,22 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
tmprect.prop_ptr = NULL;
load_ascii_string(&tmprect.prop_ptr, lcc[level].fd);
if( !strboolcmp(get_tok_value(tmprect.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmprect.prop_ptr);
continue;
}
if (level>0 && c == PINLAYER) c = 7; /* Don't care about pins inside SYM: set on different layer */
i=lastr[c];
my_realloc(_ALLOC_ID_, &bb[c],(i+1)*sizeof(xRect));
bb[c][i].x1 = tmprect.x1;
bb[c][i].y1 = tmprect.y1;
bb[c][i].x2 = tmprect.x2;
bb[c][i].y2 = tmprect.y2;
bb[c][i].prop_ptr = tmprect.prop_ptr;
if (level>0) {
rot = lcc[level].rot; flip = lcc[level].flip;
ROTATION(rot, flip, 0.0, 0.0, bb[c][i].x1, bb[c][i].y1, rx1, ry1);
@ -4649,7 +4649,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
int d = atoi(attr);
bb[c][i].dash = (short)(d >= 0 ? d : 0);
} else bb[c][i].dash = 0;
bb[c][i].bus = get_attr_val(get_tok_value(bb[c][i].prop_ptr,"bus", 0));
attr = get_tok_value(bb[c][i].prop_ptr,"ellipse", 0);
if( strcmp(attr, "") ) {
@ -4665,7 +4665,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
bb[c][i].ellipse_a = -1;
bb[c][i].ellipse_b = -1;
}
bb[c][i].sel = 0;
bb[c][i].extraptr = NULL;
set_rect_flags(&bb[c][i]);
@ -4681,7 +4681,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
continue;
}
load_ascii_string(&tmptext.prop_ptr, lcc[level].fd);
is_floater = 0;
get_tok_value(tmptext.prop_ptr, "name", 2);
if(xctx->tok_size) is_floater = 1; /* get rid of floater texts in LCC symbols */
@ -4748,9 +4748,9 @@ int load_sym_def(const char *name, FILE *embed_fd)
for(i = 1; i <level; ++i) {
const char *instname = get_tok_value(lcc[i].prop_ptr, "name", 0);
my_strcat(_ALLOC_ID_, &path, instname);
my_strcat(_ALLOC_ID_, &path, ".");
my_strcat(_ALLOC_ID_, &path, ".");
}
}
}
if(path) new_size += strlen(path);
dev = get_tok_value(prop_ptr, "name", 0);
new_size += strlen(tt[i].txt_ptr) + strlen(dev) + 2 + 1; /* tok(<dev>) */
@ -4760,7 +4760,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
tt[i].txt_ptr = txt_ptr;
my_free(_ALLOC_ID_, &path);
dbg(1, "--> tt[i].txt_ptr=%s\n", tt[i].txt_ptr);
}
}
ROTATION(rot, flip, 0.0, 0.0, tt[i].x0, tt[i].y0, rx1, ry1);
tt[i].x0 = lcc[level].x0 + rx1; tt[i].y0 = lcc[level].y0 + ry1;
tt[i].rot = (tt[i].rot + ((lcc[level].flip && (tt[i].rot & 1)) ?
@ -4777,21 +4777,21 @@ int load_sym_def(const char *name, FILE *embed_fd)
++lastt;
break;
case 'N': /* store wires as lines on layer WIRELAYER. */
tmpline.prop_ptr = NULL;
if(fscanf(lcc[level].fd, "%lf %lf %lf %lf ",&tmpline.x1, &tmpline.y1,
&tmpline.x2, &tmpline.y2) < 4 ) {
fprintf(errfp,"l_s_d(): WARNING: missing fields for LINE object, ignoring\n");
read_line(lcc[level].fd, 0);
continue;
}
}
load_ascii_string(&tmpline.prop_ptr, lcc[level].fd);
if( !strboolcmp(get_tok_value(tmpline.prop_ptr, "symbol_ignore", 0), "true")) {
my_free(_ALLOC_ID_, &tmpline.prop_ptr);
continue;
}
i = lastl[WIRELAYER];
my_realloc(_ALLOC_ID_, &ll[WIRELAYER],(i+1)*sizeof(xLine));
ll[WIRELAYER][i].x1 = tmpline.x1;
@ -4799,7 +4799,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
ll[WIRELAYER][i].x2 = tmpline.x2;
ll[WIRELAYER][i].y2 = tmpline.y2;
ll[WIRELAYER][i].prop_ptr = tmpline.prop_ptr;
if (level>0) {
rot = lcc[level].rot; flip = lcc[level].flip;
ROTATION(rot, flip, 0.0, 0.0, ll[WIRELAYER][i].x1, ll[WIRELAYER][i].y1, rx1, ry1);
@ -4829,7 +4829,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
endfile = 1;
continue;
}
if(generator) {
/* for generators (data from a pipe) can not inspect next line (fseek/ftell) looking for
* embedded symbols. Assume no embedded symbol follows */
@ -4852,7 +4852,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
xfseek(lcc[level].fd, filepos, SEEK_SET); /* rewind file pointer */
}
dbg(1, "l_s_d(): level=%d, symname=%s symtype=%s\n", level, symname, symtype);
if( /* add here symbol types not to consider when loading schematic-as-symbol instances */
!symtype ||
!strcmp(symtype, "logo") ||
@ -4882,7 +4882,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
/* replace i/o/iopin.sym filename with better looking (for LCC symbol) pins */
use_lcc_pins(level, symtype, &sympath);
dbg(1, "l_s_d(): fopen2(%s), level=%d\n",sympath, level);
/* find out if symbol is in an external file or embedded, set fd_tmp accordingly */
if ((fd_tmp = my_fopen(sympath, fopen_read_mode)) == NULL) {
@ -4919,7 +4919,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
if (level > 1) {
short rot, flip;
static const int map[4]={0,3,2,1};
flip = lcc[level-1].flip;
rot = lcc[level-1].rot;
ROTATION(rot, flip, 0.0, 0.0, lcc[level].x0, lcc[level].y0,lcc[level].x0, lcc[level].y0);
@ -4932,7 +4932,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
}
my_strdup(_ALLOC_ID_, &lcc[level].prop_ptr, prop_ptr);
my_strdup(_ALLOC_ID_, &lcc[level].symname, symname);
dbg(1, "level incremented: level=%d, symname=%s, prop_ptr=%s sympath=%s\n",
dbg(1, "level incremented: level=%d, symname=%s, prop_ptr=%s sympath=%s\n",
level, symname, prop_ptr, sympath);
}
break;
@ -5017,7 +5017,7 @@ int load_sym_def(const char *name, FILE *embed_fd)
void make_schematic_symbol_from_sel(void)
{
char filename[PATH_MAX] = "";
char name[1024];
char name[1024];
my_snprintf(name, S(name), "save_file_dialog {Save file} * INITIALLOADDIR");
tcleval(name);
@ -5034,7 +5034,7 @@ void make_schematic_symbol_from_sel(void)
place_symbol(-1, filename, 0, 0, 0, 0, NULL, 4, 1, 0/*to_push_undo*/);
if (has_x)
{
my_snprintf(name, S(name),
my_snprintf(name, S(name),
"tk_messageBox -type okcancel -parent [xschem get topwindow] "
"-message {do you want to make symbol view for %s ?}", filename);
tcleval(name);
@ -5074,7 +5074,7 @@ void create_sch_from_sym(void)
my_strdup(_ALLOC_ID_, &pinname[1], tcleval("rel_sym_path [find_file_first opin.sym]"));
my_strdup(_ALLOC_ID_, &pinname[2], tcleval("rel_sym_path [find_file_first iopin.sym]"));
my_strdup(_ALLOC_ID_, &generic_pin, tcleval("rel_sym_path [find_file_first generic_pin.sym]"));
if(pinname[0] && pinname[1] && pinname[2] && generic_pin) {
rebuild_selected_array();
if(xctx->lastsel > 1) return;
@ -5137,7 +5137,7 @@ void create_sch_from_sym(void)
if(!sub_prop) continue;
/* remove dir=... from prop string 20171004 */
my_strdup(_ALLOC_ID_, &sub2_prop, subst_token(sub_prop, "dir", NULL));
my_strdup(_ALLOC_ID_, &dir, get_tok_value(rct[i].prop_ptr,"dir",0));
if(!sub2_prop) continue;
if(!dir) continue;
@ -5192,7 +5192,7 @@ int descend_symbol(void)
/* if circuit is changed but not saved before descending
* state will be inconsistent when returning, can not propagare hilights
* save() return value:
* 1 : file saved
* 1 : file saved
* -1 : user cancel
* 0 : file not saved due to errors or per user request
*/
@ -5222,7 +5222,7 @@ int descend_symbol(void)
xctx->inst[n].prop_ptr);
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].templ,
xctx->sym[xctx->inst[n].ptr].templ);
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].sym_extra,
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch].sym_extra,
get_tok_value(xctx->sym[xctx->inst[n].ptr].prop_ptr, "extra", 0));
if(!xctx->inst[n].embed)

42
src/scheduler.c
View File

@ -408,7 +408,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
{
int interactive = 0;
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
if(argc > 2) interactive = atoi(argv[2]);
attach_labels_to_inst(interactive);
Tcl_ResetResult(interp);
@ -1701,7 +1701,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
Tcl_SetResult(interp, xctx->schverilogprop ? xctx->schverilogprop : "", TCL_VOLATILE);
}
else if(!strcmp(argv[2], "schspectreprop")) /* get schematic "spectre" global attributes */
{
{
Tcl_SetResult(interp, xctx->schspectreprop ? xctx->schspectreprop : "", TCL_VOLATILE);
}
else if(!strcmp(argv[2], "schsymbolprop")) /* get schematic "symbol" global attributes */
@ -1746,7 +1746,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
else if(!strcmp(argv[2], "symbols")) { /* number of loaded symbols */
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
Tcl_SetResult(interp, my_itoa(xctx->symbols), TCL_VOLATILE);
}
}
break;
case 't':
@ -1890,7 +1890,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
/* get_fqdevice instname param modelparam
* get the full pathname of "instname" device
* modelparam:
* modelparam:
* 0: current, 1: modelparam, 2: modelvoltage
* param: device parameter, like ib, gm, vth
* set param to {} (empty str) for just branch current of 2 terminal device
@ -2385,18 +2385,18 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
{
const char *instname=NULL;
int i, fast = 0;
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
for(i = 2; i < argc; i++) {
if(argv[i][0] == '-') {
if(!strcmp(argv[i], "-fast")) {
fast = 1;
}
} else {
} else {
instname = argv[i];
break;
}
}
}
if(instname) {
int inst;
char *type;
@ -2431,7 +2431,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
Tcl_ResetResult(interp);
}
/* hilight_netname [-fast] net
/* hilight_netname [-fast] net
* Highlight net name 'net'
* if '-fast' is given do not redraw hilights after operation */
else if(!strcmp(argv[1], "hilight_netname"))
@ -3049,7 +3049,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
for(i = 2; i < argc; i++) {
if(argv[i][0] == '-') {
if(!strcmp(argv[i], "-nosymbols")) {
if(!strcmp(argv[i], "-nosymbols")) {
load_symbols = 0 ;
} else if(!strcmp(argv[i], "-gui")) {
force = 0;
@ -3172,7 +3172,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(!strcmp(argv[i], "-lastclosed")) {
my_strncpy(f, tcleval("get_lastclosed"), S(f));
} else if(!strcmp(argv[i], "-lastopened")) {
} else if(!strcmp(argv[i], "-lastopened")) {
my_strncpy(f, tcleval("get_lastopened"), S(f));
} else if(!is_from_web(argv[i])) {
my_snprintf(f, S(f),"regsub {^~/} {%s} {%s/}", argv[i], home_dir);
@ -3250,7 +3250,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
int res = -2;
struct stat buf;
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
if(argc > 2) {
if(argc > 2) {
int i = get_symbol(rel_sym_path(argv[2]));
if(i < 0 ) {
if(!stat(argv[2], &buf)) { /* file exists */
@ -3530,7 +3530,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
* will create the netlist in different places.
* netlisting directory is reset to previous setting after completing this command
* If -messages is given return the ERC messages instead of just a fail (1)
* or no fail (0) code.
* or no fail (0) code.
* If -erc is given it means netlister is called from gui, enable show infowindow
* If -nohier is given netlist only current level
* If -keep_symbols is given no not purge symbols encountered traversing the
@ -4701,7 +4701,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
} else {
xctx->ui_state |= MENUSTART;
xctx->ui_state2 = MENUSTARTRECT;
}
}
} else {
xctx->ui_state |= MENUSTART;
xctx->ui_state2 = MENUSTARTRECT;
@ -5599,7 +5599,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
else if(!strcmp(argv[2], "schspectreprop")) { /* set schematic global spectre attribute string */
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
my_strdup(_ALLOC_ID_, &xctx->schspectreprop, argv[3]);
}
}
else if(!strcmp(argv[2], "schvhdlprop")) { /* set schematic global vhdl attribute string */
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
my_strdup(_ALLOC_ID_, &xctx->schvhdlprop, argv[3]);
@ -5720,7 +5720,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
argc -= shift;
/* 0 1 2 3 4 5
/* 0 1 2 3 4 5
* xschem setprop instance R4 value [30k] */
if(argc > 2 && !strcmp(argv[2], "instance")) {
int inst;
@ -5736,7 +5736,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
char *translated_sym = NULL;
int sym_number = -1;
char *subst = NULL, *old_name = NULL;;
if(!fast) {
symbol_bbox(inst, &xctx->inst[inst].x1, &xctx->inst[inst].y1, &xctx->inst[inst].x2, &xctx->inst[inst].y2);
xctx->push_undo();
@ -5811,7 +5811,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
my_strdup2(_ALLOC_ID_, &sym->prop_ptr, subst_token(sym->prop_ptr, argv[4], NULL)); /* delete attr */
} else if(argc > 5 && !strcmp(argv[2], "rect")) {
/* 0 1 2 3 4 5 6
/* 0 1 2 3 4 5 6
* xschem setprop rect c n token [value] */
int change_done = 0;
xRect *r;
@ -5948,7 +5948,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
/* show_unconnected_pins
* Add a "lab_show.sym" to all instance pins that are not connected to anything */
else if(!strcmp(argv[1], "show_unconnected_pins") )
{
{
if(!xctx) {Tcl_SetResult(interp, not_avail, TCL_STATIC); return TCL_ERROR;}
show_unconnected_pins();
Tcl_ResetResult(interp);
@ -6192,7 +6192,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
extra_rawfile(3, NULL, NULL, -1.0, -1.0);
/* free_rawfile(&xctx->raw, 0, 0); */
table_read(f);
if(sch_waves_loaded() >= 0) {
my_strdup(_ALLOC_ID_, &xctx->raw->sim_type, "table");
draw();
@ -6513,7 +6513,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
/* unselect_attached_floaters
* Unselect objects (not symbol instances) attached to some instance with a
* Unselect objects (not symbol instances) attached to some instance with a
* non empty name=... attribute */
else if(!strcmp(argv[1], "unselect_attached_floaters"))
{
@ -6644,7 +6644,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
}
} else {
xctx->last_command = 0;
xctx->ui_state |= MENUSTART;
xctx->ui_state |= MENUSTART;
xctx->ui_state2 = MENUSTARTWIRE;
}
} else {

60
src/select.c
View File

@ -28,7 +28,7 @@
* Recursive routine
*/
static void check_connected_nets(int stop_at_junction, int n)
{
{
int k, touches;
xWire * const wire = xctx->wire;
Wireentry *wireptr;
@ -36,7 +36,7 @@ static void check_connected_nets(int stop_at_junction, int n)
char *type;
double x1, y1, x2, y2;
Iterator_ctx ctx;
x1 = wire[n].x1;
y1 = wire[n].y1;
x2 = wire[n].x2;
@ -78,7 +78,7 @@ static void check_connected_nets(int stop_at_junction, int n)
(wire[n].x1 == wire[k].x2 && wire[n].y1 == wire[k].y2 && wire[n].end1 < 2 && wire[k].end2 < 2) ||
(wire[n].x2 == wire[k].x1 && wire[n].y2 == wire[k].y1 && wire[n].end2 < 2 && wire[k].end1 < 2) ||
(wire[n].x2 == wire[k].x2 && wire[n].y2 == wire[k].y2 && wire[n].end2 < 2 && wire[k].end2 < 2);
}
}
if(touches) {
xctx->wire[k].sel = SELECTED;
check_connected_nets(stop_at_junction, k); /* recursive check */
@ -87,7 +87,7 @@ static void check_connected_nets(int stop_at_junction, int n)
}
}
/* stop_at_junction==1 --> stop selecting wires at 'T' junctions
/* stop_at_junction==1 --> stop selecting wires at 'T' junctions
* stop_at_junction==2 --> select only wires directly attached to selected net/instance
*/
void select_connected_nets(int stop_at_junction)
@ -132,7 +132,7 @@ void select_connected_nets(int stop_at_junction)
xRect *rct;
int n = iptr->n;
double x1, y1;
if(n == i) continue;
type = (xctx->inst[n].ptr+ xctx->sym)->type;
if( type && (!strcmp(type, "label") || !strcmp(type, "probe")) ) {
@ -176,7 +176,7 @@ int select_dangling_nets(void)
double x0, y0, x1, y1, x2, y2;
table = my_calloc(_ALLOC_ID_, xctx->wires, sizeof(int));
hash_instances();
hash_wires();
@ -229,7 +229,7 @@ int select_dangling_nets(void)
touch(wire[w].x1, wire[w].y1, wire[w].x2, wire[w].y2, wire[i].x2, wire[i].y2) ||
touch(wire[i].x1, wire[i].y1, wire[i].x2, wire[i].y2, wire[w].x1, wire[w].y1) ||
touch(wire[i].x1, wire[i].y1, wire[i].x2, wire[i].y2, wire[w].x2, wire[w].y2);
if(touches) {
if(touches) {
table[i] = 1; /* wire[i] also not dangling */
done = 0;
}
@ -296,7 +296,7 @@ int select_dangling_nets(void)
if(!rct) continue;
rects = (xctx->inst[n].ptr + xctx->sym)->rects[PINLAYER];
for(p = 0; p < rects; p++)
{
{
get_inst_pin_coord(n, p, &x1, &y1);
touches = (x0 == x1 && y0 == y1);
if(touches) {
@ -734,9 +734,9 @@ void bbox(int what,double x1,double y1, double x2, double y2)
}
}
/* n = -1 : clear first selected info
* n = -2 : return first selected element if still selected, or get first from
* selected list. If no elements selected return first selected item (j = 0)
/* n = -1 : clear first selected info
* n = -2 : return first selected element if still selected, or get first from
* selected list. If no elements selected return first selected item (j = 0)
* n >= 0 : store indicated element as first selected
*/
int set_first_sel(unsigned short type, int n, unsigned int col)
@ -744,7 +744,7 @@ int set_first_sel(unsigned short type, int n, unsigned int col)
if(n == -2) {
int j;
/* retrieve first selected element (if still selected)... */
if(xctx->first_sel.n >=0 && xctx->first_sel.type == ELEMENT &&
if(xctx->first_sel.n >=0 && xctx->first_sel.type == ELEMENT &&
xctx->inst[xctx->first_sel.n].sel == SELECTED) {
for(j=0; j < xctx->lastsel; j++) {
if(xctx->sel_array[j].type == ELEMENT && xctx->sel_array[j].n == xctx->first_sel.n) {
@ -948,7 +948,7 @@ void select_wire(int i,unsigned short select_mode, int fast, int override_lock)
static int select_attached_floaters(int inst, const char *name)
{
{
int i, c;
int found = 0;
char *attach = NULL;
@ -971,7 +971,7 @@ static int select_attached_floaters(int inst, const char *name)
select_line(c, i, SELECTED, 1, 1);
}
}
for(i = 0; i < xctx->polygons[c]; i++) {
if(!strcmp(name, get_tok_value(xctx->poly[c][i].prop_ptr, "name", 0))) {
found = 1;
@ -983,14 +983,14 @@ static int select_attached_floaters(int inst, const char *name)
found = 1;
select_arc(c, i, SELECTED, 1, 1);
}
}
}
}
for(i = 0; i < xctx->wires; i++) {
if(!strcmp(name, get_tok_value(xctx->wire[i].prop_ptr, "name", 0))) {
found = 1;
select_wire(i, SELECTED, 1, 1);
}
}
}
for(i = 0; i < xctx->texts; i++) {
if(!strcmp(name, get_tok_value(xctx->text[i].prop_ptr, "name", 0))) {
found = 1;
@ -1042,7 +1042,7 @@ void select_element(int i,unsigned short select_mode, int fast, int override_loc
}
}
tcleval("infowindow");
my_snprintf(str, S(str), "n=%4d x = %.16g y = %.16g w = %.16g h = %.16g",i,
my_snprintf(str, S(str), "n=%4d x = %.16g y = %.16g w = %.16g h = %.16g",i,
xctx->inst[i].xx1, xctx->inst[i].yy1,
xctx->inst[i].xx2-xctx->inst[i].xx1, xctx->inst[i].yy2-xctx->inst[i].yy1
);
@ -1149,7 +1149,7 @@ void select_box(int c, int i, unsigned short select_mode, int fast, int override
xctx->rect[c][i].x2, xctx->rect[c][i].y2);
} else {
xctx->rect[c][i].sel = 0;
if(!(fast & 2)) drawtemprect(xctx->gctiled, NOW, xctx->rect[c][i].x1, xctx->rect[c][i].y1,
if(!(fast & 2)) drawtemprect(xctx->gctiled, NOW, xctx->rect[c][i].x1, xctx->rect[c][i].y1,
xctx->rect[c][i].x2, xctx->rect[c][i].y2);
}
if( xctx->rect[c][i].sel == (SELECTED1|SELECTED2|SELECTED3|SELECTED4)) xctx->rect[c][i].sel = SELECTED;
@ -1173,7 +1173,7 @@ void select_arc(int c, int i, unsigned short select_mode, int fast, int override
my_snprintf(str, S(str), "Info: selected arc : layer=%d, n=%d properties: %s",c-4,i,s);
statusmsg(str,3);
tcleval("infowindow");
my_snprintf(str, S(str), "n=%4d x = %.16g y = %.16g r = %.16g a = %.16g b = %.16g",
i, xctx->arc[c][i].x, xctx->arc[c][i].y, xctx->arc[c][i].r, xctx->arc[c][i].a, xctx->arc[c][i].b);
statusmsg(str,1);
@ -1279,7 +1279,7 @@ Selected select_object(double mx,double my, unsigned short select_mode,
{
Selected sel;
xctx->already_selected = 0;
if(!selptr)
if(!selptr)
sel = find_closest_obj(mx, my, override_lock);
else
sel = *selptr;
@ -1441,7 +1441,7 @@ void select_inside(int stretch, double x1,double y1, double x2, double y2, int s
#endif
estr = my_expand(get_text_floater(i), tclgetintvar("tabstop"));
text_bbox(estr,
xctx->text[i].xscale, xctx->text[i].yscale, (short)select_rot, (short)select_flip,
xctx->text[i].xscale, xctx->text[i].yscale, (short)select_rot, (short)select_flip,
xctx->text[i].hcenter, xctx->text[i].vcenter,
xctx->text[i].x0, xctx->text[i].y0,
&xx1,&yy1, &xx2,&yy2, &tmpint, &dtmp);
@ -1485,7 +1485,7 @@ void select_inside(int stretch, double x1,double y1, double x2, double y2, int s
if(!xctx->enable_layer[c]) continue;
for(i=0;i<xctx->polygons[c]; ++i) {
int k, selected_points, flag;
polygon_bbox(xctx->poly[c][i].x, xctx->poly[c][i].y, xctx->poly[c][i].points, &xa, &ya, &xb, &yb);
if(RECT_OUTSIDE(xa, ya, xb, yb, x1, y1, x2, y2)) continue;
selected_points = 0;
@ -1510,7 +1510,7 @@ void select_inside(int stretch, double x1,double y1, double x2, double y2, int s
if(sel && stretch) select_polygon(c, i, SELECTED1, 1, 0);
}
}
}
for(i=0;i<xctx->lines[c]; ++i)
{
@ -1604,7 +1604,7 @@ void select_inside(int stretch, double x1,double y1, double x2, double y2, int s
select_box(c, i,SELECTED4,1, 0);
}
}
} /* end for i */
} /* end for c */
drawtemparc(xctx->gc[SELLAYER], END, 0.0, 0.0, 0.0, 0.0, 0.0);
@ -1654,7 +1654,7 @@ void select_touch(double x1,double y1, double x2, double y2, int sel) /*added un
estr = my_expand(get_text_floater(i), tclgetintvar("tabstop"));
text_bbox(estr,
xctx->text[i].xscale, xctx->text[i].yscale, (short)select_rot, (short)select_flip,
xctx->text[i].xscale, xctx->text[i].yscale, (short)select_rot, (short)select_flip,
xctx->text[i].hcenter, xctx->text[i].vcenter,
xctx->text[i].x0, xctx->text[i].y0,
&xx1,&yy1, &xx2,&yy2, &tmpint, &dtmp);
@ -1689,7 +1689,7 @@ void select_touch(double x1,double y1, double x2, double y2, int sel) /*added un
if(!xctx->enable_layer[c]) continue;
for(i=0;i<xctx->polygons[c]; ++i) {
int k, flag;
polygon_bbox(xctx->poly[c][i].x, xctx->poly[c][i].y, xctx->poly[c][i].points, &xa, &ya, &xb, &yb);
if(RECT_OUTSIDE(xa, ya, xb, yb, x1, y1, x2, y2)) continue;
flag=0;
@ -1800,15 +1800,15 @@ int floaters_from_selected_inst()
txty0 = symtxt->y0;
txtrot = symtxt->rot;
txtflip = symtxt->flip;
rot = (txtrot + ( (instflip && (txtrot & 1) ) ? instrot+2 : instrot) ) & 0x3;
flip = txtflip ^ instflip;
ROTATION(instrot, instflip, 0.0, 0.0, txtx0, txty0, x0, y0);
x0 += instx0;
y0 += insty0;
create_text(0, x0, y0, rot, flip, symtxt->txt_ptr,
create_text(0, x0, y0, rot, flip, symtxt->txt_ptr,
subst_token(symtxt->prop_ptr, "name", xctx->inst[i].instname),
symtxt->xscale, symtxt->yscale);
xctx->text[xctx->texts - 1].sel = SELECTED;

18
src/sort_labels.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: sort_labels.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -31,13 +31,13 @@ BEGIN{
}
# LDYMS[12]
{
{
line[lines++] = $0 " " hash_string($1)
}
END{
close(FILENAME)
close(FILENAME)
for(i=0;i< lines;i++) {
print line[i] > FILENAME
@ -48,12 +48,12 @@ END{
}
function hash_string(s, n, i, h, c)
function hash_string(s, n, i, h, c)
{
n = s
sub(/^.*\[/,"",n)
sub(/\].*/,"",n)
sub(/\[.*/, "", s)
sub(/\[.*/, "", s)
h = s "__" sprintf("%08d", n)

50
src/spectre.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#!/usr/bin/awk -f
#
# File: spice.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -28,7 +28,7 @@ BEGIN{
user_code=0 #20180129
while( (ARGV[1] ~ /^[-]/) || (ARGV[1] ~ /^$/) ) {
# if(ARGV[1] == "-xyce") { xyce = 1}
# if(ARGV[1] == "-xyce") { xyce = 1}
for(i=2; i<= ARGC;i++) {
ARGV[i-1] = ARGV[i]
}
@ -55,7 +55,7 @@ END{
## resolve parametric instance name vector multiplicity
substitute_instance_param()
for(i=0; i<lines; i++) {
$0 = line[i]
@ -113,7 +113,7 @@ function substitute_instance_param( i, j, name, first, last)
}
function sign(x)
function sign(x)
{
return x<0 ? -1 : x>0 ? 1 : 0
}
@ -162,22 +162,22 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
#20150922 handle the case of pmos elements that netlist also a diode
# format="@name @pinlist @model w=@w l=@l geomod=0 m=@m
# #dx#name 0 @@b dnwell area=... pj=..."
# replace #dx#name with dx prefix added on all @name elements
# replace #dx#name with dx prefix added on all @name elements
# example:
# m6[3] GWL WLDECF[3] WL[3] HDD phv w=50u l=10u geomod=0 m=1
# m6[2] GWL WLDECF[2] WL[2] HDD phv w=50u l=10u geomod=0 m=1
# m6[1] GWL WLDECF[1] WL[1] HDD phv w=50u l=10u geomod=0 m=1
# m6[0] GWL WLDECF[0] WL[0] HDD phv w=50u l=10u geomod=0 m=1
# dxm6[3] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[2] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[1] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[0] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# m6[3] GWL WLDECF[3] WL[3] HDD phv w=50u l=10u geomod=0 m=1
# m6[2] GWL WLDECF[2] WL[2] HDD phv w=50u l=10u geomod=0 m=1
# m6[1] GWL WLDECF[1] WL[1] HDD phv w=50u l=10u geomod=0 m=1
# m6[0] GWL WLDECF[0] WL[0] HDD phv w=50u l=10u geomod=0 m=1
# dxm6[3] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[2] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[1] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[0] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
#20151027 do this for all fields
for(i=1; i<=NF;i++) {
if($i ~/^##[a-zA-Z_]+/) {
sub(/^##/, "", $i)
} else
} else
if($i ~/^#[a-zA-Z_0-9]+#[a-zA-Z_]+/) {
iprefix=$i
sub(/^#/,"",iprefix)
@ -187,8 +187,8 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
## 20160301 add '?1' if missing in format string
if(i>1 && ( $(i-1) !~/^\?/) ) {
$i = "?1 " $i
}
$0 = $0 # reparse input line
}
$0 = $0 # reparse input line
}
}
## 20140506 do not transform {} of variation groups
@ -217,7 +217,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
sub(/ value=/," c=")
IGNORECASE=0
}
### ?? too dangerous
### ?? too dangerous
# gsub(/ value=/," ")
# gsub(/ VALUE=/," ")
@ -235,10 +235,10 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
num = split($1, name, ",")
if(num==0) print ""
for(j=2;j<=NF;j+=1) # start from 2 not from 3 20070221
{
# ............ --> matches ?n and ?-n
# ............ --> matches ?n and ?-n
# some CDL netlists have this: $SUB=?1 B where B is a node
if($j ~/^(.*=)?\?-?[0-9]+$/) continue # handle the case that $2 not pinlist 20070221
arg_num[j]=split($j,tmp,",")

22
src/spectre_netlist.c
View File

@ -94,7 +94,7 @@ static int spectre_netlist(FILE *fd, int spectre_stop )
{
if(skip_instance(i, 1, lvs_ignore)) continue;
type = (xctx->inst[i].ptr+ xctx->sym)->type;
if( type && !IS_LABEL_OR_PIN(type) ) {
/* already done in global_spectre_netlist */
if(!strcmp(type,"netlist_commands") && xctx->netlist_count==0) continue;
@ -187,7 +187,7 @@ int global_spectre_netlist(int global, int alert) /* netlister driver */
bus_char[1] = str_tmp[1];
}
xctx->netlist_count=0;
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
tclgetvar("netlist_dir"), get_cell(xctx->sch[xctx->currsch], 0), getpid());
dbg(1, "global_spectre_netlist(): opening %s for writing\n",netl_filename);
fd=fopen(netl_filename, "w");
@ -231,7 +231,7 @@ int global_spectre_netlist(int global, int alert) /* netlister driver */
}
}
if(!top_sub) fprintf(fd,"//");
if(uppercase_subckt)
if(uppercase_subckt)
fprintf(fd,"SUBCKT %s ( ", get_cell(xctx->sch[xctx->currsch], 0));
else
fprintf(fd,"subckt %s ( ", get_cell(xctx->sch[xctx->currsch], 0));
@ -243,7 +243,7 @@ int global_spectre_netlist(int global, int alert) /* netlister driver */
dbg(1, "found top level symbol %s\n", top_symbol_name);
load_sym_def(top_symbol_name, NULL);
found_top_symbol = 1;
if(xctx->sym[xctx->symbols - 1].type != NULL &&
if(xctx->sym[xctx->symbols - 1].type != NULL &&
/* only use the symbol if it has pins and is a subcircuit ? */
/* !strcmp(xctx->sym[xctx->symbols - 1].type, "subcircuit") && */
xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) {
@ -298,7 +298,7 @@ int global_spectre_netlist(int global, int alert) /* netlister driver */
/* /20100217 */
if(!top_sub) fprintf(fd,"//");
if(uppercase_subckt)
if(uppercase_subckt)
fprintf(fd, "ENDS\n");
else
fprintf(fd, "ends\n");
@ -323,9 +323,9 @@ int global_spectre_netlist(int global, int alert) /* netlister driver */
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
stored_flags = my_calloc(_ALLOC_ID_, xctx->instances, sizeof(unsigned int));
for(i=0;i<xctx->instances; ++i) stored_flags[i] = xctx->inst[i].color;
if(global)
{
{
int saved_hilight_nets = xctx->hilight_nets;
int web_url = is_from_web(xctx->current_dirname);
char *current_dirname_save = NULL;
@ -360,7 +360,7 @@ int global_spectre_netlist(int global, int alert) /* netlister driver */
/* only additional symbols (created with instance schematic=... attr) will have this attribute */
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch - 1].prop_ptr,
tcl_hook2(xctx->sym[i].parent_prop_ptr));
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch - 1].sym_extra,
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch - 1].sym_extra,
get_tok_value(xctx->sym[i].prop_ptr, "extra", 0));
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
@ -515,7 +515,7 @@ int spectre_block_netlist(FILE *fd, int i, int alert)
char *name = NULL;
const char *default_schematic;
int uppercase_subckt = tclgetboolvar("uppercase_subckt");
split_f = tclgetboolvar("split_files");
if(!strboolcmp( get_tok_value(xctx->sym[i].prop_ptr,"spectre_stop",0),"true") )
@ -573,12 +573,12 @@ int spectre_block_netlist(FILE *fd, int i, int alert)
/*
* fprintf(fd, "%s ", extra ? extra : "" );
*/
/* 20081206 new get_sym_template does not return token=value pairs where token listed in extra */
fprintf(fd, "\nparameters %s", get_sym_template(xctx->sym[i].templ, extra));
my_free(_ALLOC_ID_, &extra);
fprintf(fd, "\n");
spectre_stop ? load_schematic(0,filename, 0, alert) : load_schematic(1,filename, 0, alert);
get_additional_symbols(1);
err |= spectre_netlist(fd, spectre_stop); /* 20111113 added spectre_stop */

62
src/spice.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#!/usr/bin/awk -f
#
# File: spice.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -39,7 +39,7 @@ BEGIN{
special_devs[".subckt"] = 1
while( (ARGV[1] ~ /^[-]/) || (ARGV[1] ~ /^$/) ) {
if(ARGV[1] == "-xyce") { xyce = 1}
if(ARGV[1] == "-xyce") { xyce = 1}
for(i=2; i<= ARGC;i++) {
ARGV[i-1] = ARGV[i]
}
@ -61,7 +61,7 @@ BEGIN{
zz = yy
yy = $0
$0 = zz
if(first) {
if(first) {
first=0
next
}
@ -79,7 +79,7 @@ END{
## resolve parametric instance name vector multiplicity
substitute_instance_param()
for(i=0; i<lines; i++) {
$0 = line[i]
@ -89,7 +89,7 @@ END{
if(tolower($0) ~/^[ \t]*\.save[ \t]+.*\?-?[0-9]+/) { # .save file=test1.raw format=raw v( ?1 C2 )
$1 = ""
$0 = ".print " $0
}
}
gsub(/ [mM] *= *1 *$/,"") # xyce does not like m=# fields (multiplicity) removing m=1 is no an issue anyway
}
process()
@ -142,7 +142,7 @@ function substitute_instance_param( i, j, name, first, last)
}
function sign(x)
function sign(x)
{
return x<0 ? -1 : x>0 ? 1 : 0
}
@ -190,22 +190,22 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
#20150922 handle the case of pmos elements that netlist also a diode
# format="@name @pinlist @model w=@w l=@l geomod=0 m=@m
# #dx#name 0 @@b dnwell area=... pj=..."
# replace #dx#name with dx prefix added on all @name elements
# replace #dx#name with dx prefix added on all @name elements
# example:
# m6[3] GWL WLDECF[3] WL[3] HDD phv w=50u l=10u geomod=0 m=1
# m6[2] GWL WLDECF[2] WL[2] HDD phv w=50u l=10u geomod=0 m=1
# m6[1] GWL WLDECF[1] WL[1] HDD phv w=50u l=10u geomod=0 m=1
# m6[0] GWL WLDECF[0] WL[0] HDD phv w=50u l=10u geomod=0 m=1
# dxm6[3] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[2] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[1] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[0] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# m6[3] GWL WLDECF[3] WL[3] HDD phv w=50u l=10u geomod=0 m=1
# m6[2] GWL WLDECF[2] WL[2] HDD phv w=50u l=10u geomod=0 m=1
# m6[1] GWL WLDECF[1] WL[1] HDD phv w=50u l=10u geomod=0 m=1
# m6[0] GWL WLDECF[0] WL[0] HDD phv w=50u l=10u geomod=0 m=1
# dxm6[3] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[2] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[1] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
# dxm6[0] 0 HDD dnwell area='(50u + 73u)*(10u + 32u)' pj='2*(50u +73u)+2*(10u +32u)'
#20151027 do this for all fields
for(i=1; i<=NF;i++) {
if($i ~/^##[a-zA-Z_]+/) {
sub(/^##/, "", $i)
} else
} else
if($i ~/^#[a-zA-Z_0-9]+#[a-zA-Z_]+/) {
iprefix=$i
sub(/^#/,"",iprefix)
@ -215,8 +215,8 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
## 20160301 add '?1' if missing in format string
if(i>1 && ( $(i-1) !~/^\?/) ) {
$i = "?1 " $i
}
$0 = $0 # reparse input line
}
$0 = $0 # reparse input line
}
}
## 20140506 do not transform {} of variation groups
@ -245,7 +245,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
sub(/ value=/," c=")
IGNORECASE=0
}
### ?? too dangerous
### ?? too dangerous
# gsub(/ value=/," ")
# gsub(/ VALUE=/," ")
@ -259,8 +259,8 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
if(!xyce) {
$1=""
$0 = $0 # reparse line for field splitting
gsub(/ *\?-?[0-9]+ */, "") # in some cases ?-1 is printed (unknow multiplicity)
gsub(/ *\?-?[0-9]+ */, "") # in some cases ?-1 is printed (unknow multiplicity)
gsub(/\( */, "(")
gsub(/ *\)/, ")")
for(i=1; i<=NF; i++) {
@ -273,7 +273,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
}
}
}
} else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
num=split($2,name,",")
for(i=1;i<=num;i++) print $1 " " name[i]
@ -284,7 +284,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
print $0
} else {
# handle uncommon primitives that have a prefix before the device name
if(tolower($1) in special_devs) {
if(tolower($1) in special_devs) {
# YDELAY ?1 Rda[4],Rda[3],Rda[2],Rda[1],Rda[0] ?1 softrst[4],softrst[3],...
devprefix = $1
num = split($3, name, ",")
@ -300,10 +300,10 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
}
if(num==0) print ""
for(j=2;j<=NF;j+=1) # start from 2 not from 3 20070221
{
# ............ --> matches ?n and ?-n
# ............ --> matches ?n and ?-n
# some CDL netlists have this: $SUB=?1 B where B is a node
if($j ~/^(.*=)?\?-?[0-9]+$/) continue # handle the case that $2 not pinlist 20070221
arg_num[j]=split($j,tmp,",")

32
src/spice_netlist.c
View File

@ -29,7 +29,7 @@ static const char *hier_psprint_mtime(const char *file_name)
static char date[200];
struct stat time_buf;
struct tm *tm;
my_strncpy(date, "xxxxxxxx_xxxxxx", S(date));
my_strncpy(date, "xxxxxxxx_xxxxxx", S(date));
if(!stat(file_name , &time_buf)) {
tm=localtime(&(time_buf.st_mtime) );
strftime(date, sizeof(date), "%Y%m%d_%H%M%S", tm);
@ -38,8 +38,8 @@ static const char *hier_psprint_mtime(const char *file_name)
return date;
}
/*
* what:
/*
* what:
* 1 : ps/pdf print
* 2 : list hierarchy
*/
@ -52,7 +52,7 @@ void hier_psprint(char **res, int what) /* netlister driver */
struct stat buf;
Str_hashtable subckt_table = {NULL, 0};
int save_prev_mod = xctx->prev_set_modify;
save = xctx->do_copy_area;
xctx->do_copy_area = 0;
if((what & 1) && !ps_draw(1, 1, 0)) return; /* prolog */
@ -208,7 +208,7 @@ static int spice_netlist(FILE *fd, int spice_stop )
{
if(skip_instance(i, 1, lvs_ignore)) continue;
type = (xctx->inst[i].ptr+ xctx->sym)->type;
if( type && !IS_LABEL_OR_PIN(type) ) {
/* already done in global_spice_netlist */
if(!strcmp(type,"netlist_commands") && xctx->netlist_count==0) continue;
@ -301,7 +301,7 @@ int global_spice_netlist(int global, int alert) /* netlister driver */
bus_char[1] = str_tmp[1];
}
xctx->netlist_count=0;
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
tclgetvar("netlist_dir"), get_cell(xctx->sch[xctx->currsch], 0), getpid());
dbg(1, "global_spice_netlist(): opening %s for writing\n",netl_filename);
fd=fopen(netl_filename, "w");
@ -345,7 +345,7 @@ int global_spice_netlist(int global, int alert) /* netlister driver */
}
}
if(!top_sub) fprintf(fd,"**");
if(uppercase_subckt)
if(uppercase_subckt)
fprintf(fd,".SUBCKT %s", get_cell(xctx->sch[xctx->currsch], 0));
else
fprintf(fd,".subckt %s", get_cell(xctx->sch[xctx->currsch], 0));
@ -357,7 +357,7 @@ int global_spice_netlist(int global, int alert) /* netlister driver */
dbg(1, "found top level symbol %s\n", top_symbol_name);
load_sym_def(top_symbol_name, NULL);
found_top_symbol = 1;
if(xctx->sym[xctx->symbols - 1].type != NULL &&
if(xctx->sym[xctx->symbols - 1].type != NULL &&
/* only use the symbol if it has pins and is a subcircuit ? */
/* !strcmp(xctx->sym[xctx->symbols - 1].type, "subcircuit") && */
xctx->sym[xctx->symbols - 1].rects[PINLAYER] > 0) {
@ -412,7 +412,7 @@ int global_spice_netlist(int global, int alert) /* netlister driver */
/* /20100217 */
if(!top_sub) fprintf(fd,"**");
if(uppercase_subckt)
if(uppercase_subckt)
fprintf(fd, ".ENDS\n");
else
fprintf(fd, ".ends\n");
@ -437,9 +437,9 @@ int global_spice_netlist(int global, int alert) /* netlister driver */
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
stored_flags = my_calloc(_ALLOC_ID_, xctx->instances, sizeof(unsigned int));
for(i=0;i<xctx->instances; ++i) stored_flags[i] = xctx->inst[i].color;
if(global)
{
{
int saved_hilight_nets = xctx->hilight_nets;
int web_url = is_from_web(xctx->current_dirname);
char *current_dirname_save = NULL;
@ -474,7 +474,7 @@ int global_spice_netlist(int global, int alert) /* netlister driver */
/* only additional symbols (created with instance schematic=... attr) will have this attribute */
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch - 1].prop_ptr,
tcl_hook2(xctx->sym[i].parent_prop_ptr));
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch - 1].sym_extra,
my_strdup(_ALLOC_ID_, &xctx->hier_attr[xctx->currsch - 1].sym_extra,
get_tok_value(xctx->sym[i].prop_ptr, "extra", 0));
my_strdup(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
@ -629,7 +629,7 @@ int spice_block_netlist(FILE *fd, int i, int alert)
char *name = NULL;
const char *default_schematic;
int uppercase_subckt = tclgetboolvar("uppercase_subckt");
split_f = tclgetboolvar("split_files");
if(!strboolcmp( get_tok_value(xctx->sym[i].prop_ptr,"spice_stop",0),"true") )
@ -680,18 +680,18 @@ int spice_block_netlist(FILE *fd, int i, int alert)
else
fprintf(fd, ".subckt %s ", s);
print_spice_subckt_nodes(fd, i);
my_strdup(_ALLOC_ID_, &extra, get_tok_value(xctx->sym[i].prop_ptr,"extra",0) );
/* this is now done in print_spice_subckt_nodes */
/*
* fprintf(fd, "%s ", extra ? extra : "" );
*/
/* 20081206 new get_sym_template does not return token=value pairs where token listed in extra */
fprintf(fd, "%s", get_sym_template(xctx->sym[i].templ, extra));
my_free(_ALLOC_ID_, &extra);
fprintf(fd, "\n");
spice_stop ? load_schematic(0,filename, 0, alert) : load_schematic(1,filename, 0, alert);
get_additional_symbols(1);
err |= spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */

8
src/store.c
View File

@ -69,13 +69,13 @@ void check_inst_storage(void)
if(xctx->instances >= xctx->maxi)
{
int i, old = xctx->maxi;
xctx->maxi=(1 + xctx->instances / ELEMINST) * ELEMINST;
my_realloc(_ALLOC_ID_, &xctx->inst, sizeof(xInstance)*xctx->maxi);
#ifdef ZERO_REALLOC
memset(xctx->inst + xctx->instances, 0, sizeof(xInstance) * (xctx->maxi - xctx->instances));
#endif
/* clear all flag bits (to avoid random data in bit 8, that can not be cleraed
/* clear all flag bits (to avoid random data in bit 8, that can not be cleraed
* by set_inst_flags() */
for(i = old; i < xctx->maxi; i++) xctx->inst[i].flags = 0;
}
@ -171,7 +171,7 @@ void store_arc(int pos, double x, double y, double r, double a, double b,
xctx->arcs[rectc]++;
}
void store_poly(int pos, double *x, double *y, int points, unsigned int rectc,
void store_poly(int pos, double *x, double *y, int points, unsigned int rectc,
unsigned short sel, char *prop_ptr)
{
int n, j;
@ -288,7 +288,7 @@ int storeobject(int pos, double x1,double y1,double x2,double y2,
xctx->rect[rectc][n].bus = 0.0;
if(prop_ptr) {
xctx->rect[rectc][n].bus = get_attr_val(get_tok_value(prop_ptr, "bus", 0));
}
}
if(prop_ptr && (attr = get_tok_value(prop_ptr,"dash",0))[0]) {
int d = atoi(attr);
xctx->rect[rectc][n].dash = (char) (d >= 0 ? d : 0);

2
src/supergrep.awk
View File

@ -35,7 +35,7 @@ FNR == 1 { a=b=c=d=e=f=g=h=i=j=k=l="" }
print h
print i
print ""
}
}
' $@

96
src/svgdraw.c
View File

@ -74,7 +74,7 @@ static void svg_xfillrectangle(int layer, double x1, double y1, double x2, doubl
double bus, int dash, int fill)
{
double width;
if(bus == -1.0) width = BUS_WIDTH * svg_linew;
else if(bus > 0.0) width = bus * xctx->mooz;
else width = -1.0;
@ -89,15 +89,15 @@ static void svg_xfillrectangle(int layer, double x1, double y1, double x2, doubl
if(bus > 0.0) {
fprintf(fd, " stroke-linecap:square;\n");
fprintf(fd, " stroke-linejoin:miter;\n");
}
if(fill == 0) {
}
if(fill == 0) {
fprintf(fd,"fill:none;\" ");
} else if(fill == 2) {
fprintf(fd, "fill-opacity:1.0;\" ");
} else {
fprintf(fd, "\" ");
}
}
}
}
fprintf(fd,"d=\"M%g %gL%g %gL%g %gL%g %gL%g %gz\"/>\n", x1, y1, x2, y1, x2, y2, x1, y2, x1, y1);
}
@ -209,7 +209,7 @@ static void svg_filledrect(int gc, double rectx1,double recty1,double rectx2,dou
{
double x1,y1,x2,y2;
double width;
if(bus == -1.0) width = BUS_WIDTH * svg_linew;
else if(bus > 0.0) width = bus * xctx->mooz;
else width = -1.0;
@ -250,8 +250,8 @@ static void svg_filledrect(int gc, double rectx1,double recty1,double rectx2,dou
if(bus > 0.0) {
fprintf(fd, " stroke-linecap:square;\n");
fprintf(fd, " stroke-linejoin:miter;\n");
}
if(fill == 0) {
}
if(fill == 0) {
fprintf(fd,"fill:none;\" ");
fprintf(fd, "d=\"M%g %g A%g %g 0 %d %d %g %g\"/>\n", xx1, yy1, rx, ry, fa, fs, xx2, yy2);
} else if(fill == 2) {
@ -260,8 +260,8 @@ static void svg_filledrect(int gc, double rectx1,double recty1,double rectx2,dou
} else {
fprintf(fd, "\" ");
fprintf(fd, "d=\"M%g %g A%g %g 0 %d %d %g %gL%g %gz\"/>\n", xx1, yy1, rx, ry, fa, fs, xx2, yy2, cx, cy);
}
}
}
}
}
} else {
svg_xfillrectangle(gc, x1,y1,x2,y2, bus, dash, fill);
@ -340,17 +340,17 @@ static void svg_drawarc(int gc, int fillarc, double x,double y,double r,double a
if(bus > 0.0) {
fprintf(fd, " stroke-linecap:square;\n");
fprintf(fd, " stroke-linejoin:miter;\n");
}
}
if(fillarc == 0) {
fprintf(fd,"fill:none;\" ");
fprintf(fd, "d=\"M%g %g A%g %g 0 %d %d %g %g\"/>\n", xx1, yy1, rr, rr, fa, fs, xx2, yy2);
} else if(fillarc == 2) {
} else if(fillarc == 2) {
fprintf(fd, "fill-opacity:1.0;\" ");
fprintf(fd, "d=\"M%g %g A%g %g 0 %d %d %g %gL%g %gz\"/>\n", xx1, yy1, rr, rr, fa, fs, xx2, yy2, xx, yy);
} else {
fprintf(fd, "d=\"M%g %g A%g %g 0 %d %d %g %gL%g %gz\"/>\n", xx1, yy1, rr, rr, fa, fs, xx2, yy2, xx, yy);
}
}
}
}
}
}
@ -379,7 +379,7 @@ static void svg_draw_string_line(int layer, char *s, double x, double y, double
double line_delta;
double lines;
char col[20];
if(color_ps)
if(color_ps)
my_snprintf(col, S(col), "#%02x%02x%02x",
svg_colors[layer].red, svg_colors[layer].green, svg_colors[layer].blue);
else if(tclgetboolvar("dark_colorscheme"))
@ -388,16 +388,16 @@ static void svg_draw_string_line(int layer, char *s, double x, double y, double
my_snprintf(col, S(col), "#%02x%02x%02x", 0, 0, 0);
if(s==NULL) return;
if(llength==0) return;
line_delta = lineno*fontheight;
lines = (no_of_lines-1)*fontheight;
ix=X_TO_SCREEN(x);
iy=Y_TO_SCREEN(y);
if(rot&1) {
rot1=3;
} else rot1=0;
if( rot==0 && flip==0) {iy+=line_delta+fontascent;}
else if(rot==1 && flip==0) {iy+=longest_line;ix=ix-fontheight+fontascent-lines+line_delta;}
else if(rot==2 && flip==0) {iy=iy-fontheight-lines+line_delta+fontascent; ix=ix-longest_line;}
@ -406,7 +406,7 @@ static void svg_draw_string_line(int layer, char *s, double x, double y, double
else if(rot==1 && flip==1) {ix=ix-fontheight+line_delta-lines+fontascent;}
else if(rot==2 && flip==1) {iy=iy-fontheight-lines+line_delta+fontascent;}
else if(rot==3 && flip==1) {iy=iy+longest_line;ix+=line_delta+fontascent;}
fprintf(fd,"<text fill=\"%s\" xml:space=\"preserve\" font-size=\"%g\" ", col, size*xctx->mooz);
if(strcmp(svg_font_weight, "normal")) fprintf(fd, "font-weight=\"%s\" ", svg_font_weight);
if(strcmp(svg_font_style, "normal")) fprintf(fd, "font-style=\"%s\" ", svg_font_style);
@ -417,13 +417,13 @@ static void svg_draw_string_line(int layer, char *s, double x, double y, double
while(*s) {
switch(*s) {
case '<':
fputs("&lt;", fd);
fputs("&lt;", fd);
break;
case '>':
fputs("&gt;", fd);
fputs("&gt;", fd);
break;
case '&':
fputs("&amp;", fd);
fputs("&amp;", fd);
break;
default:
fputc(*s, fd);
@ -608,7 +608,7 @@ static int svg_embedded_image(xRect *r, double rx1, double ry1, double rx2, doub
/* screen position */
if(RECT_OUTSIDE(x1, y1, x2, y2,
xctx->areax1,xctx->areay1,xctx->areax2,xctx->areay2)) return 0;
if(rot == 1 || rot == 3) {
w = fabs(y2 - y1);
h = fabs(x2 - x1);
@ -629,12 +629,12 @@ static int svg_embedded_image(xRect *r, double rx1, double ry1, double rx2, doub
if(!strncmp(attr, "/9j/", 4)) jpg = 1;
else if(!strncmp(attr, "iVBOR", 5)) jpg = 0;
else if(my_memmem(buffer, buffer_size, "<svg", 4) &&
else if(my_memmem(buffer, buffer_size, "<svg", 4) &&
my_memmem(buffer, buffer_size, "xmlns", 5)) {
if(filter) {
jpg = 2; /* svg */
jpg = 2; /* svg */
}
}
}
else jpg = -1; /* some invalid data */
} else {
jpg = -1;
@ -668,7 +668,7 @@ static int svg_embedded_image(xRect *r, double rx1, double ry1, double rx2, doub
}
}
my_snprintf(transform, S(transform),
my_snprintf(transform, S(transform),
"transform=\"translate(%g,%g) rotate(%d) scale(%g,%g)\"", xorig, yorig, rot * 90, scalex, scaley);
if(alpha == 1.0) strcpy(opacity, "");
else my_snprintf(opacity, S(opacity), "style=\"opacity:%g;\"", alpha);
@ -709,7 +709,7 @@ static void svg_draw_symbol(int c, int n,int layer,short tmp_flip, short rot,
type = xctx->sym[xctx->inst[n].ptr].type;
lvs_ignore=tclgetboolvar("lvs_ignore");
if(xctx->inst[n].ptr == -1) return;
if(layer == 0) {
if(layer == 0) {
xctx->inst[n].flags &= ~IGNORE_INST; /* clear bit */
if( type && strcmp(type, "launcher") && strcmp(type, "logo") &&
strcmp(type, "probe") &&
@ -759,7 +759,7 @@ static void svg_draw_symbol(int c, int n,int layer,short tmp_flip, short rot,
}
if(hide) {
int color = (disabled==1) ? GRIDLAYER : (disabled == 2) ? PINLAYER : SYMLAYER;
svg_filledrect(color, xctx->inst[n].xx1, xctx->inst[n].yy1, xctx->inst[n].xx2, xctx->inst[n].yy2,
svg_filledrect(color, xctx->inst[n].xx1, xctx->inst[n].yy1, xctx->inst[n].xx2, xctx->inst[n].yy2,
0.0, 2, 0, -1, -1);
}
}
@ -874,7 +874,7 @@ static void svg_draw_symbol(int c, int n,int layer,short tmp_flip, short rot,
for(j=0;j< symptr->texts; ++j) {
double xscale, yscale;
get_sym_text_size(n, j, &xscale, &yscale);
text = symptr->text[j];
/* if(xscale*FONTWIDTH* xctx->mooz<1) continue; */
@ -884,7 +884,7 @@ static void svg_draw_symbol(int c, int n,int layer,short tmp_flip, short rot,
ROTATION(rot, flip, 0.0,0.0,text.x0,text.y0,x1,y1);
textlayer = c_for_text;
/* do not allow custom text color on hilighted instances */
if(disabled == 1) textlayer = GRIDLAYER;
if(disabled == 1) textlayer = GRIDLAYER;
else if(disabled == 2) textlayer = PINLAYER;
else if( xctx->inst[n].color == -10000) {
int lay;
@ -909,7 +909,7 @@ static void svg_draw_symbol(int c, int n,int layer,short tmp_flip, short rot,
my_snprintf(svg_font_style, S(svg_font_style), "italic");
if( symptr->text[j].flags & TEXT_OBLIQUE)
my_snprintf(svg_font_style, S(svg_font_style), "oblique");
if(text_svg)
if(text_svg)
svg_draw_string(textlayer, txtptr,
(text.rot + ( (flip && (text.rot & 1) ) ? rot+2 : rot) ) & 0x3,
flip^text.flip, text.hcenter, text.vcenter,
@ -1007,16 +1007,16 @@ void svg_draw(void)
dx=xctx->xrect[0].width;
dy=xctx->xrect[0].height;
dbg(1, "svg_draw(): dx=%g dy=%g\n", dx, dy);
if(xctx->plotfile[0]) {
fd=fopen(xctx->plotfile, "w");
if(!fd) {
if(!fd) {
dbg(0, "can not open file: %s\n", xctx->plotfile);
return;
}
} else {
fd=fopen("plot.svg", "w");
if(!fd) {
if(!fd) {
dbg(0, "can not open file: %s\n", "plot.svg");
return;
}
@ -1070,14 +1070,14 @@ void svg_draw(void)
fprintf(fd, "<svg xmlns=\"http://www.w3.org/2000/svg\""
" xmlns:xlink=\"http://www.w3.org/1999/xlink\""
" width=\"%g\" height=\"%g\" version=\"1.1\">\n", dx, dy);
fprintf(fd, "<style type=\"text/css\">\n"); /* use css stylesheet 20121119 */
/* fill_pattern:
* 0 : no fill
* 1 : stippled fill
* 2 : solid fill
* fill_type[i]:
* fill_type[i]:
* 0 : no fill
* 1 : patterned (stippled) fill
* 2 : solid fill
@ -1085,15 +1085,15 @@ void svg_draw(void)
for(i=0;i<cadlayers; ++i){
if(unused_layer[i]) continue;
fprintf(fd, ".l%d{\n", i);
if( xctx->fill_pattern == 0 || xctx->fill_type[i] == 0)
fprintf(fd, " fill: #%02x%02x%02x; fill-opacity: 0.2;\n",
if( xctx->fill_pattern == 0 || xctx->fill_type[i] == 0)
fprintf(fd, " fill: #%02x%02x%02x; fill-opacity: 0.2;\n",
svg_colors[i].red, svg_colors[i].green, svg_colors[i].blue);
else if( xctx->fill_pattern == 2 && xctx->fill_type[i])
else if( xctx->fill_pattern == 2 && xctx->fill_type[i])
fprintf(fd, " fill: #%02x%02x%02x;\n", svg_colors[i].red, svg_colors[i].green, svg_colors[i].blue);
else if( xctx->fill_pattern && xctx->fill_type[i] == 2)
else if( xctx->fill_pattern && xctx->fill_type[i] == 2)
fprintf(fd, " fill: #%02x%02x%02x;\n", svg_colors[i].red, svg_colors[i].green, svg_colors[i].blue);
else
fprintf(fd, " fill: #%02x%02x%02x; fill-opacity: 0.5;\n",
else
fprintf(fd, " fill: #%02x%02x%02x; fill-opacity: 0.5;\n",
svg_colors[i].red, svg_colors[i].green, svg_colors[i].blue);
fprintf(fd, " stroke: #%02x%02x%02x;\n", svg_colors[i].red, svg_colors[i].green, svg_colors[i].blue);
fprintf(fd, " stroke-linecap:round;\n");
@ -1105,10 +1105,10 @@ void svg_draw(void)
}
fprintf(fd, "}\n");
}
fprintf(fd, "text {font-family: %s;}\n", tclgetvar("svg_font_name"));
fprintf(fd, "</style>\n");
/* background */
fprintf(fd, "<rect class=\"l0\" x=\"%g\" y=\"%g\" width=\"%g\" height=\"%g\"/>\n", 0.0, 0.0, dx, dy);
svg_drawgrid();
@ -1167,7 +1167,7 @@ void svg_draw(void)
if(xctx->hilight_nets && (entry=bus_hilight_hash_lookup( xctx->wire[i].node, 0, XLOOKUP))) {
color = get_color(entry->value);
}
svg_drawline(color, xctx->wire[i].bus, xctx->wire[i].x1,
svg_drawline(color, xctx->wire[i].bus, xctx->wire[i].x1,
xctx->wire[i].y1,xctx->wire[i].x2,xctx->wire[i].y2, 0);
}
@ -1215,8 +1215,8 @@ void svg_draw(void)
my_snprintf(svg_font_style, S(svg_font_style), "italic");
if( xctx->text[i].flags & TEXT_OBLIQUE)
my_snprintf(svg_font_style, S(svg_font_style), "oblique");
if(text_svg)
if(text_svg)
svg_draw_string(textlayer, get_text_floater(i),
xctx->text[i].rot, xctx->text[i].flip, xctx->text[i].hcenter, xctx->text[i].vcenter,
xctx->text[i].x0,xctx->text[i].y0,

32
src/symgen.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
#
# File: symgen.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -106,7 +106,7 @@ start_labels == 1 {
next
}
/^\./{
/^\./{
if(/^\.bus/) {
if( !horizontal || (pos == 0 || pos == 2) ) {
bus = 1
@ -164,7 +164,7 @@ start_pin {
delta1 = delta2 = pinspacing / 2
}
}
coord += delta1
pin[pos, n, "coord"] = round(coord)
dbg("pin[" pos ", " n ", coord]: " pin[pos, n, "coord"] " pinname: " \
@ -181,12 +181,12 @@ start_pin {
END{
header()
attrs(attributes)
if(horizontal !=1) {
firstpinyoffset = round(pintextoffset + pincharspacing * pin[1, "maxlength"])
lastpinyoffset = round(pintextoffset + pincharspacing * pin[3, "maxlength"])
}
dbg("pin[1, maxlength]: " pin[1, "maxlength"])
dbg("pin[3, maxlength]: " pin[3, "maxlength"])
dbg("firstpinyoffset: " firstpinyoffset)
@ -218,19 +218,19 @@ END{
for(n = 0; n < pin[p,"n"]; n++) {
dir = pin[p, n, "dir"]
plinelay = (dir =="in") ? 4 : (dir == "inout") ? 3 : 2
if(p == 0 ) {
if(p == 0 ) {
x = symbolx1 - pinlinelength
y = symboly1 + pin[p, n, "coord"] + firstpinyoffset
}
else if(p == 1 ) {
else if(p == 1 ) {
x = symbolx1 + pin[p, n, "coord"]
y = symboly1 - pinlinelength
}
else if(p == 2 ) {
else if(p == 2 ) {
x = symbolx2 + pinlinelength
y = symboly1 + pin[p, n, "coord"] + firstpinyoffset
}
else if(p == 3 ) {
else if(p == 3 ) {
x = symbolx1 + pin[p, n, "coord"]
y = symboly2 + pinlinelength
}
@ -327,7 +327,7 @@ END{
laby = (symboly1 + symboly2) / 2 + ( l - label["n"] / 2 ) * labelspacing + labelcenteroffset
text(label[l], labx, laby, 0, 0, labeltextsize, "hcenter=1")
}
}
}
function dbg(s)
{
@ -360,7 +360,7 @@ function trigger(x, y, layer, pos)
}
function pinnumber_id(pinseq)
function pinnumber_id(pinseq)
{
return("@#" pinseq ":pinnumber")
}

24
src/tedax.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#!/usr/bin/awk -f
#
# File: tedax.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -30,14 +30,14 @@ BEGIN{
# conn U1:2 INPUT_A A 1:4:9:12 1
/^[ \t]*#/{ print; next}
/^begin netlist/{
/^begin netlist/{
print
next
}
/^begin_inst .* numslots/{
/^begin_inst .* numslots/{
reparse()
numslots=$4;
numslots=$4;
if(numslots ==0) numslots = 1
next
}
@ -78,7 +78,7 @@ $1=="device"||$1=="footprint"{
}
next
}
# conn U1 Tx2In Tx2\ In 10 10
/^conn/{
reparse()
@ -137,7 +137,7 @@ $1=="device"||$1=="footprint"{
print "pinname", i_arr[1], i_arr[2], n_arr[3]
}
}
for(ii = 0; ii < footprint_n; ii++) { # used to preserve ordering
i = footprint_num[ii]
print "footprint", i, footprint[i]
@ -157,7 +157,7 @@ $1=="device"||$1=="footprint"{
delete device
delete device_num # used to preserve ordering
device_n = 0
next
}

4
src/tedax_netlist.c
View File

@ -150,7 +150,7 @@ int global_tedax_netlist(int global, int alert) /* netlister driver */
bus_char[1] = str_tmp[1];
}
xctx->netlist_count=0;
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
tclgetvar("netlist_dir"), get_cell(xctx->sch[xctx->currsch], 0), getpid());
fd=fopen(netl_filename, "w");
if(fd==NULL){
@ -197,7 +197,7 @@ int global_tedax_netlist(int global, int alert) /* netlister driver */
{
int saved_hilight_nets = xctx->hilight_nets;
int web_url = is_from_web(xctx->current_dirname);
char *current_dirname_save = NULL;
char *current_dirname_save = NULL;
unselect_all(1);
/* ensure all unused symbols purged before descending hierarchy */

246
src/token.c
View File

@ -47,12 +47,12 @@ void floater_hash_all_names(void)
int i;
int_hash_free(&xctx->floater_inst_table);
int_hash_init(&xctx->floater_inst_table, HASHSIZE);
for(i=0; i<xctx->instances; ++i) {
for(i=0; i<xctx->instances; ++i) {
if(xctx->inst[i].instname && xctx->inst[i].instname[0]) {
int_hash_lookup(&xctx->floater_inst_table, xctx->inst[i].instname, i, XINSERT);
}
}
}
}
/* if cmd is wrapped inside tcleval(...) pass the content to tcl
* for evaluation, return tcl result. If no tcleval(...) found return copy of cmd */
@ -82,8 +82,8 @@ int is_generator(const char *name)
{
#ifdef __unix__
int res = 0;
static regex_t *re = NULL;
static regex_t *re = NULL;
if(!name) {
if(re) {
regfree(re);
@ -112,7 +112,7 @@ int is_generator(const char *name)
}
/* cleanup syntax of symbol generators: xxx(a,b,c) --> xxx_a_b_c */
const char *sanitize(const char *name)
const char *sanitize(const char *name)
{
static char *s = NULL;
static char *empty="";
@ -182,7 +182,7 @@ char *get_generator_command(const char *str)
int match_symbol(const char *name) /* never returns -1, if symbol not found load systemlib/missing.sym */
{
int i,found;
found=0;
dbg(1, "match_symbol(): name=%s\n", name);
for(i=0;i<xctx->symbols; ++i) {
@ -360,32 +360,32 @@ const char *list_tokens(const char *s, int with_quotes)
}
static int get_sym_pin_number(int sym, const char *pin_name)
{
{
int n = -1;
if(isonlydigit(pin_name)) {
n = atoi(pin_name);
}
}
else if(pin_name[0]) {
for(n = 0 ; n < xctx->sym[sym].rects[PINLAYER]; ++n) {
char *prop = xctx->sym[sym].rect[PINLAYER][n].prop_ptr;
if(!strcmp(get_tok_value(prop,"name",0), pin_name)) break;
}
}
}
}
return n;
}
}
int get_inst_pin_number(int inst, const char *pin_name)
{
int n = -1;
if(isonlydigit(pin_name)) {
n = atoi(pin_name);
}
}
else if(pin_name[0] && xctx->inst[inst].ptr >= 0) {
for(n = 0 ; n < (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER]; ++n) {
char *prop = (xctx->inst[inst].ptr + xctx->sym)->rect[PINLAYER][n].prop_ptr;
if(!strcmp(get_tok_value(prop,"name",0), pin_name)) break;
}
}
}
}
return n;
}
@ -416,7 +416,7 @@ static void get_pin_and_attr(const char *token, char **pin_num_or_name, char **p
my_strdup2(_ALLOC_ID_, pin_attr, "");
}
dbg(1, "get_pin_and_attr(): token=%s, name=%s, attr=%s\n", token,
*pin_num_or_name ? *pin_num_or_name : "<NULL>",
*pin_num_or_name ? *pin_num_or_name : "<NULL>",
*pin_attr ? *pin_attr: "<NULL>");
}
@ -449,7 +449,7 @@ const char *get_tok_value(const char *s,const char *tok, int with_quotes)
static char *translated_tok = NULL;
xctx->tok_size = 0;
if(s==NULL) {
if(tok == NULL) {
my_free(_ALLOC_ID_, &result);
@ -624,7 +624,7 @@ const char *get_sym_template(char *s,char *extra)
}
/* caller is responsible for freeing up storage for return value
* return NULL if no matching token found
* return NULL if no matching token found
* caller is responsible for freeing up storage for pin_attr_value */
static char *get_pin_attr_from_inst(int inst, int pin, const char *attr)
{
@ -715,7 +715,7 @@ void hash_names(int inst, int action)
/* return -1 if name is not used, else return first instance number with same name found
* old_basename: base name (without [...]) of instance name the new 'name' was built from
* brkt: pointer to '[...]' part of instance name (or empty string if no [...] found)
* q: integer number added to 'name' when trying an unused instance name
* q: integer number added to 'name' when trying an unused instance name
* (name = old_basename + q + bracket)
* or -1 if only testing for unique 'name'.
*/
@ -767,14 +767,14 @@ void new_prop_string(int i, const char *old_prop, int dis_uniq_names)
char *old_name_base = NULL;
char *up_new_name = NULL;
int is_used;
dbg(1, "new_prop_string(): i=%d, old_prop=%s\n", i, old_prop);
if(old_prop==NULL) {
my_free(_ALLOC_ID_, &xctx->inst[i].prop_ptr);
return;
}
old_name_len = my_strdup(_ALLOC_ID_, &old_name,get_tok_value(old_prop,"name",0) ); /* added old_name_len */
if(old_name==NULL) {
my_strdup(_ALLOC_ID_, &xctx->inst[i].prop_ptr, old_prop); /* changed to copy old props if no name */
my_strdup2(_ALLOC_ID_, &xctx->inst[i].instname, "");
@ -795,13 +795,13 @@ void new_prop_string(int i, const char *old_prop, int dis_uniq_names)
if(!n) old_name_base[0] = '\0'; /* there is no basename (like in "[3:0]" or "12"), set to empty string */
brkt=find_bracket(old_name); /* if no bracket found will point to end of string ('\0') */
my_realloc(_ALLOC_ID_, &new_name, old_name_len + 40);
qq = get_last_used_index(old_name_base, brkt); /* */
for(q = qq;; ++q) {
my_snprintf(new_name, old_name_len + 40, "%s%d%s", old_name_base, q, brkt);
is_used = name_is_used(new_name, old_name_base, brkt, q);
if(is_used == -1 ) break;
if(is_used == -1 ) break;
}
my_free(_ALLOC_ID_, &old_name_base);
dbg(1, "new_prop_string(): new_name=%s\n", new_name);
@ -958,10 +958,10 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
if(!xctx->tok_size)
my_strdup(_ALLOC_ID_, &format, get_tok_value(xctx->sym[xctx->inst[inst].ptr].prop_ptr, fmt_attr, 2));
/* allow format string override in instance */
if(xctx->tok_size && strcmp(fmt_attr, "vhdl_format"))
if(xctx->tok_size && strcmp(fmt_attr, "vhdl_format"))
my_strdup(_ALLOC_ID_, &format, get_tok_value(xctx->inst[inst].prop_ptr, "vhdl_format", 2));
/* get netlist format rule from symbol */
if(!xctx->tok_size && strcmp(fmt_attr, "vhdl_format"))
if(!xctx->tok_size && strcmp(fmt_attr, "vhdl_format"))
my_strdup(_ALLOC_ID_, &format, get_tok_value(xctx->sym[xctx->inst[inst].ptr].prop_ptr, "vhdl_format", 2));
if((name==NULL) || (format==NULL) ) {
my_free(_ALLOC_ID_, &template);
@ -1042,7 +1042,7 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
const char *s = sanitize(translate(inst, get_sym_name(inst, 0, 0, 0)));
my_mstrcat(_ALLOC_ID_, &result, s, NULL);
}
else if (strcmp(token,"@symname_ext")==0)
else if (strcmp(token,"@symname_ext")==0)
{
const char *s = sanitize(translate(inst, get_sym_name(inst, 0, 1, 0)));
my_mstrcat(_ALLOC_ID_, &result, s, NULL);
@ -1096,7 +1096,7 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
}
}
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
* @#0, @#1:net_name, @#2:name, ... */
else if(token[0]=='@' && token[1]=='#') {
int n;
@ -1197,7 +1197,7 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
* can be calculated. Before that do also a round of translation to remove remaining @params */
if(result) {
dbg(1, "print_vhdl_primitive(): before translate3() result=%s\n", result);
if(strchr(result, '@')) {
if(strchr(result, '@')) {
/* netlist_commands often have @ characters due to ngspice syntax. Do not translate */
if(strcmp(xctx->sym[xctx->inst[inst].ptr].type, "netlist_commands")) {
my_strdup2(_ALLOC_ID_, &result,
@ -1205,18 +1205,18 @@ static void print_vhdl_primitive(FILE *fd, int inst) /* netlist primitives, 200
/* can not put template in above translate3: -----------------------^^^^
* if instance has VHI=VHI, format string has VHI=@VHI, and symbol template has VHI=3
* we do not want token @VHI to resolve to 3, but stop at VHI as specified in instance */
if(strchr(result, '@')) {
if(strchr(result, '@')) {
my_strdup2(_ALLOC_ID_, &result,
translate3(result, 0, xctx->inst[inst].prop_ptr, parent_prop_ptr, template, NULL));
}
}
}
}
my_strdup2(_ALLOC_ID_, &result, tcl_hook2(result)); /* tcl evaluation if tcleval(....) */
if(is_expr(result)) {
my_strdup2(_ALLOC_ID_, &result, eval_expr(result));
}
dbg(1, "print_vhdl_primitive(): after translate3() result=%s\n", result);
}
}
if(result) fprintf(fd, "%s", result);
fputc('\n',fd);
fprintf(fd, "---- end primitive\n");
@ -1417,7 +1417,7 @@ const char *get_trailing_path(const char *str, int no_of_dir, int skip_ext)
size_t ext_pos, dir_pos;
int n_ext, n_dir, c, i, generator = 0;
if(str == NULL) return NULL;
if(str == NULL) return NULL;
my_strncpy(s, str, S(s));
len = strlen(s);
@ -1750,7 +1750,7 @@ void print_generic(FILE *fd, char *ent_or_comp, int symbol)
{
my_strdup(_ALLOC_ID_, &generic_type,
get_tok_value(xctx->sym[symbol].rect[GENERICLAYER][i].prop_ptr,"generic_type",0));
my_strdup(_ALLOC_ID_, &generic_value,
my_strdup(_ALLOC_ID_, &generic_value,
get_tok_value(xctx->sym[symbol].rect[GENERICLAYER][i].prop_ptr,"value", 0) );
str_tmp = get_tok_value(xctx->sym[symbol].rect[GENERICLAYER][i].prop_ptr,"name",0);
if(!tmp) fprintf(fd, "generic (\n");
@ -1879,7 +1879,7 @@ void print_tedax_subckt(FILE *fd, int symbol)
}
/* This function is used to generate the @pinlist replacement getting port order
* from the spice_sym_def attribute (either directly or by loading the provided .include file),
* from the spice_sym_def attribute (either directly or by loading the provided .include file),
* checking with the corresponding symbol pin name and getting the net name attached to it.
* Any name mismatch is reported, in this case the function does nothing and the default xschem
* symbol port ordering will be used. */
@ -1904,7 +1904,7 @@ static int has_included_subcircuit(int inst, int symbol, char **result)
char *net, *net_save;
Str_hashentry *entry;
Str_hashtable table = {NULL, 0};
my_strdup2(_ALLOC_ID_, &symname, get_tok_value(xctx->inst[inst].prop_ptr, "schematic", 0));
if(!symname[0]) {
my_strdup2(_ALLOC_ID_, &symname, get_tok_value(xctx->sym[symbol].prop_ptr, "schematic", 0));
@ -1990,7 +1990,7 @@ static int has_included_subcircuit(int inst, int symbol, char **result)
dbg(0, "has_included_subcircuit(): %s symbol and .subckt pins do not match. Discard port order\n",
symname);
if(has_x)
tclvareval("alert_ {has_included_subcircuit(): ", symname,
tclvareval("alert_ {has_included_subcircuit(): ", symname,
" symbol and .subckt pins do not match. Discard .subckt port order}", NULL);
}
if(tmp_result) my_free(_ALLOC_ID_, &tmp_result);
@ -2128,7 +2128,7 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
}
my_free(_ALLOC_ID_, &pin_attr);
my_free(_ALLOC_ID_, &pin_num_or_name);
}
/* this will print the other @parameters, usually "extra" nodes so they will be in the order
* specified by the format string. The 'extra' attribute is no more used to print extra nodes
@ -2140,7 +2140,7 @@ void print_spice_subckt_nodes(FILE *fd, int symbol)
my_mstrcat(_ALLOC_ID_, &result, token + 1, " ", NULL);
}
}
/* if(c!='%' && c!='@' && c!='\0' ) fputc(c,fd); */
/* if(c!='%' && c!='@' && c!='\0' ) fputc(c,fd); */
if(c == '@' || c =='%') s--;
state=TOK_BEGIN;
}
@ -2289,7 +2289,7 @@ void print_spectre_subckt_nodes(FILE *fd, int symbol)
}
my_free(_ALLOC_ID_, &pin_attr);
my_free(_ALLOC_ID_, &pin_num_or_name);
}
/* this will print the other @parameters, usually "extra" nodes so they will be in the order
* specified by the format string. The 'extra' attribute is no more used to print extra nodes
@ -2301,7 +2301,7 @@ void print_spectre_subckt_nodes(FILE *fd, int symbol)
my_mstrcat(_ALLOC_ID_, &result, token + 1, " ", NULL);
}
}
/* if(c!='%' && c!='@' && c!='\0' ) fputc(c,fd); */
/* if(c!='%' && c!='@' && c!='\0' ) fputc(c,fd); */
if(c == '@' || c =='%') s--;
state=TOK_BEGIN;
}
@ -2349,7 +2349,7 @@ int print_spice_element(FILE *fd, int inst)
const char *str_ptr=NULL;
register int c, state=TOK_BEGIN, space;
char *template=NULL,*format=NULL, *s, *name=NULL, *token=NULL;
const char *lab;
const char *lab;
const char *value = NULL;
/* char *translatedvalue = NULL; */
size_t sizetok=0;
@ -2358,7 +2358,7 @@ int print_spice_element(FILE *fd, int inst)
int no_of_pins=0;
char *result = NULL;
size_t size = 0;
char *spiceprefixtag = NULL;
char *spiceprefixtag = NULL;
const char *fmt_attr = NULL;
size = CADCHUNKALLOC;
@ -2425,7 +2425,7 @@ int print_spice_element(FILE *fd, int inst)
token[token_pos]='\0';
token_pos=0;
if(strcmp(token,"@symref")==0)
if(strcmp(token,"@symref")==0)
{
const char *s = get_sym_name(inst, 9999, 1, 0);
my_mstrcat(_ALLOC_ID_, &result, s, NULL);
@ -2479,7 +2479,7 @@ int print_spice_element(FILE *fd, int inst)
if(!spice_ignore) {
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
str_ptr = net_name(inst, i, &multip, 0, 1);
my_mstrcat(_ALLOC_ID_, &result, "?", my_itoa(multip), " ", str_ptr, " ", NULL);
}
}
@ -2500,13 +2500,13 @@ int print_spice_element(FILE *fd, int inst)
}
}
}
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
* @#0, @#1:net_name, @#2:name, ... */
else if(token[0]=='@' && token[1]=='#') {
int n;
char *pin_attr = NULL;
char *pin_num_or_name = NULL;
get_pin_and_attr(token, &pin_num_or_name, &pin_attr);
n = get_inst_pin_number(inst, pin_num_or_name);
if(n>=0 && pin_attr[0] && n < (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER]) {
@ -2604,16 +2604,16 @@ int print_spice_element(FILE *fd, int inst)
* passgate.sch:
* instance of nmos.sym: L=L_N W=W_N nf=1 m=1 model=@modeln
* nmos.sym:
* format="@name @pinlist @model L=@L W=@W nf=@nf
* format="@name @pinlist @model L=@L W=@W nf=@nf
* + ad=@ad as=@as pd=@pd .... m=@m
* template="name=M1 W=1 L=0.15 m=1
* template="name=M1 W=1 L=0.15 m=1
* ad=\"expr('int((@nf + 1)/2) * @W / @nf * 0.29')\"
* ..."
* model=nfet_01v8
*/
my_strdup2(_ALLOC_ID_, &val,
my_strdup2(_ALLOC_ID_, &val,
translate3(token, 0, xctx->inst[inst].prop_ptr, NULL, NULL, NULL));
/* can not put template in above translate3: ---------------------------^^^^
* if instance has VHI=VHI, format string has VHI=@VHI, and symbol template has VHI=3
@ -2681,7 +2681,7 @@ int print_spice_element(FILE *fd, int inst)
if (!(strcmp(token+1,"name") && strcmp(token+1,"lab")) /* expand name/labels */
&& ((lab = expandlabel(value, &itmp)) != NULL)) {
my_mstrcat(_ALLOC_ID_, &result, lab, NULL);
} else {
} else {
my_mstrcat(_ALLOC_ID_, &result, value, NULL);
}
}
@ -2743,7 +2743,7 @@ int print_spectre_element(FILE *fd, int inst)
const char *str_ptr=NULL;
register int c, state=TOK_BEGIN, space;
char *template=NULL,*format=NULL, *s, *name=NULL, *token=NULL;
const char *lab;
const char *lab;
const char *value = NULL;
/* char *translatedvalue = NULL; */
size_t sizetok=0;
@ -2752,7 +2752,7 @@ int print_spectre_element(FILE *fd, int inst)
int no_of_pins=0;
char *result = NULL;
size_t size = 0;
char *spiceprefixtag = NULL;
char *spiceprefixtag = NULL;
const char *fmt_attr = NULL;
size = CADCHUNKALLOC;
@ -2819,7 +2819,7 @@ int print_spectre_element(FILE *fd, int inst)
token[token_pos]='\0';
token_pos=0;
if(strcmp(token,"@symref")==0)
if(strcmp(token,"@symref")==0)
{
const char *s = get_sym_name(inst, 9999, 1, 0);
my_mstrcat(_ALLOC_ID_, &result, s, NULL);
@ -2872,7 +2872,7 @@ int print_spectre_element(FILE *fd, int inst)
if(!spectre_ignore) {
if(!int_hash_lookup(&table, name, 1, XINSERT_NOREPLACE)) {
str_ptr = net_name(inst, i, &multip, 0, 1);
my_mstrcat(_ALLOC_ID_, &result, "?", my_itoa(multip), " ", str_ptr, " ", NULL);
}
}
@ -2892,13 +2892,13 @@ int print_spectre_element(FILE *fd, int inst)
}
}
}
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
* @#0, @#1:net_name, @#2:name, ... */
else if(token[0]=='@' && token[1]=='#') {
int n;
char *pin_attr = NULL;
char *pin_num_or_name = NULL;
get_pin_and_attr(token, &pin_num_or_name, &pin_attr);
n = get_inst_pin_number(inst, pin_num_or_name);
if(n>=0 && pin_attr[0] && n < (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER]) {
@ -2996,16 +2996,16 @@ int print_spectre_element(FILE *fd, int inst)
* passgate.sch:
* instance of nmos.sym: L=L_N W=W_N nf=1 m=1 model=@modeln
* nmos.sym:
* format="@name @pinlist @model L=@L W=@W nf=@nf
* format="@name @pinlist @model L=@L W=@W nf=@nf
* + ad=@ad as=@as pd=@pd .... m=@m
* template="name=M1 W=1 L=0.15 m=1
* template="name=M1 W=1 L=0.15 m=1
* ad=\"expr('int((@nf + 1)/2) * @W / @nf * 0.29')\"
* ..."
* model=nfet_01v8
*/
my_strdup2(_ALLOC_ID_, &val,
my_strdup2(_ALLOC_ID_, &val,
translate3(token, 0, xctx->inst[inst].prop_ptr, NULL, NULL, NULL));
/* can not put template in above translate3: ---------------------------^^^^
* if instance has VHI=VHI, format string has VHI=@VHI, and symbol template has VHI=3
@ -3073,7 +3073,7 @@ int print_spectre_element(FILE *fd, int inst)
if (!(strcmp(token+1,"name") && strcmp(token+1,"lab")) /* expand name/labels */
&& ((lab = expandlabel(value, &itmp)) != NULL)) {
my_mstrcat(_ALLOC_ID_, &result, lab, NULL);
} else {
} else {
my_mstrcat(_ALLOC_ID_, &result, value, NULL);
}
}
@ -3145,7 +3145,7 @@ void print_tedax_element(FILE *fd, int inst)
const char *tmp;
int instance_based=0;
size_t sizetok=0;
size_t token_pos=0;
size_t token_pos=0;
int escape=0;
int no_of_pins=0;
int subcircuit = 0;
@ -3186,7 +3186,7 @@ void print_tedax_element(FILE *fd, int inst)
int_hash_init(&table, 37);
for(i=0;i<no_of_pins; ++i) {
my_strdup2(_ALLOC_ID_, &net, net_name(inst,i, &net_mult, 0, 1));
my_strdup2(_ALLOC_ID_, &pinname,
my_strdup2(_ALLOC_ID_, &pinname,
get_tok_value(xctx->sym[xctx->inst[inst].ptr].rect[PINLAYER][i].prop_ptr,"name",0));
my_strdup2(_ALLOC_ID_, &pin, expandlabel(pinname, &pin_mult));
if(!int_hash_lookup(&table, pinname, 1, XINSERT_NOREPLACE)) {
@ -3194,8 +3194,8 @@ void print_tedax_element(FILE *fd, int inst)
for(n = 0; n < net_mult; ++n) {
my_strdup(_ALLOC_ID_, &netbit, find_nth(net, ",", "", 0, n+1));
my_strdup(_ALLOC_ID_, &pinbit, find_nth(pin, ",", "", 0, n+1));
fprintf(fd, "__map__ %s -> %s\n",
pinbit ? pinbit : "__UNCONNECTED_PIN__",
fprintf(fd, "__map__ %s -> %s\n",
pinbit ? pinbit : "__UNCONNECTED_PIN__",
netbit ? netbit : "__UNCONNECTED_PIN__");
}
}
@ -3240,7 +3240,7 @@ void print_tedax_element(FILE *fd, int inst)
}
my_free(_ALLOC_ID_, &pinnumber);
}
if(extra){
char netstring[40];
/* fprintf(errfp, "extra_pinnumber: |%s|\n", extra_pinnumber); */
@ -3252,7 +3252,7 @@ void print_tedax_element(FILE *fd, int inst)
/* fprintf(errfp, "extra_pinnumber_token: |%s|\n", extra_pinnumber_token); */
/* fprintf(errfp, "extra_token: |%s|\n", extra_token); */
instance_based=0;
/* alternate instance based extra net naming: net:<pinumber>=netname */
my_snprintf(netstring, S(netstring), "net:%s", extra_pinnumber_token);
dbg(1, "print_tedax_element(): netstring=%s\n", netstring);
@ -3261,7 +3261,7 @@ void print_tedax_element(FILE *fd, int inst)
if(!extra_token_val[0]) extra_token_val=get_tok_value(template, extra_token, 0);
else instance_based=1;
if(!extra_token_val[0]) extra_token_val="--UNDEF--";
fprintf(fd, "conn %s %s %s %s %d", name, extra_token_val, extra_token, extra_pinnumber_token, i+1);
++i;
if(instance_based) fprintf(fd, " # instance_based");
@ -3323,7 +3323,7 @@ void print_tedax_element(FILE *fd, int inst)
const char *s = sanitize(translate(inst, get_sym_name(inst, 0, 0, 0)));
fputs(s, fd);
}
else if (strcmp(token,"@symname_ext")==0)
else if (strcmp(token,"@symname_ext")==0)
{
const char *s = sanitize(translate(inst, get_sym_name(inst, 0, 1, 0)));
fputs(s, fd);
@ -3381,7 +3381,7 @@ void print_tedax_element(FILE *fd, int inst)
int n;
char *pin_attr = NULL;
char *pin_num_or_name = NULL;
get_pin_and_attr(token, &pin_num_or_name, &pin_attr);
n = get_inst_pin_number(inst, pin_num_or_name);
if(n>=0 && pin_attr[0] && n < (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER]) {
@ -3534,10 +3534,10 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
if( state==TOK_BEGIN && (c=='@' || c=='%') && !escape ) state=TOK_TOKEN;
else if(state==TOK_TOKEN && token_pos > 1 &&
(
( (space || c == '%' || c == '@') && !escape ) ||
( (space || c == '%' || c == '@') && !escape ) ||
( (!space && c != '%' && c != '@') && escape )
)
) {
) {
state=TOK_SEP;
}
@ -3585,7 +3585,7 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
const char *s = sanitize(translate(inst, get_sym_name(inst, 0, 0, 0)));
my_mstrcat(_ALLOC_ID_, &result, s, NULL);
}
else if (strcmp(token,"@symname_ext")==0)
else if (strcmp(token,"@symname_ext")==0)
{
const char *s = sanitize(translate(inst, get_sym_name(inst, 0, 1, 0)));
my_mstrcat(_ALLOC_ID_, &result, s, NULL);
@ -3636,13 +3636,13 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
}
}
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
/* reference by pin number instead of pin name, allows faster lookup of the attached net name
* @#0, @#1:net_name, @#2:name, ... */
else if(token[0]=='@' && token[1]=='#') {
int n;
char *pin_attr = NULL;
char *pin_num_or_name = NULL;
get_pin_and_attr(token, &pin_num_or_name, &pin_attr);
n = get_inst_pin_number(inst, pin_num_or_name);
if(n>=0 && pin_attr[0] && n < (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER]) {
@ -3727,16 +3727,16 @@ static void print_verilog_primitive(FILE *fd, int inst) /* netlist switch level
if(c=='\0')
{
char *parent_prop_ptr = NULL;
if(xctx->currsch > 0) {
parent_prop_ptr = xctx->hier_attr[xctx->currsch - 1].prop_ptr;
}
}
/* if result is like: 'tcleval(some_string)' pass it thru tcl evaluation so expressions
* can be calculated. Before that do also a round of translation to remove remaining @params */
if(result) {
dbg(1, "print_verilog_primitive(): before translate3() result=%s\n", result);
if(strchr(result, '@')) {
if(strchr(result, '@')) {
/* netlist_commands often have @ characters due to ngspice syntax. Do not translate */
if(strcmp(xctx->sym[xctx->inst[inst].ptr].type, "netlist_commands")) {
my_strdup2(_ALLOC_ID_, &result,
@ -3831,7 +3831,7 @@ void print_verilog_element(FILE *fd, int inst)
my_strdup(_ALLOC_ID_, &v_extra, get_tok_value(xctx->sym[xctx->inst[inst].ptr].prop_ptr, "verilog_extra", 0));
/* extra is the list of attributes NOT to consider as instance parameters */
my_strdup(_ALLOC_ID_, &extra, get_tok_value(xctx->sym[xctx->inst[inst].ptr].prop_ptr, "extra", 0));
my_strdup(_ALLOC_ID_, &verilogprefix,
my_strdup(_ALLOC_ID_, &verilogprefix,
get_tok_value(xctx->sym[xctx->inst[inst].ptr].prop_ptr, "verilogprefix", 0));
if(verilogprefix) {
my_strdup(_ALLOC_ID_, &symname, verilogprefix);
@ -3984,8 +3984,8 @@ const char *net_name(int i, int j, int *multip, int hash_prefix_unnamed_net, int
char *pinname = NULL;
/* if merging a ngspice_probe.sym element it contains a @@p token,
* so translate calls net_name, but we are placing the merged objects,
/* if merging a ngspice_probe.sym element it contains a @@p token,
* so translate calls net_name, but we are placing the merged objects,
* no net name is assigned yet */
if(!xctx->inst[i].node) {
return expandlabel("", multip);
@ -4019,7 +4019,7 @@ const char *net_name(int i, int j, int *multip, int hash_prefix_unnamed_net, int
xctx->hilight_nets=1;
}
}
if(*multip <= 1)
if(*multip <= 1)
my_snprintf(unconn, S(unconn), "__UNCONNECTED_PIN__%d", xctx->netlist_unconn_cnt++);
else
my_snprintf(unconn, S(unconn), "__UNCONNECTED_PIN__%d_[%d..0]", xctx->netlist_unconn_cnt++, *multip - 1);
@ -4116,7 +4116,7 @@ char *trim_chars(const char *str, const char *sep)
}
/* find nth field in str separated by sep. 1st field is position 1
* separators inside quotes are not considered as field separators
* separators inside quotes are not considered as field separators
* if keep_quote == 1 keep quoting characters and backslashes in returned field
* if keep_quote == 4 same as above but remove surrounding "..."
* find_nth("aaa,bbb,ccc,ddd", ",", 0, 2) --> bbb
@ -4293,7 +4293,7 @@ static char *get_pin_attr(const char *token, int inst, int engineering)
size_t tmp;
prepare_netlist_structs(0);
str_ptr = net_name(inst,n, &multip, 0, 1);
tmp = strlen(str_ptr) +100 ; /* always make room for some extra chars
tmp = strlen(str_ptr) +100 ; /* always make room for some extra chars
* so 1-char writes to result do not need reallocs */
value = my_malloc(_ALLOC_ID_, tmp);
@ -4305,16 +4305,16 @@ static char *get_pin_attr(const char *token, int inst, int engineering)
return value;
}
/* This routine processes the entire string returned by translate, looks
* for "@spice_get_node <spice_node> " patterns and replaces with the
/* This routine processes the entire string returned by translate, looks
* for "@spice_get_node <spice_node> " patterns and replaces with the
* Spice simulated value for that node.
* the format is "some_text@spice_get_node <spice_node> some_additional_text"
* Examples:
* Id=@spice_get_node i(\@m.@path@spiceprefix@name\.msky130_fd_pr__@model\[id])
* will translate to:
* will translate to:
* Id=6.6177u
* Id=@spice_get_node i(\@m.@path@spiceprefix@name\.msky130_fd_pr__@model\[id]) A
* will translate to:
* will translate to:
* Id=6.6177uA
* note the required separator spaces around the spice node. Spaces are used here as
* separators since spice nodes don't allow spaces.
@ -4381,7 +4381,7 @@ const char *spice_get_node(const char *token)
/* caller must free returned value
* get the full pathname of "instname" device
* modelparam:
* modelparam:
* 0: current, 1: modelparam, 2: modelvoltage
* param: device parameter, like "ib", "gm", "vth"
* set param to {} (empty str) for just branch current of 2 terminal device
@ -4449,7 +4449,7 @@ char *get_fqdevice(const char *param, int modelparam, const char *instname)
dbg(1, "fqdev=%s\n", fqdev);
strtolower(fqdev);
idx = get_raw_index(fqdev, NULL);
/* special handling for resistors that are converted to b sources:
/* special handling for resistors that are converted to b sources:
* i(@r.x4.r1[i]) --> i(@b.x4.br1[i])
*/
if(idx < 0 && !strncmp(fqdev, "i(@r", 4)) {
@ -4476,7 +4476,7 @@ char *get_fqdevice(const char *param, int modelparam, const char *instname)
const char *translate(int inst, const char* s)
{
#ifdef __unix__
static regex_t *get_sp_cur = NULL;
static regex_t *get_sp_cur = NULL;
#endif
static const char *empty="";
static char *result=NULL; /* safe to keep even with multiple schematics */
@ -4499,7 +4499,7 @@ const char *translate(int inst, const char* s)
char *value1 = NULL;
int sim_is_ngspice, sim_is_vacask /*, sim_is_xyce */;
char *instname = NULL;
if(!s && inst == -1) {
if(result) my_free(_ALLOC_ID_, &result);
#ifdef __unix__
@ -4510,11 +4510,11 @@ const char *translate(int inst, const char* s)
}
#endif
}
if(!s || !xctx || !xctx->inst) {
return empty;
}
#ifdef __unix__
if(!get_sp_cur) {
get_sp_cur = my_malloc(_ALLOC_ID_, sizeof(regex_t));
@ -4525,9 +4525,9 @@ const char *translate(int inst, const char* s)
"^@spice_get_(current|modelparam|modelvoltage)(_[a-zA-Z][a-zA-Z0-9_]*)*\\(", REG_NOSUB | REG_EXTENDED);
}
#endif
sp_prefix = tclgetboolvar("spiceprefix");
if(inst >= xctx->instances) {
dbg(0, "translate(): instance number out of bounds: %d\n", inst);
return empty;
@ -4543,9 +4543,9 @@ const char *translate(int inst, const char* s)
size=CADCHUNKALLOC;
my_realloc(_ALLOC_ID_, &result,size);
result[0]='\0';
dbg(1, "translate(): substituting props in <%s>, instance <%s>\n", s ? s : "<NULL>" , instname);
while(1)
{
c=*s++;
@ -4560,9 +4560,9 @@ const char *translate(int inst, const char* s)
(
( (space || c == '%' || c == '@') && !escape ) ||
( (!space && c != '%' && c != '@') && escape )
)
)
) state=TOK_SEP;
STR_ALLOC(&result, result_pos, &size);
STR_ALLOC(&token, token_pos, &sizetok);
if(state==TOK_TOKEN) token[token_pos++]=(char)c;
@ -4592,13 +4592,13 @@ const char *translate(int inst, const char* s)
const char *path = xctx->sch_path[xctx->currsch] + 1;
int start_level = sch_waves_loaded(), skip = 0;
if(start_level == -1) start_level = 0;
/* skip path components that are above the level where raw file was loaded */
while(*path && skip < start_level) {
if(*path == '.') skip++;
++path;
}
tmp=strlen(path);
STR_ALLOC(&result, tmp + result_pos, &size);
memcpy(result+result_pos, path, tmp+1);
@ -4637,7 +4637,7 @@ const char *translate(int inst, const char* s)
my_free(_ALLOC_ID_, &value);
}
} else if(inst >= 0 && strcmp(token,"@sch_last_modified")==0 && xctx->inst[inst].ptr >= 0) {
get_sch_from_sym(file_name, xctx->inst[inst].ptr + xctx->sym, inst, 0);
if(!stat(file_name , &time_buf)) {
tm=localtime(&(time_buf.st_mtime) );
@ -4749,19 +4749,19 @@ const char *translate(int inst, const char* s)
}
}
if(net) my_free(_ALLOC_ID_, &net);
}
}
}
}
}
/* copy as is: processed by spice_get_node() later
* the format is "some_text@spice_get_node <spice_node> some_additional_text"
* Examples:
* Id=@spice_get_node i(\@m.@path@spiceprefix@name\.msky130_fd_pr__@model\[id])
* will translate to:
* will translate to:
* Id=6.6177u
* Id=@spice_get_node i(\@m.@path@spiceprefix@name\.msky130_fd_pr__@model\[id]) A
* will translate to:
* will translate to:
* Id=6.6177uA
* note the required separator spaces around the spice node. Spaces are used here as
* separators since spice nodes don't allow spaces.
@ -4807,12 +4807,12 @@ const char *translate(int inst, const char* s)
len = strlen(path) + strlen(instname) + strlen(net) + 2;
dbg(1, "net=%s\n", net);
fqnet = my_malloc(_ALLOC_ID_, len);
global_net = strrchr(net, '.');
if(global_net == NULL) global_net = net;
else global_net++;
if(inst < 0 || record_global_node(3, NULL, global_net)) {
strtolower(net);
my_snprintf(fqnet, len, "%s", global_net);
@ -4855,7 +4855,7 @@ const char *translate(int inst, const char* s)
/* @spice_get_current(...) or @spice_get_current_<param>(...)
* @spice_get_modelparam(...) or @spice_get_modelparam_<param>(...)
* @spice_get_modelvoltage(...) or @spice_get_modelvoltage_<param>(...)
*
*
* Only @spice_get_current(...) and @spice_get_current_<param>(...) are processed
* the other types are ignored */
#ifdef __unix__
@ -5048,7 +5048,7 @@ const char *translate(int inst, const char* s)
/* token contans _param after @spice_get_current or @spice_get_modelparam
* or @spice_get_modelvoltage */
if(strcmp(token, "@spice_get_current") &&
strcmp(token, "@spice_get_modelparam") &&
strcmp(token, "@spice_get_modelparam") &&
strcmp(token, "@spice_get_modelvoltage")) {
int n = 0;
param = my_malloc(_ALLOC_ID_, strlen(token) + 1);
@ -5117,7 +5117,7 @@ const char *translate(int inst, const char* s)
if(idx >= 0) {
val = xctx->raw->cursor_b_val[idx];
}
/* special handling for resistors that are converted to b sources:
/* special handling for resistors that are converted to b sources:
* i(@r.x4.r1[i]) --> i(@b.x4.br1[i])
*/
if(idx < 0 && !strncmp(fqdev, "i(@r", 4)) {
@ -5161,7 +5161,7 @@ const char *translate(int inst, const char* s)
}
else if(strcmp(token,"@schspectreprop")==0 && xctx->schspectreprop)
{
{
tmp=strlen(xctx->schspectreprop);
STR_ALLOC(&result, tmp + result_pos, &size);
memcpy(result+result_pos,xctx->schspectreprop, tmp+1);
@ -5176,7 +5176,7 @@ const char *translate(int inst, const char* s)
result_pos+=tmp;
}
/* /20100217 */
else if(strcmp(token,"@schsymbolprop")==0 && xctx->schsymbolprop)
{
tmp=strlen(xctx->schsymbolprop);
@ -5193,7 +5193,7 @@ const char *translate(int inst, const char* s)
result_pos+=tmp;
}
/* /20100217 */
else if(strcmp(token,"@schverilogprop")==0 && xctx->schverilogprop)
{
tmp=strlen(xctx->schverilogprop);
@ -5262,7 +5262,7 @@ const char *translate(int inst, const char* s)
dbg(1, "2 translate(): lcc[%d].prop_ptr=%s, value1=%s\n", i-1, lcc[i-1].prop_ptr, value1);
} else break;
i--;
}
}
tmp=strlen(value1);
STR_ALLOC(&result, tmp + result_pos, &size);
@ -5285,11 +5285,11 @@ const char *translate(int inst, const char* s)
} /* while(1) */
dbg(2, "translate(): returning %s\n", result);
my_free(_ALLOC_ID_, &token);
/* resolve spice_get_node patterns.
/* resolve spice_get_node patterns.
* if result is like: 'tcleval(some_string)' pass it thru tcl evaluation so expressions
* can be calculated */
my_strdup2(_ALLOC_ID_, &result, spice_get_node(tcl_hook2(result)));
if(is_expr(result) && inst >= 0) {
dbg(1, "translate(): expr():%s\n", result);
my_strdup2(_ALLOC_ID_, &result, eval_expr(
@ -5439,8 +5439,8 @@ const char *translate2(Lcc *lcc, int level, char* s)
* ex.: name=@name w=@w l=@l ---> name=m112 w=3e-6 l=0.8e-6
* using s1, s2, s3 in turn to resolve @tokens
* if no definition for @token is found return @token as is in s
* if s==NULL return emty string
* eat_escapes:
* if s==NULL return emty string
* eat_escapes:
* bit0 == 0 --> keep escapes
* == 1 --> remove escapes
* bit1 == 0 --> return unchanged token if no value found in s* strings
@ -5457,7 +5457,7 @@ const char *translate3(const char *s, int eat_escapes, const char *s1,
size_t sizetok=0;
size_t token_pos=0;
const char *value;
int i, escape=0;
int i, escape=0;
size_t found_value = 0;
const char *escape_pos = NULL;
const char *sptr[5]; /* 1...4 used */
@ -5484,7 +5484,7 @@ const char *translate3(const char *s, int eat_escapes, const char *s1,
(
( (space || c == '%' || c == '@') && !escape ) ||
( (!space && c != '%' && c != '@') && escape )
)
)
) state=TOK_SEP;
if( s > escape_pos ) escape = 0;
s++;

12
src/track_memory.awk
View File

@ -1,14 +1,14 @@
#!/usr/bin/awk -f
# memory leak analyzer. Run xschem with options "-d 3 -l log", do some operations you want to check
# then *from this directory* launch:
# then *from this directory* launch:
# ./track_memory.awk /path/to/log [nosource]
# it will print the amount of leaked memory (total, leak)
# and the allocation that was not freed, with the source code line (if 'nosource' not given)
# it will print the amount of leaked memory (total, leak)
# and the allocation that was not freed, with the source code line (if 'nosource' not given)
# total and leak should indicate same amount of bytes, it is a cross check for the script.
BEGIN{
show_source = 1
max = 0
total = 0
total = 0
malloc = 0
free = 0
realloc = 0
@ -21,7 +21,7 @@ BEGIN{
}
# my_malloc(234,): allocating 1a01ff0 , 10 bytes
/^my_[mc]alloc\(/{
/^my_[mc]alloc\(/{
id = $1
sub(/.*\(/,"", id)
sub(/,.*/,"",id)
@ -33,7 +33,7 @@ BEGIN{
}
# my_free(977,): freeing 198efc0
/^my_free\(/{
/^my_free\(/{
if(!($3 in address)) {
print "Double free: " $0 " Log file line: " NR
} else {

4
src/traduci.awk
View File

@ -38,7 +38,7 @@ function replace_pattern(old, new)
{
__a[__lines++] = $0
__a[__lines++] = $0
}
function beginfile(f)
@ -57,5 +57,5 @@ function endfile(f, i)
}
close(f)
}
}
}

30
src/utile/clock.awk
View File

@ -1,27 +1,27 @@
#!/usr/bin/awk -f
# File: clock.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
#
# plugin for clock expansion
#
# clock <signal> <pulse> <period> [invert] [high value] [low value]
@ -30,7 +30,7 @@
#___________________| |____________| |__________
# | | |
# |<pulse>| |
# |<----- period ----->|
# |<----- period ----->|
# |
# clock_start
# Stefan, 04122001
@ -41,7 +41,7 @@ BEGIN {
OFMT="%.14g" # better precision
CONVFMT="%.14g"
old_event=-1
}
}
## stefan fix 20100630: reset absolute time if multiple beginfile--endfile given
/^[ \t]*beginfile[ \t]+/{
@ -49,7 +49,7 @@ BEGIN {
}
/^[ \t]*clock[ \t]+/{
sub(/[ \t]*;.*/,"")
clock_name = $2
clock_start[clock_name]=time
@ -67,7 +67,7 @@ BEGIN {
if($6!="") clock_low[clock_name]=$6
else clock_low[clock_name]=0
}
print "set " clock_name " " value(clock_name, clock_state[clock_name])
next
}
@ -128,7 +128,7 @@ function next_event( k, i, clock_event1, clock_event2)
{
k=0
for(i in clock_start)
{
{
clock_event1 = int( (time-clock_start[i])/clock_period[i])*clock_period[i] + clock_start[i]
while(clock_event1 <= time) {
clock_event1+=clock_period[i]
@ -137,14 +137,14 @@ function next_event( k, i, clock_event1, clock_event2)
while(clock_event2 <= time) {
clock_event2+=clock_period[i]
}
if(clock_event1 < clock_event2)
if(clock_event1 < clock_event2)
clock_event = clock_event1+0
else
else
clock_event = clock_event2+0
if(!k) { event=clock_event ; current_clock=i; k=1}
else if(clock_event < event)
else if(clock_event < event)
{
event = clock_event
event = clock_event
current_clock=i
}
else if( abs(clock_event - event)<1e-12 )
@ -163,7 +163,7 @@ function value(clock_name, i) {
else return clock_low[clock_name]
}
function abs(x)
function abs(x)
{
return x<0? -x : x
}

22
src/utile/expand_alias.awk
View File

@ -1,21 +1,21 @@
#!/usr/bin/awk -f
# File: expand_alias.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -33,7 +33,7 @@
# sample input:
#
# alias ciclo_we par1 par2
#
#
# set apad 0
# set dqpad 0
# s .1
@ -45,9 +45,9 @@
# set dqpad 0
# set wenpad 1
# s .1
#
#
# endalias
#
#
# ciclo_we aa 55
# ciclo_we 55 aa
@ -82,7 +82,7 @@ function process_line()
alias[name , "l" line++]=$0
if($1 ~ /^endalias *$/)
{
alias[name , "lines"]=line-1
alias[name , "lines"]=line-1
beginalias=0;
}
return
@ -92,7 +92,7 @@ function process_line()
expand_alias($0)
}
else print $0
}
}
# 20150718 generic replacer of {param} patterns in macro lines
@ -117,11 +117,11 @@ function replace(name, s, pre, par, post)
return s
}
# 20110630
# 20110630
function analyze_params_in_expressions(name, s, ss, s_arr, i, o, o_arr, n)
{
s=replace(name, s) #20150918 new {par} format to avoid ambiguities in complex patterns
ss=""
n = split(s, s_arr, /[=\-\/\+\*]/) # 20150810 added '=' for substituting 'set sig 0 slope=slp' with slp=param
o = split(s, o_arr, /[^=\-\+\*\/]+/) # 20150810 added '='

20
src/utile/param.awk
View File

@ -1,28 +1,28 @@
#!/usr/bin/awk -f
# File: param.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
# 20200212 added simple expression parsing
# 20170830
# 20170830
BEGIN{
for(i=0;i<=127;i++)
{
@ -34,7 +34,7 @@ BEGIN{
{
gsub (/[ \t]*=[ \t]*/, "=")
}
/^\.*param/{
param[$2]=arith($3)
@ -59,9 +59,9 @@ BEGIN{
}
else {
$nf = arith($nf)
}
}
}
}
}
#20171117 ascii string --> hex
@ -85,7 +85,7 @@ BEGIN{
# 20150718 generic replacer of {param} patterns
# 20150718 generic replacer of {param} patterns
# example: set vcc '{param}? 1.2 : {vhigh}'
function replace(s, pre, par, post)
{
@ -134,7 +134,7 @@ function arith(s, op, n, ss, j, valid_expr, arith_operators)
}
}
if(!valid_expr) return sss
# if the result of an arithmetic evaluation is 1 return 1.0
# if the result of an arithmetic evaluation is 1 return 1.0
# otherwise stimuli.awk will translate it to the high logic value
else if(arith_operators && lab==1) return "1.0"
else return lab

10
src/utile/preprocess.awk
View File

@ -1,26 +1,26 @@
#!/usr/bin/awk -f
# File: preprocess.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
#
function expand_file(file, err)

138
src/utile/stimuli.awk
View File

@ -1,21 +1,21 @@
#!/usr/bin/awk -f
# File: stimuli.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -72,7 +72,7 @@
# - prefixing a bus assignment with the tilde char (~) produces inverted data:
# ex: set apad ~AA'0101'FF ---> 0101 0101 1010 0000 0000
# - NEW!!!! added relative_powermill format, which generates stimuli files
# with no explicit reference to absolute time, usefull for interactive mode
# with no explicit reference to absolute time, usefull for interactive mode
# simulations, (generated file can be read with read_cmd_file command)
# example:
# rel_node_v no=aaa
@ -93,9 +93,9 @@
# By the way, why not padding with "x" chars which mean don't
# change?
# 01/01/2000 - tobinary() pads missing bits with "x" chars, removed the test
# on space described above. I hope this does not introduce
# on space described above. I hope this does not introduce
# side effects/bugs.
# 10/01/2000 - Removed explicit pathnames. this is no more an awk script but a
# 10/01/2000 - Removed explicit pathnames. this is no more an awk script but a
# sh script, which in turn runs awk.
# 21/01/2000 - bugfix: the last "set whatever_node 1" assigment in stimuli file
# was incorrectly translated to "force_node_v no=whatever_node v=1"
@ -105,21 +105,21 @@
# assignment (relative_powermill only)
# 01-06-2000 - dump lines are printed in the position they appear, not at end of file.
# eldo and spice keywords work as before
# 24-10-2001 - fixed a bug in write_pwl_pair.(incorrect eldo stimuli generation in
# 24-10-2001 - fixed a bug in write_pwl_pair.(incorrect eldo stimuli generation in
# case of assignment at time=previous time+slope).
# 21-11-2001 - NEW! ncsim format
# 03-12-2001 - clock and stop_clock directives, handled by external clock.awk program
# 04-12-2001 - Improvements in ncsim format (dont cares, single bit and bus slice
# 04-12-2001 - Improvements in ncsim format (dont cares, single bit and bus slice
# assignments
# 12-07-2002 - Improvements in the clock keyword, now high and low voltage levels can
# 12-07-2002 - Improvements in the clock keyword, now high and low voltage levels can
# be specified too, no backward compatibility issues, see help file
# When pressing the Translate button the simulated time is printed
# 24-07-2002 - various bug fixes (ncsim bus slice notation using () instead of [] to
# avoid confusing the ncsim TCL interpreter,when using the ncsim source
# avoid confusing the ncsim TCL interpreter,when using the ncsim source
# command )
# 23-08-2002 - in ncsim format comments are printed on translated file to indicate the
# 23-08-2002 - in ncsim format comments are printed on translated file to indicate the
# beginning of an alias
# 28-10-2002 - optional index delimiters in buswidth declaration: ex: buswidth add 4 < >
# 28-10-2002 - optional index delimiters in buswidth declaration: ex: buswidth add 4 < >
# --> add<3> add<2> add<1> add<0>
# 28-10-2002 - create_eldo_bus keyword can be specified to force bus creation for xelga
# plots even when the eldo_simple option is used
@ -127,10 +127,10 @@
# set vxp 8.0 20000 ==> 20K resistance
# 29-10-2003 - New keyword "ground" to specify low voltage level (Vil), similarly to "voltage" for Vih
# 08-09-2005 - New ground_node keyword for specifying different gnd node for sources
# 20100301 - new syntax for set instruction,
# 20100301 - new syntax for set instruction,
# set <signal> <sigval> [res=<resval>] [vhi=<hival>] [vlo=<lowval>] [slope=<slopeval>]
# all values can be parametrs and simple arithmetic expressions with parameters
# - added simple expression parser on params, supported operators : +, -, *, /, expressions
# - added simple expression parser on params, supported operators : +, -, *, /, expressions
# evaluated frol left to right, no parenthesis, and no operator priority..
# examples:
# param tck 2500
@ -140,7 +140,7 @@
# set a vx-0.3
# s tck-tds
#
#
#
#
# sample input:
# time 0
@ -148,7 +148,7 @@
# unit u
# voltage 1.8
# bus apad apad8 apad7 apad6 apad5 apad4 apad3 apad2 apad1 apad0
#
#
# set vneg_h 1 ; set initial state
# set vnegon 1
# set vxws_off 1
@ -157,9 +157,9 @@
# set sw_to_neg 1
# set vxh 0
# set apad 000
#
#
# s 110
#
#
# set apad 1ff
# set arrpwh 0
# s 8
@ -168,7 +168,7 @@
# set vnegon 0
# s 7
#
# usage:
# usage:
# expand_alias.awk stimuli3 | clock.awk |stimuli.awk
BEGIN{
@ -197,16 +197,16 @@ BEGIN{
}
}
/^[ \t]*beginfile[ \t]+/{
/^[ \t]*beginfile[ \t]+/{
reset_all();file=$2
next
next
}
/<<<alias>>>/{
if(format != "ncsim") next
/<<<alias>>>/{
if(format != "ncsim") next
$0 = $1 " " $2 " " $3 " " $4 # 20100212
}
/^[ \t]*(eldo|spice)[ \t]+/{$1="";$0=substr($0,2);dump[++dumpline]=$0;next}
# 20170419 added {time} to be replaced with actual time value in dump string
@ -221,7 +221,7 @@ BEGIN{
/^[ \t]*halfvoltage[ \t]+/{ halfvoltage=$2; halfvoltageset=1} # 20160412
/^[ \t]*unit[ \t]+/{ unit=$2}
/^[ \t]*ground_node[ \t]+/{ gndnode=$2}
/^[ \t]*format[ \t]+/{
/^[ \t]*format[ \t]+/{
if($2=="hspice") {
format="eldo"
variant="hspice"
@ -236,7 +236,7 @@ BEGIN{
ground=$2
if(!halfvoltageset) { # 20170405
if(is_number(voltage) && is_number(ground)) {
halfvoltage=(voltage+ground) / 2
halfvoltage=(voltage+ground) / 2
} else {
halfvoltage = "'(" voltage "+" ground ")/2)'"
}
@ -246,17 +246,17 @@ BEGIN{
voltage = $2
if(!halfvoltageset) { # 20170405
if(is_number(voltage) && is_number(ground)) {
halfvoltage=(voltage+ground) / 2
halfvoltage=(voltage+ground) / 2
} else {
halfvoltage = "'(" voltage "+" ground ")/2'"
}
}
}
/^[ \t]*reset_sim[ \t]*/{if(format=="ncsim") print "reset" >file} # usefull in ncsim
/^[ \t]*s[ \t]+/{
time+=$2
if(format=="ncsim" && time >=0 )
if(format=="ncsim" && time >=0 )
{
print "run " $2 " " unit "s" >file
}
@ -280,8 +280,8 @@ BEGIN{
print "; time= " time > file
powmill_statement++
delete set_list
}
}
}
/^[ \t]*buswidth[ \t]+/{
@ -291,7 +291,7 @@ BEGIN{
for(i=($3); i>=1;i--)
bus[$2,i]=$2 openbracket $3-i closebracket
}
/^[ \t]*bus[ \t]+/{
@ -310,7 +310,7 @@ BEGIN{
/^[ \t]*set[ \t]+/{
# 20100301
res = ron
res = ron
vhi = voltage
vlo = ground
slp=slope
@ -318,7 +318,7 @@ BEGIN{
for(i=4; i<=NF; i++) {
if($i ~ /^;/) break
#20150918 delete $i after using it
if((i==4) && ($i+0>0) && NF==4 ) { res=$i;$i=""; break}
if((i==4) && ($i+0>0) && NF==4 ) { res=$i;$i=""; break}
if(tolower($i) ~ /^r(es)?=/) { res=$i; sub(/^.*=/,"",res); $i="" }
if(tolower($i) ~ /^vhi(gh)?=/) { vhi=$i; sub(/^.*=/,"",vhi); $i="" }
if(tolower($i) ~ /^vlow?=/) { vlo=$i; sub(/^.*=/,"",vlo); $i="" }
@ -333,7 +333,7 @@ BEGIN{
halfvoltage = "'(" vhi "+" vlo ")/2'"
}
}
if($2 in buswidth)
{
if($3 ~ /^~/) # inversion flag on bus assignment
@ -354,13 +354,13 @@ BEGIN{
w=buswidth[$2]
low=s_i(bus[$2,w]) # LSB bit of the bus
high=s_i(bus[$2,w-num+1]) # MSB bit of the bus
if(num < w && num >1 )
{
sig=sig "(" high ":" low ")" ; quote="\""
}
if(num < w && num ==1)
if(num < w && num >1 )
{
sig=sig "(" low ")" ; quote="'"
sig=sig "(" high ":" low ")" ; quote="\""
}
if(num < w && num ==1)
{
sig=sig "(" low ")" ; quote="'"
}
if($3 !~ /[zZxX]/)
{
@ -370,7 +370,7 @@ BEGIN{
{
print "release " sig >file
}
else
else
{
sig= "." $2
gsub(/\./,":",sig)
@ -395,7 +395,7 @@ BEGIN{
v=substr(binstring,i,1)
if(v !~ /[xX]/)
{
set_list[s]=v # used to build the set of signals forced between
set_list[s]=v # used to build the set of signals forced between
# successive s lines
}
@ -413,7 +413,7 @@ BEGIN{
{
$3=1
}
if($3 !~ /^[xX]$/)
{
$3=$0
@ -467,10 +467,10 @@ function end_file(){
print "**************************************\n" > file
for(i in signalname)
{
use_z = ( (format !~ /_simple/) && signalz[i] )
use_z = ( (format !~ /_simple/) && signalz[i] )
ix=i
gsub(/\./,"_",ix)
if(!use_z)
if(!use_z)
printf simplesignalname[i]>file
else
printf signalname[i]>file
@ -483,7 +483,7 @@ function end_file(){
# 20100224 quotes instead of parenthesis used for value=....
# as per new eldo syntax. this makes it compatible w eldo and hspice
print "R" ix " XX" ix " " i " value='v(VR" ix ")'">file
else
else
print "R" ix " XX" ix " " i " 'v(VR" ix ")'">file
printf "%s",signalres[i]>file
for(j=1;j<=signal[i,"n"];j++)
@ -509,7 +509,7 @@ function end_file(){
print "; POWERMILL VECTOR FILE">file
print "type vec">file
printf "signal ">file
for(i=1;i<=signals;i++)
for(i=1;i<=signals;i++)
printf signal_list[i] " " >file
printf "\n" >file
print "slope " slope*mult>file
@ -529,7 +529,7 @@ function end_file(){
if(j>1) x-=slp
v=signal[i,"value",j]
if(v>halfvoltage) vv="1"
if(v==halfvoltage) vv="z"
if(v==halfvoltage) vv="z"
if(v<halfvoltage) vv="0"
if(output[x]=="") output[x]=chars(signals,"_")
output[x]=setbit(output[x],vv,signals-k)
@ -615,18 +615,18 @@ function write_pwl_pair( name, value,res, vhi, vlo,slope, timex, namex,vv,vv1,
else {v = value; pwlres=res}
namex=name
gsub(/\./,"_",namex)
if(!(name in signalname) )
if(!(name in signalname) )
{
timex=time < 0 ? 0: time
signal_list[++signals]=name
signalname[name]="V" namex " XX" namex " " gndnode " PWL "
simplesignalname[name]="V" namex " " name " " gndnode " PWL "
signalname[name]="V" namex " XX" namex " " gndnode " PWL "
simplesignalname[name]="V" namex " " name " " gndnode " PWL "
signal[name,"time",1]= timex
signal[name,"value",1]= v
signal[name,"n"]= 1
# 20170810 0 instead of gndnode
# |
signalres[name]="VR" namex " VR" namex " " 0 " PWL "
signalres[name]="VR" namex " VR" namex " " 0 " PWL "
signalres[name,"value",1]= pwlres
}
if(signal[name,"value", signal[name,"n"] ]!=v || signalres[name,"value", signal[name,"n"] ]!=pwlres)
@ -641,10 +641,10 @@ function write_pwl_pair( name, value,res, vhi, vlo,slope, timex, namex,vv,vv1,
}
## 20151112
else if(timex+slope == signal[name,"time",signal[name,"n"]] ) {
n = signal[name,"n"]
n = signal[name,"n"]
signal[name,"value",n]= v
signalres[name,"value",n]= pwlres
}
}
else
{
if( timex > signal[name,"time",signal[name,"n"]] )
@ -657,11 +657,11 @@ function write_pwl_pair( name, value,res, vhi, vlo,slope, timex, namex,vv,vv1,
## 20100302 interpolation if signal change occurs before conpleting previous transaction
else if(timex < signal[name,"time",signal[name,"n"]] ){
n = signal[name,"n"]
vv1 = signal[name,"value",n-1]
vv2 = signal[name,"value",n]
tt1 = signal[name,"time",n-1]
tt2 = signal[name,"time",n]
n = signal[name,"n"]
vv1 = signal[name,"value",n-1]
vv2 = signal[name,"value",n]
tt1 = signal[name,"time",n-1]
tt2 = signal[name,"time",n]
vv = vv1 + (vv2-vv1)/(tt2-tt1) * (timex-tt1)
signal[name,"time",n]=timex
signal[name,"value",n]= vv
@ -674,7 +674,7 @@ function write_pwl_pair( name, value,res, vhi, vlo,slope, timex, namex,vv,vv1,
signal[name,"time",n]=timex+slope
signal[name,"value",n]= v
signalres[name,"value",n]= pwlres
}
}
}
}
}
@ -752,7 +752,7 @@ function binary( n, width, a,i,str)
}
return str
}
function binval(str, i,n)
# returns the decimal value of the binary number encoded in "str"
{
@ -803,7 +803,7 @@ function hsort(array,ra,n, rarray,l,j,ir,i,rra)
array[i]=rarray
}
}
function setbit( string, replace, pos, reversepos,len)
# returns <string> with bits starting at position <pos>
# set to <replace>, position 0 being relative to the rightmost bit
@ -851,7 +851,7 @@ function reset_all()
delete dump
time=0
origin=0
}
function break_lines(filename, quote, j, lines, line, l, i, count, style )
@ -863,7 +863,7 @@ function break_lines(filename, quote, j, lines, line, l, i, count, style )
close(filename)
# 20120410
lines = lines + 0 # do NOT remove, solves a problem with gawk 3.0.5 where a variable used as
lines = lines + 0 # do NOT remove, solves a problem with gawk 3.0.5 where a variable used as
# array index is "magically" converted to string
@ -871,10 +871,10 @@ function break_lines(filename, quote, j, lines, line, l, i, count, style )
for(l=1;l<=lines;l++)
{
$0=line[l]
if($0 ~ /^\* ELDO/) {style="+"}
if($0 ~ /^; POWERMILL/) {style="\\"}
count=0
if(NF==0) print "">filename
@ -886,7 +886,7 @@ function break_lines(filename, quote, j, lines, line, l, i, count, style )
if(substr($i,j,1)=="'") quote = !quote
}
# print "+++ " quote, $i, count
printf "%s ", $i>filename
count++
if(( count>=15 && !quote) || i==NF)

50
src/utile/utile.tcl
View File

@ -1,22 +1,22 @@
#!/bin/sh
# File: utile.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -32,13 +32,13 @@ proc text_window {w filename} {
toplevel $w
wm title $w "(IN)UTILE ALIAS FILE"
wm iconname $w "ALIAS"
frame $w.buttons
pack $w.buttons -side bottom -fill x -pady 2m
button $w.buttons.dismiss -text Dismiss -command "destroy $w"
button $w.buttons.code -text "See Code" -command "showCode $w"
pack $w.buttons.dismiss $w.buttons.code -side left -expand 1
text $w.text -relief sunken -bd 2 -yscrollcommand "$w.scroll set" -setgrid 1 \
-height 30
scrollbar $w.scroll -command "$w.text yview"
@ -47,7 +47,7 @@ proc text_window {w filename} {
set fileid [open $filename "r"]
$w.text insert 0.0 [read $fileid]
close $fileid
}
}
proc entry_line {txtlabel} {
global entry1
@ -83,10 +83,10 @@ proc entry_line {txtlabel} {
proc write_data {w f} {
set fid [open $f "w"]
set t [$w get 0.0 {end - 1 chars}]
puts -nonewline $fid $t
puts -nonewline $fid $t
close $fid
}
proc read_data {w f} {
set fid [open $f "r"]
set t [read $fid]
@ -120,11 +120,11 @@ proc new_window {w filename} {
translate $filename ; get_time"
button $w.buttons.dismiss -text Dismiss -command "destroy $w"
pack $w.buttons.dismiss $w.buttons.translate -side left -expand 1
pack $w.scroll -side right -fill y
pack $w.text -expand yes -fill both
}
proc get_time {} {
set fileid [open "inutile.simulationtime" "RDONLY"]
.buttons.time delete 0 end
@ -132,8 +132,8 @@ proc get_time {} {
close $fileid
file delete "inutile.simulationtime"
}
proc alias_window {w filename} {
catch {destroy $w}
toplevel $w
@ -152,24 +152,24 @@ proc alias_window {w filename} {
button $w.buttons.save -text Save -command "write_data $w.text $filename"
button $w.buttons.load -text Reload -command "read_data $w.text $filename"
pack $w.buttons.dismiss $w.buttons.save $w.buttons.load -side left -expand 1
pack $w.scroll -side right -fill y
pack $w.text -expand yes -fill both
$w.text insert 0.0 $testo
}
}
proc help_window {w filename} {
catch {destroy $w}
toplevel $w
wm title $w "(IN)UTILE ALIAS FILE"
wm iconname $w "ALIAS"
frame $w.buttons
pack $w.buttons -side bottom -fill x -pady 2m
button $w.buttons.dismiss -text Dismiss -command "destroy $w"
button $w.buttons.save -text Save -command "write_data $w.text $filename"
pack $w.buttons.dismiss $w.buttons.save -side left -expand 1
text $w.text -relief sunken -bd 2 -yscrollcommand "$w.scroll set" -setgrid 1 \
-height 30 -width 90
scrollbar $w.scroll -command "$w.text yview"
@ -178,7 +178,7 @@ proc help_window {w filename} {
set fileid [open $filename "RDONLY CREAT"]
$w.text insert 0.0 [read $fileid]
close $fileid
}
}
proc translate {f} {
global tcl_platform
@ -214,15 +214,15 @@ text .text -relief sunken -bd 2 -yscrollcommand ".scroll set" -setgrid 1 \
scrollbar .scroll -command ".text yview"
button .buttons.save -text Save -command {
set entry1 $filename;set filename [entry_line {Filename}]
write_data .text $filename
write_data .text $filename
}
button .buttons.load -text Reload -command {
set entry1 $filename;set filename [entry_line {Filename}]
read_data .text $filename
read_data .text $filename
}
button .buttons.send -text "Template" -command {
if { ![string compare [.text get 0.0 {end - 1 chars}] ""] } then {
template .text $env(UTILE3_PATH)/template.stimuli
template .text $env(UTILE3_PATH)/template.stimuli
}
}
label .buttons.timelab -text "time:"
@ -235,7 +235,7 @@ pack .scroll -side right -fill y
pack .text -expand yes -fill both
# 20140408
if { [file exists $filename] } {
if { [file exists $filename] } {
set fileid [open $filename "RDONLY"]
.text insert 0.0 [read $fileid]
close $fileid
@ -248,10 +248,10 @@ regsub {\..*$} $tmp {} lines
for {set i 1} {$i <= $lines} {incr i} {
set tmp [.text get $i.0 "$i.0 lineend"]
if [regexp {^(include)|(\.include)} $tmp ] {
alias_window .tw$i [lindex $tmp 1]
if [regexp {^(include)|(\.include)} $tmp ] {
alias_window .tw$i [lindex $tmp 1]
}
}
}

40
src/verilog.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: verilog.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -77,13 +77,13 @@ BEGIN{
sub(/----pin\(/,"",prim_field)
sub(/\)$/,"",prim_field)
pport_mult = split(prim_field, prim_field_array,/,/)
# 20060919 BEGIN
# if bussed port connected to primitive and primitive mult==1 print only basename of bus
if(primitive_mult==1 && pport_mult>1) {
if(check2(prim_field_array, pport_mult))
printf "%s[%s:%s] ", prefix s_b(prim_field_array[1]),
s_i(prim_field_array[1]), s_i(prim_field_array[pport_mult])
if(check2(prim_field_array, pport_mult))
printf "%s[%s:%s] ", prefix s_b(prim_field_array[1]),
s_i(prim_field_array[1]), s_i(prim_field_array[pport_mult])
else {
printf " { "
for(s=1;s<= pport_mult; s++) {
@ -92,8 +92,8 @@ BEGIN{
}
printf "}%s", primitive_line_sep[i+1]
}
}
else
}
else
# 20060919 end
printf "%s", prim_field_array[1+(j-1) % pport_mult] # 20140401 1+(j-1) % pport_mult instead of j
@ -130,7 +130,7 @@ primitive==1{primitive_line=primitive_line "\n" $0; next }
printf "%s ", signal_type[i]
# 20161118
ntypes = split(signal_type[i], sigtype_arr)
ntypes = split(signal_type[i], sigtype_arr)
if(ntypes==2) {
if( i in signal_delay) printf "%s ", signal_delay[i]
printf "%s", i
@ -144,7 +144,7 @@ primitive==1{primitive_line=primitive_line "\n" $0; next }
printf " ;\n"
} else {
if( i in signal_delay) printf "%s ", signal_delay[i]
if(signal_index[i] !~ /no_index/)
if(signal_index[i] !~ /no_index/)
{
if(tmp[1] ~ /:/) printf "[%s] ",tmp[1]
else if(n==1) printf "[%s:%s] ",tmp[1], tmp[1]
@ -156,7 +156,7 @@ primitive==1{primitive_line=primitive_line "\n" $0; next }
}
}
# /20161118
siglist=0;
print ""
netlist=1
@ -165,7 +165,7 @@ primitive==1{primitive_line=primitive_line "\n" $0; next }
# store signals
siglist==1 && ($1 in net_types) {
# 20070525 recognize "reg real", "wire signed" types and similar
# 20070525 recognize "reg real", "wire signed" types and similar
if($2 in net_types) {
if($3 ~ /^#/) basename=s_b($4)
else basename=s_b($3)
@ -199,7 +199,7 @@ siglist==1 && ($1 in net_types) {
if($3=="="){
val=$0
sub(/.*=/,"",val)
sub(/;.*/,"",val)
sub(/;.*/,"",val)
signal_value[basename]=val
}
if(!(basename in signal_basename)) signal_num[signal_n++] = basename # used to preserve order of signals
@ -211,7 +211,7 @@ siglist==1 && ($1 in net_types) {
}
next
}
/---- begin signal list/{
siglist=1;
next
@ -301,7 +301,7 @@ begin_module && $1 ~/^\);$/ {
printf "\n);\n\n"
}
previous=""
next
next
}
# types of in/out/inout ports of module
@ -335,7 +335,7 @@ NF==3 && netlist==0 && architecture==0 && ($1 in direction) {
next
}
/^---- end parameters/{
/^---- end parameters/{
parameters=0
next
}
@ -412,7 +412,7 @@ function hsort(ra,n, l,j,ir,i,rra)
ra[i]=rra
}
}
# check if an array of indexes (sig[3]) arr[1],arr[2].....
# check if an array of indexes (sig[3]) arr[1],arr[2].....
# is contigous and decreeasing
# 20140409 handle ascending order as well as descending
function check2(arr,n ,decreasing,a,name,i,start,ok)

24
src/verilog_netlist.c
View File

@ -108,7 +108,7 @@ int global_verilog_netlist(int global, int alert) /* netlister driver */
/* top sch properties used for library use declarations and type definitions */
/* to be printed before any entity declarations */
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
tclgetvar("netlist_dir"), get_cell(xctx->sch[xctx->currsch], 0),getpid());
fd=fopen(netl_filename, "w");
if(fd==NULL){
@ -136,7 +136,7 @@ int global_verilog_netlist(int global, int alert) /* netlister driver */
if( type && (strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value(xctx->sym[xctx->inst[i].ptr].prop_ptr , fmt_attr, 2);
if(!xctx->tok_size && strcmp(fmt_attr, "verilog_format"))
if(!xctx->tok_size && strcmp(fmt_attr, "verilog_format"))
str_tmp = get_tok_value(xctx->sym[xctx->inst[i].ptr].prop_ptr, "verilog_format", 2);
my_strdup(_ALLOC_ID_, &tmp_string, str_tmp);
@ -487,15 +487,15 @@ int verilog_block_netlist(FILE *fd, int i, int alert)
if( type && ( strcmp(type,"timescale")==0 || strcmp(type,"verilog_preprocessor")==0) )
{
str_tmp = get_tok_value(xctx->sym[xctx->inst[j].ptr].prop_ptr, fmt_attr, 2);
if(!xctx->tok_size && strcmp(fmt_attr, "verilog_format"))
if(!xctx->tok_size && strcmp(fmt_attr, "verilog_format"))
str_tmp = get_tok_value(xctx->sym[xctx->inst[j].ptr].prop_ptr, "verilog_format", 2);
my_strdup(_ALLOC_ID_, &tmp_string, str_tmp);
fprintf(fd, "%s\n", str_tmp ? translate(j, tmp_string) : "<NULL>");
}
}
my_strdup(_ALLOC_ID_, &verilogprefix,
my_strdup(_ALLOC_ID_, &verilogprefix,
get_tok_value(xctx->sym[i].prop_ptr, "verilogprefix", 0));
if(verilogprefix) {
my_strdup(_ALLOC_ID_, &symname, verilogprefix);
@ -506,13 +506,13 @@ int verilog_block_netlist(FILE *fd, int i, int alert)
my_free(_ALLOC_ID_, &verilogprefix);
fprintf(fd, "module %s (\n", sanitize(symname));
my_free(_ALLOC_ID_, &symname);
/*print_generic(fd, "entity", i); */
dbg(1, "verilog_block_netlist(): entity ports\n");
/* print port list */
tmp=0;
for(j=0;j<xctx->sym[i].rects[PINLAYER]; ++j)
@ -527,7 +527,7 @@ int verilog_block_netlist(FILE *fd, int i, int alert)
}
}
int_hash_free(&table);
if(extra) {
for(extra_ptr = extra; ; extra_ptr=NULL) {
extra_token=my_strtok_r(extra_ptr, " ", "", 0, &saveptr1);
@ -549,7 +549,7 @@ int verilog_block_netlist(FILE *fd, int i, int alert)
if(strboolcmp(get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_ignore",0), "true")) {
my_strdup(_ALLOC_ID_, &sig_type,get_tok_value(
xctx->sym[i].rect[PINLAYER][j].prop_ptr,"verilog_type",0));
my_strdup(_ALLOC_ID_, &port_value,
my_strdup(_ALLOC_ID_, &port_value,
get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"value", 0) );
my_strdup(_ALLOC_ID_, &dir_tmp, get_tok_value(xctx->sym[i].rect[PINLAYER][j].prop_ptr,"dir",0) );
if(strcmp(dir_tmp,"in")){
@ -594,13 +594,13 @@ int verilog_block_netlist(FILE *fd, int i, int alert)
if(skip_instance(l, 1, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strboolcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[l].prop_ptr,"value", 0));
}
}
if(xctx->schverilogprop && xctx->schverilogprop[0]) {
fprintf(fd, "%s\n", xctx->schverilogprop);
}

90
src/vhdl.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: vhdl.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2024 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -130,14 +130,14 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
component_name=$2
no_print=1
}
(component==1){
if($4==":=") $5=get_number($5)
if($5==":=") $6=get_number($6)
if($1 ~ /\[.*:.*\]/)
{
arch_sig_name[component_name,$1]=s_b($1) # array used to compare
arch_sig_name[component_name,$1]=s_b($1) # array used to compare
# actual ports in instances, if they match
# avoid indexes (to/downto)
xx=s_i($1)
@ -155,7 +155,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
$4=vector_type xxx[1] " downto " xxx[2] ")"
else
$4=vector_type xxx[1] " to " xxx[2] ")"
$1=s_b($1)
$1=s_b($1)
print " " $0
}
else print $0
@ -195,12 +195,12 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
$1=s_b($1)
print " " $0
}
else print $0
else print $0
entity_ports[$1]=1
if($1=="end" && $2==entity_name) entity=0
no_print=1
}
#### BEGIN RESOLVE SIGNALS
@ -216,10 +216,10 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
# omit bit ranges ( CNT => CNT(3 downto 0) --> CNT => CNT )
print $0
no_print=1
}
}
/^[ \t]*(signal|constant|variable)[ \t]+/{ ### dangerous <<< 07062002 added "variable"
if( $NF ~ /\[[^:,]+:[^:,]+\]$/) # 09112003, corrected to recognize only XXX[3:1] and not XXX[3:1],AA[3]
{
up=$NF
@ -285,7 +285,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
{
i = arch_signal_num[ii]
## 04062002 don't add _vector if user defined type
if(arch_sig_type_array[i] ~ /^(boolean|bit|real|std_logic|integer)$/)
if(arch_sig_type_array[i] ~ /^(boolean|bit|real|std_logic|integer)$/)
vector_type=arch_sig_type_array[i] "_vector ("
else
vector_type=arch_sig_type_array[i] " ("
@ -294,22 +294,22 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
hsort(tmp, n)
if(n>1 || (arch_index_array[i] !~ /no_index/) ) #11092003 if not no_index treat as a bus
{
if(check(tmp,n))
if(check(tmp,n))
{
if(arch_signal_dir[i] == " downto ")
{
arch_sig_name[entity_name, i "[" tmp[1] ":" tmp[n] "]"]=i
arch_sig_name[entity_name, i "[" tmp[1] ":" tmp[n] "]"]=i
printf "%s",arch_signal_class[i] " " i " : " vector_type tmp[1] " downto " tmp[n] ")" #04062002
}
else
{
arch_sig_name[entity_name, i "[" tmp[n] ":" tmp[1] "]"]=i
arch_sig_name[entity_name, i "[" tmp[n] ":" tmp[1] "]"]=i
printf "%s",arch_signal_class[i] " " i " : " vector_type tmp[n] " to " tmp[1] ")" #04062002
}
}
else print "\n**** ERROR >>>> " i " non contigous bus ->" n, "|" arch_index_array[i] "|"
}
else
else
{
# we do not declare parametrized subranges as normally will result in redeclaration
# of a port signal
@ -328,7 +328,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
printf "%s",arch_signal_class[i] " " basename " : " vector_type range #04062002
}
else continue
}
}
else
printf "%s",arch_signal_class[i] " " i " : " arch_sig_type_array[i]
}
@ -339,7 +339,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
# if(tolower(arch_sig_type_array[i]) ~ /vector/) sep="\""
if(n>1 || (arch_index_array[i] !~ /no_index/) ) sep="\""
else sep = "'"
if( arch_value_array[i] !~ sep)
if( arch_value_array[i] !~ sep)
arch_value_array[i] = sep arch_value_array[i] sep
}
printf "%s"," := " arch_value_array[i]
@ -373,7 +373,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
actual_port_mult=split(inst_actual_port[j],actual_port_array,",")
}
else {
actual_port_mult=1
actual_port_mult=1
actual_port_array[1]=inst_actual_port[j]
}
ck2[j] = check2(actual_port_array,actual_port_mult)
@ -392,21 +392,21 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
actual_port_mult=split(inst_actual_port[j],actual_port_array,",")
}
else {
actual_port_mult=1
actual_port_mult=1
actual_port_array[1]=inst_actual_port[j]
}
# force to actual multiplicty unresolved (due to params) symbol pin multiplicity
parametrized_formal_range=0 # 20100408
if(inst_formal_port_mult[j]<0) {
parametrized_formal_range=1 # 20100408
parametrized_formal_range=1 # 20100408
inst_formal_port_mult[j] = actual_port_mult
inst_formal_up[j] = actual_port_mult -1 #assume inst_formal_low=0 in case of parametrized vector port...
}
a=((i-1)*inst_formal_port_mult[j]) % actual_port_mult+1
b=(-1+i*inst_formal_port_mult[j]) % actual_port_mult+1
#print "\n-- a=" a " b=" b " formal port mult=" inst_formal_port_mult[j]
#print "\n-- a=" a " b=" b " formal port mult=" inst_formal_port_mult[j]
if(j>0 && j!=g) printf " ,\n"
else if(j>0) printf "\n"
if(inst_formal_port_mult[j]>1 && actual_port_mult>1 && ck2[j]) {
@ -438,13 +438,13 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
# 20100408 if formal range contains generic and actual port width is 1 specify formal bit index in assignment
if( (parametrized_formal_range || (inst_formal_port_mult[j]>1)) && actual_port_mult==1) {
# patch for single bit actual port
# patch for single bit actual port
# assigned on vector formal port 23112002
# 20170920
if( parametrized_formal_range && inst_actual_port[j] ~/\[.*:.*\]/) {
printf "%s"," " inst_formal_port[j] " => " get_number(actual_port)
} else
printf "%s"," " inst_formal_port[j] " => " get_number(actual_port)
} else
# /20170920
for(num=inst_formal_low[j]; ; num+=sign(inst_formal_up[j] - inst_formal_low[j])) {
if(num !=inst_formal_low[j]) printf " ,\n"
@ -459,7 +459,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
formal_index= (inst_formal_up[j] >= inst_formal_low[j]) ? \
remainder(inst_formal_up[j]-num+1+inst_formal_low[j], inst_formal_port_mult[j]) + inst_formal_low[j]: \
remainder(inst_formal_up[j]+num-1+inst_formal_up[j] , inst_formal_port_mult[j]) + inst_formal_up[j]
if(num !=a) printf " ,\n"
#07062002 aggiunto get_number x generici
printf "%s"," " inst_formal_port[j] "(" formal_index ") => " to_round_brackets(get_number(actual_port_array[num]))
@ -487,7 +487,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
sub(/^.*:/,"",index_low)
sub(/\].*$/,"",index_low)
if( (index_up !~/^[0-9]+$/) || (index_low !~/^[0-9]+$/) ) {
inst_formal_port_mult[p]=-1 # component port index contains parameter, multiplicity cant be resolved
inst_formal_port_mult[p]=-1 # component port index contains parameter, multiplicity cant be resolved
inst_formal_up[p]=0
inst_formal_low[p]=0
}
@ -495,7 +495,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
inst_formal_port_mult[p] = abs(index_up - index_low) + 1
inst_formal_up[p]=index_up
inst_formal_low[p]=index_low
#print "--port assignment: port " s_b($1) " formal idx hi=" index_up " lo=" index_low
#print "--port assignment: port " s_b($1) " formal idx hi=" index_up " lo=" index_low
}
}
else {
@ -503,7 +503,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
inst_formal_up[p]=0
inst_formal_low[p]=0
}
# if formal port = a[2:2] translate as a(2)
# if formal port = a[2:2] translate as a(2)
if(index_up == index_low && $1 ~ /\[.*:.*\]/)
inst_formal_port[p] = s_b($1) "(" index_up ")"
else
@ -522,7 +522,7 @@ primitive==1{primitive_line=primitive_line " " $0; next } # 20071217
port_map=1
no_print=1
}
/^port map/{
if(!port_map){
@ -553,9 +553,9 @@ function remainder(n,div, x) {
x=n%div
if(x<o) return x+div
return x
}
}
function abs(x)
function abs(x)
{
if(x+0<0) return -x
else return x
@ -618,13 +618,13 @@ function check(arr,n ,i,start,ok)
return 1
}
# check if an array of indexes (sig[3]) arr[1],arr[2].....
# check if an array of indexes (sig[3]) arr[1],arr[2].....
# is contigous and decreeasing
function check2(arr,n ,a,name,i,start,ok)
{
name=s_b(arr[1])
start=s_i(arr[1])
if(arr[1] !~ /[0-9]+/)
if(arr[1] !~ /[0-9]+/)
{
if(n>1) return 0
else return 1
@ -645,7 +645,7 @@ function check2(arr,n ,a,name,i,start,ok)
}
return 1
}
function s_i(a)
{
sub(/.*\[/,"",a)
@ -701,24 +701,24 @@ function compact_pinlist(pin, dir ,i,ii,base,curr,curr_n,np)
delete pin_ret
delete net_ret
delete dir_ret
np=pin["n"]
if(np) {
ii=1
for(i=1;i<=np;i++) {
base =s_b( pin[i] )
if(i==1) {curr=base; curr_n=i}
else {
else {
if(base != curr) {
pin_ret[ii] = compact_label(pin,curr_n,i-1)
dir_ret[ii] = dir[i-1]
dir_ret[ii] = dir[i-1]
ii++
curr=base;curr_n=i
}
}
}
pin_ret[ii] = compact_label(pin,curr_n,np)
dir_ret[ii] = dir[np]
dir_ret[ii] = dir[np]
pin_ret["n"] = dir_ret["n"] = ii
}
}
@ -737,10 +737,10 @@ function compact_label(ar,a,b, ret,start,i)
else {ret = ret ar[i-1] ","; start=i }
}
}
else if(s_b(ar[i])!=s_b(ar[i-1]) ||
( lab_index(ar[i]) != lab_index(ar[i-1])-1 &&
else if(s_b(ar[i])!=s_b(ar[i-1]) ||
( lab_index(ar[i]) != lab_index(ar[i-1])-1 &&
lab_index(ar[i]) != lab_index(ar[i-1])+1) ) {
if(start<i-1)
if(start<i-1)
ret = ret s_b(ar[start]) "[" lab_index(ar[start]) ":" lab_index(ar[i-1]) "],"
else
ret = ret s_b(ar[start]) "[" lab_index(ar[start]) "],"
@ -752,7 +752,7 @@ function compact_label(ar,a,b, ret,start,i)
if(start < b) ret = ret (b-start+1) "*" ar[b]
else ret = ret ar[b]
}
else if(start<b)
else if(start<b)
ret = ret s_b(ar[start]) "[" lab_index(ar[start]) ":" lab_index(ar[b]) "]"
else
ret = ret s_b(ar[b]) "[" lab_index(ar[b]) "]"

28
src/vhdl_netlist.c
View File

@ -134,7 +134,7 @@ int global_vhdl_netlist(int global, int alert) /* netlister driver */
xctx->netlist_count=0;
str_hash_init(&subckt_table, HASHSIZE);
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
my_snprintf(netl_filename, S(netl_filename), "%s/.%s_%d",
tclgetvar("netlist_dir"), get_cell(xctx->sch[xctx->currsch], 0), getpid());
fd=fopen(netl_filename, "w");
@ -569,7 +569,7 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "package") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
}
dbg(1, "vhdl_block_netlist(): use statements\n");
for(l=0;l<xctx->instances; ++l)
{
@ -578,11 +578,11 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
if( !strcmp((xctx->inst[l].ptr+ xctx->sym)->type, "use") )
fprintf(fd, "%s\n", xctx->inst[l].prop_ptr);
}
dbg(1, "vhdl_block_netlist(): entity generics\n");
/* print entity generics */
print_generic(fd, "entity", i);
dbg(1, "vhdl_block_netlist(): entity ports\n");
/* print entity ports */
tmp=0;
@ -611,7 +611,7 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
}
int_hash_free(&table);
if(tmp) fprintf(fd, "\n);\n");
dbg(1, "vhdl_block_netlist(): port attributes\n");
for(l=0;l<xctx->instances; ++l)
{
@ -623,14 +623,14 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
}
}
fprintf(fd,"end %s ;\n\n", get_cell(sanitize(xctx->sym[i].name), 0) );
dbg(1, "vhdl_block_netlist(): architecture\n");
fprintf(fd,"architecture arch_%s of %s is\n\n",
get_cell(sanitize(xctx->sym[i].name), 0),
get_cell(sanitize(xctx->sym[i].name), 0) );
/* get_cell( xctx->sch[xctx->currsch], 0), get_cell( xctx->sch[xctx->currsch], 0)); */
/* load current schematic to print used components */
dbg(1, "vhdl_block_netlist(): used components\n");
/* print all components */
if(!vhdl_stop) {
@ -642,14 +642,14 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
default_schematic = get_tok_value(xctx->sym[i].prop_ptr, "default_schematic", 0);
if(!strcmp(default_schematic, "ignore")) continue;
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
if(!xctx->sym[j].type || (strcmp(xctx->sym[j].type,"primitive")!=0 &&
strcmp(xctx->sym[j].type,"subcircuit")!=0))
continue;
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
if(( strcmp(xctx->sym[j].type,"subcircuit")==0 || strcmp(xctx->sym[j].type,"primitive")==0) &&
if(( strcmp(xctx->sym[j].type,"subcircuit")==0 || strcmp(xctx->sym[j].type,"primitive")==0) &&
check_lib(1, abs_path)
) {
/* only print component declaration if used in current subcircuit */
found=0;
for(l=0;l<xctx->instances; ++l)
@ -673,7 +673,7 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
get_tok_value( xctx->sym[j].rect[PINLAYER][k].prop_ptr,"sig_type",0));
my_strdup(_ALLOC_ID_, &port_value,
get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"value", 0) );
if(!sig_type || sig_type[0]=='\0') my_strdup(_ALLOC_ID_, &sig_type,"std_logic");
my_strdup(_ALLOC_ID_, &dir_tmp, get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"dir",0) );
str_tmp = get_tok_value(xctx->sym[j].rect[PINLAYER][k].prop_ptr,"name",0);
@ -698,18 +698,18 @@ int vhdl_block_netlist(FILE *fd, int i, int alert)
dbg(1, "vhdl_block_netlist(): netlisting %s\n", get_cell( xctx->sch[xctx->currsch], 0));
err |= vhdl_netlist(fd, vhdl_stop);
fprintf(fd,"//// begin user architecture code\n");
for(l=0;l<xctx->instances; ++l) {
if(skip_instance(l, 1, lvs_ignore)) continue;
if(xctx->netlist_count &&
!strboolcmp(get_tok_value(xctx->inst[l].prop_ptr, "only_toplevel", 0), "true")) continue;
my_strdup(_ALLOC_ID_, &type,(xctx->inst[l].ptr+ xctx->sym)->type);
if(type && !strcmp(type,"netlist_commands")) {
fprintf(fd, "%s\n", get_tok_value(xctx->inst[l].prop_ptr,"value", 0));
}
}
if(xctx->schvhdlprop && xctx->schvhdlprop[0]) fprintf(fd, "%s\n", xctx->schvhdlprop);
fprintf(fd, "end arch_%s ;\n\n", get_cell(sanitize(xctx->sym[i].name), 0) );
my_free(_ALLOC_ID_, &sig_type);

162
src/xinit.c
View File

@ -91,16 +91,16 @@ Xschem_ctx **get_save_xctx(void)
* window_path[1] = .x3.drw
* window_path[2] = .x4.drw
* ...
*/
*/
char *get_window_path(int i)
{
return window_path[i];
}
Xschem_ctx *get_old_xctx(void)
{
{
return old_xctx;
}
}
int get_last_created_window(void)
@ -344,7 +344,7 @@ void init_pixdata()/* populate xctx->fill_type array that is used in create_gc()
const char *tclpixdata;
const char *tclword;
int found_data;
for(i=0;i<cadlayers; ++i) {
tclpixdata = Tcl_GetVar2(interp, "pixdata", my_itoa(i), TCL_GLOBAL_ONLY);
dbg(1, "pixdata(%d)=%s\n", i, tclpixdata);
@ -423,7 +423,7 @@ static void free_xschem_data()
if(xctx->hier_attr[i].symname) my_free(_ALLOC_ID_, &xctx->hier_attr[i].symname);
if(xctx->hier_attr[i].sym_extra) my_free(_ALLOC_ID_, &xctx->hier_attr[i].sym_extra);
}
my_free(_ALLOC_ID_, &xctx->gridpoint);
my_free(_ALLOC_ID_, &xctx->biggridpoint);
my_free(_ALLOC_ID_, &xctx->gc);
@ -725,7 +725,7 @@ static void delete_schematic_data(int delete_pixmap)
{
dbg(1, "delete_schematic_data()\n");
unselect_all(1);
/* clear static data in get_tok_value() must be done after unselect_all(1)
/* clear static data in get_tok_value() must be done after unselect_all(1)
* as this functions re-uses get_tok_value() */
parse_cmd_string(NULL, NULL); /* clear static data in function */
get_tok_value(NULL, NULL, 0); /* clear static data in function */
@ -738,7 +738,7 @@ static void delete_schematic_data(int delete_pixmap)
resetwin(0, 1, 1, 0, 0); /* delete preview pixmap, delete cairo surfaces */
if(has_x) free_gc();
}
/* delete instances, wires, lines, rects, arcs, polys, texts, hash_inst, hash_wire,
/* delete instances, wires, lines, rects, arcs, polys, texts, hash_inst, hash_wire,
* inst & wire .node fields, instance name hash */
remove_symbols();
str_replace(NULL, NULL, NULL, 0, -1);
@ -784,7 +784,7 @@ int compare_schematics(const char *f)
l = 1024 + strlen(xctx->inst[i].prop_ptr ? xctx->inst[i].prop_ptr : "");
my_realloc(_ALLOC_ID_, &s, l);
my_snprintf(s, l, "C %s %g %g %d %d %s", tcl_hook2(xctx->inst[i].name),
xctx->inst[i].x0, xctx->inst[i].y0, xctx->inst[i].rot, xctx->inst[i].flip,
xctx->inst[i].x0, xctx->inst[i].y0, xctx->inst[i].rot, xctx->inst[i].flip,
xctx->inst[i].prop_ptr ? xctx->inst[i].prop_ptr : "");
int_hash_lookup(&table1, s, i, XINSERT_NOREPLACE);
}
@ -800,10 +800,10 @@ int compare_schematics(const char *f)
/* save old xctx and create new xctx for compare schematic */
save_xctx = xctx;
xctx = NULL;
xctx = NULL;
alloc_xschem_data("", ".drw");
xctx->netlist_type = CAD_SPICE_NETLIST;
tclsetvar("netlist_type","spice");
tclsetvar("netlist_type","spice");
init_pixdata(); /* populate xctx->fill_type array that is used in create_gc() to set fill styles */
/* draw in same window */
xctx->window = save_xctx->window;
@ -846,7 +846,7 @@ int compare_schematics(const char *f)
l = 1024 + strlen(xctx->inst[i].prop_ptr ? xctx->inst[i].prop_ptr : "");
my_realloc(_ALLOC_ID_, &s, l);
my_snprintf(s, l, "C %s %g %g %d %d %s", tcl_hook2(xctx->inst[i].name),
xctx->inst[i].x0, xctx->inst[i].y0, xctx->inst[i].rot, xctx->inst[i].flip,
xctx->inst[i].x0, xctx->inst[i].y0, xctx->inst[i].rot, xctx->inst[i].flip,
xctx->inst[i].prop_ptr ? xctx->inst[i].prop_ptr : "");
int_hash_lookup(&table2, s, i, XINSERT_NOREPLACE);
found = int_hash_lookup(&table1, s, i, XLOOKUP);
@ -1002,21 +1002,21 @@ static void xwin_exit(void)
}
/*
/*
* color structures in xschem:
* - char *xctx->color_array[]:
* - char *xctx->color_array[]:
* array of color character names ("#xxxxxx" hex) indexed by xschem layer number.
* these are set from tcl 'color' list variable in init_color_array()
* - unsigned int xctx->color_index[]:
* - unsigned int xctx->color_index[]:
* array of integers, pixel values, color lookup table, indexed by xschem layer num.
* this array is initialized in build_colors() by calling find_best_color()
* indexes are returned from XAllocNamedColor()
* these are used in XSetForeground and XSetBackground calls:
* XSetForeground(display, gc, xctx->color_index[i])
* - XColor xctx->xcolor_array[]:
* XSetForeground(display, gc, xctx->color_index[i])
* - XColor xctx->xcolor_array[]:
* array of 256 XColor structures:
* typedef struct {
* unsigned long pixel; // pixel value
* unsigned long pixel; // pixel value
* unsigned short red, green, blue; // rgb values
* char flags; // DoRed, DoGreen, DoBlue
* char pad;
@ -1184,7 +1184,7 @@ void toggle_fullscreen(const char *topwin)
} else {
xctx->pending_fullzoom=1;
window_state(display , parent_id,normal); /* normal view */
/* when switching back from fullscreen multiple ConfigureNotify events are generated.
/* when switching back from fullscreen multiple ConfigureNotify events are generated.
* pending_fullzoom does not work on the last correct ConfigureNotify event,
* so we zoom_full() again */
}
@ -1202,7 +1202,7 @@ static int source_tcl_file(char *s)
{
char tmp[1024];
if(Tcl_EvalFile(interp, s)==TCL_ERROR) {
fprintf(errfp, "Tcl_AppInit() error: can not execute %s, please fix:\n", s);
fprintf(errfp, "%s", tclresult());
#if TCL_MAJOR_VERSION >= 8 && TCL_MINOR_VERSION >=6
@ -1244,7 +1244,7 @@ int preview_window(const char *what, const char *win_path, const char *fname)
* and an Expose event calls another preview draw */
if(semaphore) return 0;
++semaphore;
dbg(1, "preview_window(): what=%s, win_path=%s, fname=%s\n",
dbg(1, "preview_window(): what=%s, win_path=%s, fname=%s\n",
what, win_path ? win_path : "<NULL>", fname ? fname : "<NULL>");
dbg(1, "------\n");
if(!strcmp(what, "create") && last_preview < 4) {
@ -1274,7 +1274,7 @@ int preview_window(const char *what, const char *win_path, const char *fname)
if(i < 10) {
save_xctx = xctx; /* save current schematic */
xctx = preview_xctx[i];
if(fname && fname[0] && (!current_file[i] || strcmp(fname, current_file[i])) ) {
if(fname && fname[0] && (!current_file[i] || strcmp(fname, current_file[i])) ) {
if(current_file[i]) {
delete_schematic_data(1);
}
@ -1395,7 +1395,7 @@ void swap_tabs(void)
ctx = save_xctx[i];
save_xctx[i] = save_xctx[j];
save_xctx[j] = ctx;
/* update filenames on tab buttons */
ctx = xctx;
xctx = save_xctx[i];
@ -1410,7 +1410,7 @@ void swap_tabs(void)
}
/* swap primary view (.drw) with first valid window (x1.drw, x2.drw, ...)
* used for window close ('xschem exit' command)
* used for window close ('xschem exit' command)
* if dr == 1 do draw and don't move following window onto first. This is used if
* primary windows is about to be deleted */
void swap_windows(int dr)
@ -1472,7 +1472,7 @@ void swap_windows(int dr)
if(!dr) tclvareval("wm withdraw .; update; wm geometry . ", geometry, "; wm deiconify .", NULL);
resetwin(1, 1, 1, 0, 0);
if(dr) draw();
new_schematic("switch", wp_j, "", 0);
resetwin(1, 1, 1, 0, 0);
@ -1489,7 +1489,7 @@ void swap_windows(int dr)
/* window_path[1] == ".x1.drw" */
/* .... */
int check_loaded(const char *f, char *win_path)
{
{
int i;
Xschem_ctx *ctx;
int found = 0;
@ -1553,7 +1553,7 @@ static int switch_window(int *window_count, const char *win_path, int tcl_ctx)
}
/* if window was closed then tkwin == 0 --> do nothing */
if((!has_x || (tkwin && has_x)) && n >= 0 && n < MAX_NEW_WINDOWS) {
if(tcl_ctx) tclvareval("save_ctx ", xctx->current_win_path, NULL);
xctx = save_xctx[n];
if(tcl_ctx) {
@ -1571,7 +1571,7 @@ static int switch_window(int *window_count, const char *win_path, int tcl_ctx)
/* win_path: .drw for main (first) tab, .x1.drw, ... for additional tabs */
static int switch_tab(int *window_count, const char *win_path, int dr)
{
{
int n;
int save_menu_removed, save_fullscreen, save_toolbar_visible;
const char *new_path = win_path;
@ -1588,7 +1588,7 @@ static int switch_tab(int *window_count, const char *win_path, int dr)
}
else return 1;
}
if(!strcmp(new_path, xctx->current_win_path)) return 0; /* already there */
n = get_tab_or_window_number(new_path);
if(n == -1) {
@ -1640,7 +1640,7 @@ static void create_new_window(int *window_count, const char *win_path, const cha
int i, n, confirm = 1;
dbg(1, "new_schematic() create: fname=%s *window_count = %d\n", fname, *window_count);
if(win_path && win_path[0]) confirm = 0;
my_strncpy(prev_window, xctx->current_win_path, S(prev_window));
if(confirm && fname && fname[0] && check_loaded(fname, toppath)) {
@ -1733,8 +1733,8 @@ static void create_new_window(int *window_count, const char *win_path, const cha
tclvareval("save_ctx ", window_path[n], NULL);
tcleval("eval_user_startup_commands");
/* restore previous context,
* because the Expose event after new window creation does a context switch prev win -> new win
*
* because the Expose event after new window creation does a context switch prev win -> new win
*
* tclvareval("restore_ctx ", prev_window, NULL);
* new_schematic("switch", prev_window, "", 1);
*/
@ -1811,7 +1811,7 @@ static void create_new_tab(int *window_count, const char *noconfirm, const char
tclvareval(
"if {![info exists tctx::tab_bg] } {set tctx::tab_bg [",
".tabs.x", nn, " cget -bg]}", NULL);
tclvareval("pack ", ".tabs.x", nn,
tclvareval("pack ", ".tabs.x", nn,
" -before ", ".tabs.add -side left", NULL);
}
/* */
@ -1977,7 +1977,7 @@ static void destroy_tab(int *window_count, const char *win_path)
/* seems unnecessary; previous tab save_pixmap was not deleted */
/* resetwin(1, 0, 0, 0, 0); */ /* create pixmap. resetwin(create_pixmap, clear_pixmap, force, w, h) */
if(xctx->current_win_path)
tclvareval("restore_ctx ", xctx->current_win_path, " ; housekeeping_ctx", NULL);
resetwin(1, 1, 1, 0, 0);
@ -2004,7 +2004,7 @@ static void destroy_all_windows(int *window_count, int force)
tkwin = Tk_NameToWindow(interp, window_path[i], mainwindow); /* NULL if win_path not existing */
}
if(has_x && !tkwin) dbg(0, "new_schematic(\"switch\",...): Warning: %s has been destroyed\n", window_path[i]);
else {
else {
xctx = save_xctx[i];
close = 0;
xctx->semaphore++; /* to avoid context switches when dialog below is shown */
@ -2163,7 +2163,7 @@ void change_linewidth(double w)
dbg(1, "Line width = %d\n", linew);
for(i=0;i<cadlayers; ++i) {
XSetLineAttributes(display, xctx->gc[i], linew, LineSolid, LINECAP , LINEJOIN);
}
}
XSetLineAttributes (display, xctx->gctiled, linew, LineSolid, LINECAP , LINEJOIN);
}
if(!xctx->only_probes) {
@ -2207,11 +2207,11 @@ void create_memory_cairo_ctx(int what)
/* clears and creates cairo_sfc, cairo_ctx, cairo_save_sfc, cairo_save_ctx
* and sets some graphical attributes */
static void resetcairo(int create, int clear, int force_or_resize)
{
{
#if HAS_CAIRO==1
dbg(1, "resetcairo() %d, %d, %d\n", create, clear, force_or_resize);
if(clear && force_or_resize) {
/* xctx->cairo_save_sfc is based on pixmap and pixmaps are not resizeable, so on resize
/* xctx->cairo_save_sfc is based on pixmap and pixmaps are not resizeable, so on resize
* we must destroy & recreate everything. xctx->cairo_sfc can be resized using cairo_*_surface_set_size
* being based on window */
cairo_destroy(xctx->cairo_save_ctx);
@ -2288,7 +2288,7 @@ void resetwin(int create_pixmap, int clear_pixmap, int force, int w, int h)
#else
XWindowAttributes wattr;
#endif
dbg(1, "\nresetwin(): %s create=%d, clear=%d, force=%d, w=%d, h=%d\n",
dbg(1, "\nresetwin(): %s create=%d, clear=%d, force=%d, w=%d, h=%d\n",
xctx->current_win_path, create_pixmap, clear_pixmap, force, w, h);
if(w && h) {
width = w;
@ -2361,7 +2361,7 @@ void resetwin(int create_pixmap, int clear_pixmap, int force, int w, int h)
XSetTile(display,xctx->gctiled, xctx->save_pixmap);
XSetFillStyle(display,xctx->gctiled,FillTiled);
}
/* whenever a pixmap is recreated all GC attributes must be reissued */
resetcairo(1, 0, 1); /* create, clear, force */
change_linewidth(-1.0);
@ -2370,7 +2370,7 @@ void resetwin(int create_pixmap, int clear_pixmap, int force, int w, int h)
}
if(xctx->pending_fullzoom > 0 && create_pixmap) {
tcleval("winfo ismapped .");
/* if window unmapped or size has not been set by wm (width == 1 // height == 1) do not
/* if window unmapped or size has not been set by wm (width == 1 // height == 1) do not
* perform the pending full_zoom */
if(tclresult()[0] == '1' && (width > 1 || height > 1) ) {
dbg(1, "resetwin(): window mapped, pending_fulzoom: doing zoom_full()\n");
@ -2452,7 +2452,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
found_sharedir = 1;
dbg(1, "Using environment XSCHEM_SHAREDIR = %s\n", xschem_sharedir);
}
/* Priority 2: Executable-relative detection using argv[0] */
if(!found_sharedir && xschem_executable) {
/* Use argv[0] for C89 compatibility - more portable than /proc/self/exe */
@ -2467,14 +2467,14 @@ int Tcl_AppInit(Tcl_Interp *inter)
last_slash = strrchr(exe_path, '/');
if(last_slash) {
*last_slash = '\0'; /* exe_path now contains directory */
/* Convert relative path to absolute if needed */
if(exe_path[0] != '/') { /* 'path/to/xschem' was called */
char abs_path[PATH_MAX];
my_snprintf(abs_path, sizeof(abs_path), "%s/%s", pwd_dir, exe_path);
my_strncpy(exe_path, abs_path, sizeof(exe_path));
}
/* Check if running from source directory */
my_snprintf(tmp, S(tmp), "%s/xschem.tcl", exe_path);
if(!stat(tmp, &buf)) {
@ -2485,7 +2485,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
dbg(1, "Detected source XSCHEM_SHAREDIR = %s\n", exe_path);
}
}
/* Check installed location (bin/../share/xschem) */
if(!found_sharedir) {
last_slash = strrchr(exe_path, '/');
@ -2506,20 +2506,20 @@ int Tcl_AppInit(Tcl_Interp *inter)
}
}
}
/* Priority 3: Legacy current directory check */
if(!found_sharedir && !stat("./xschem.tcl", &buf) && !stat("./systemlib", &buf) && !stat("./xschem", &buf)) {
tclsetvar("XSCHEM_SHAREDIR",pwd_dir);
found_sharedir = 1;
dbg(1, "Using current directory XSCHEM_SHAREDIR = %s\n", pwd_dir);
}
/* Priority 4: Compile-time fallback */
if(!found_sharedir) {
tclsetvar("XSCHEM_SHAREDIR", XSCHEM_SHAREDIR);
dbg(1, "Using compile-time XSCHEM_SHAREDIR = %s\n", XSCHEM_SHAREDIR);
}
/* build TCL XSCHEM_LIBRARY_PATH from const array of strings xschem_library_path */
tcleval("set XSCHEM_LIBRARY_PATH {}");
for(i = 0;; i++) {
@ -2543,54 +2543,54 @@ int Tcl_AppInit(Tcl_Interp *inter)
running_in_src_dir = 1;
/* set builtin library path if running in src/ */
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"set XSCHEM_LIBRARY_PATH %s/xschem_library", user_conf_dir);
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/devices",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/examples",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/ngspice",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/ngspice_verilog_cosim",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/logic",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/xschem_simulator",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/generators",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/inst_sch_select",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/binto7seg",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/pcb",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/rom8k",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
my_snprintf(tmp, S(tmp),
my_snprintf(tmp, S(tmp),
"append XSCHEM_LIBRARY_PATH : [file dirname \"%s\"]/xschem_library/analyses",
tclgetvar("XSCHEM_SHAREDIR"));
tcleval(tmp);
@ -2601,16 +2601,16 @@ int Tcl_AppInit(Tcl_Interp *inter)
#define WIN_XSCHEM_LIBRARY_PATH_NUM 12
const char *WIN_XSCHEM_LIBRARY_PATH[WIN_XSCHEM_LIBRARY_PATH_NUM] = {
/*1*/ "xschem_library",
/*2*/ "xschem_library/devices",
/*2*/ "xschem_library/devices",
/*3*/ "examples", /* See i==2 with WIN_XSCHEM_LIBRARY_PATH_NUM below */
/*4*/ "ngspice",
/*5*/ "ngspice_verilog_cosim",
/*6*/ "logic",
/*4*/ "ngspice",
/*5*/ "ngspice_verilog_cosim",
/*6*/ "logic",
/*7*/ "xschem_simulator",
/*8*/ "generators",
/*9*/ "inst_sch_select",
/*10*/ "binto7seg",
/*11*/ "pcb",
/*8*/ "generators",
/*9*/ "inst_sch_select",
/*10*/ "binto7seg",
/*11*/ "pcb",
/*12*/ "rom8k" };
GetModuleFileNameA(NULL, install_dir, MAX_PATH);
change_to_unix_fn(install_dir);
@ -2634,16 +2634,16 @@ int Tcl_AppInit(Tcl_Interp *inter)
{
my_free(_ALLOC_ID_, &up_hier);
if (running_in_src_dir==0)
my_strdup(_ALLOC_ID_, &up_hier, "../share/doc/xschem");
my_strdup(_ALLOC_ID_, &up_hier, "../share/doc/xschem");
else
my_strdup(_ALLOC_ID_, &up_hier, "../../../xschem_library");
my_strdup(_ALLOC_ID_, &up_hier, "../../../xschem_library");
}
my_snprintf(tmp, S(tmp),"%s/%s/%s", install_dir, up_hier, WIN_XSCHEM_LIBRARY_PATH[i]);
if (i > 0) my_strcat(_ALLOC_ID_, &win_xschem_library_path, "\;");
if (i > 0) my_strcat(_ALLOC_ID_, &win_xschem_library_path, "\;");
my_strcat(_ALLOC_ID_, &win_xschem_library_path, tmp);
}
my_snprintf(tmp, S(tmp), "set tmp2 {%s}; "
"while {[regsub {([^/]*\\.*[^./]+[^/]*)/\\.\\./?} $tmp2 {} tmp2]} {}; ", win_xschem_library_path);
"while {[regsub {([^/]*\\.*[^./]+[^/]*)/\\.\\./?} $tmp2 {} tmp2]} {}; ", win_xschem_library_path);
const char *result2 = tcleval(tmp);
const char *win_xschem_library_path_clean = tclgetvar("tmp2");
tclsetvar("XSCHEM_LIBRARY_PATH", win_xschem_library_path_clean);
@ -2692,14 +2692,14 @@ int Tcl_AppInit(Tcl_Interp *inter)
fprintf(errfp, "Tcl_AppInit(): failure creating %s\n", user_conf_dir);
Tcl_Exit(EXIT_FAILURE);
}
}
fprintf(errfp, "Using run time directory XSCHEM_SHAREDIR = %s\n", tclgetvar("XSCHEM_SHAREDIR"));
/* Execute tcl script given on command line with --preinit, before sourcing xschemrc */
if(cli_opt_preinit_command) {
tcleval(cli_opt_preinit_command);
}
/* */
/* SOURCE xschemrc file */
/* */
@ -2968,7 +2968,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
} else {
my_strncpy(xctx->current_dirname, pwd_dir, S(xctx->current_dirname));
}
/* */
/* X INITIALIZATION */
@ -3113,9 +3113,9 @@ int Tcl_AppInit(Tcl_Interp *inter)
if(cli_opt_diff[0]) {
my_strncpy(xctx->sch_to_compare, abs_sym_path(cli_opt_diff, ""), S(xctx->sch_to_compare));
tclsetvar("compare_sch", "1");
}
}
/* must be before source_user_tcl_files, so event bindings defined there
/* must be before source_user_tcl_files, so event bindings defined there
* will be correctly appended to default bindings */
tcleval("set_bindings .drw");
@ -3140,7 +3140,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
if(cli_opt_filename[0]) {
int file_loaded = 1;
/* check if local_netlist_dir is set and set netlist_dir accordingly
* following call is needed since load_schematic() may be called with
* following call is needed since load_schematic() may be called with
* reset_undo=0 and will not call set_netlist_dir */
set_netlist_dir(2, NULL);
#ifdef __unix__
@ -3158,7 +3158,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
#endif
dbg(1, "Tcl_AppInit(): cli_opt_filename %s given, removing symbols\n", cli_opt_filename);
remove_symbols();
/* if cli_opt_do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
/* if cli_opt_do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
to tcl is_xschem_file that could change xctx->netlist_type to symbol */
file_loaded = load_schematic(1, fname, !cli_opt_do_netlist, 1);
if(cli_opt_do_netlist) if(!file_loaded) tcleval("exit 1");
@ -3174,7 +3174,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
#endif
dbg(1, "Tcl_AppInit(): tmp=%s\n", tmp? tmp: "<NULL>");
my_strncpy(fname, abs_sym_path(tmp, ""), S(fname));
/* if cli_opt_do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
/* if cli_opt_do_netlist=1 call load_schematic with 'reset_undo=0' avoiding call
to tcl is_xschem_file that could change xctx->netlist_type to symbol */
file_loaded = load_schematic(1, fname, !cli_opt_do_netlist, 1);
if(!file_loaded) tcleval("exit 1");
@ -3307,7 +3307,7 @@ int Tcl_AppInit(Tcl_Interp *inter)
"::tclreadline::readline builtincompleter 0; "
"::tclreadline::readline customcompleter completer; "
"::tclreadline::Loop"
"}"
"}"
);
}
/* set up a tcl event handler to serve events (tcp connections) if no other

1034
src/xschem.tcl
View File

File diff suppressed because it is too large Load Diff

2
tests/cleanup_debug_file.awk
View File

@ -76,5 +76,5 @@ function endfile(f, i)
}
close(f)
}
}
}

12
tests/create_save.tcl
View File

@ -1,21 +1,21 @@
#
# File: create_save.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2022 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -55,7 +55,7 @@ proc create_save {} {
lappend pathlist "${filename}.sch"
cleanup_debug_file ${results_dir}/$output
cleanup_debug_file ${results_dir}/$fn_sch
}
}
}
}
}

16
tests/create_save/tests/0_examples_top.tcl
View File

@ -1,11 +1,11 @@
xschem line 910 -560 960 -540
xschem line 880 -680 1200 -680
xschem line 900 -540 950 -560
xschem line 900 -550 950 -530
xschem line 910 -530 960 -550
xschem rect 940 -510 960 -450
xschem rect 900 -490 970 -470
xschem rect 910 -510 930 -450
xschem line 910 -560 960 -540
xschem line 880 -680 1200 -680
xschem line 900 -540 950 -560
xschem line 900 -550 950 -530
xschem line 910 -530 960 -550
xschem rect 940 -510 960 -450
xschem rect 900 -490 970 -470
xschem rect 910 -510 930 -450
xschem wire 870 -300 990 -300 {lab=#net1}
xschem wire 910 -340 910 -250 {lab=#net2}
xschem wire 910 -270 970 -270 {lab=#net2}

26
tests/create_save/tests/pcb_voltage_protection.tcl
View File

@ -37,20 +37,20 @@ vvss vss 0 dc 0
* .tran 5u 7m uic
** models are generally not free: you must download
** SPICE models for active devices and put them into the below
** SPICE models for active devices and put them into the below
** referenced file in netlist/simulation directory.
.include \\"models_pcb_voltage_protection.txt\\"
.dc VVCC 0 8 0.004
.save all
"}
xschem instance ../xschem_library/devices/pnp.sym 580 -390 0 0 {name=Q6
model=BC857
device=BC857
xschem instance ../xschem_library/devices/pnp.sym 580 -390 0 0 {name=Q6
model=BC857
device=BC857
footprint=SOT23
url="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=2ahUKEwijlfagu4zfAhUN0xoKHTPBAb0QFjAAegQIAhAC&url=http%3A%2F%2Fwww.onsemi.com%2Fpub%2FCollateral%2FPN2907-D.PDF&usg=AOvVaw2wgr87fGZgGfBRhXzHGwZM"}
xschem instance ../xschem_library/devices/zener.sym 330 -190 2 0 {name=x3
model=BZX5V1
device=BZX5V1
model=BZX5V1
device=BZX5V1
footprint=acy(300)
xxxspiceprefix="#D#"}
xschem instance ../xschem_library/devices/gnd.sym 330 -130 0 0 {name=l13 lab=VSS}
@ -61,9 +61,9 @@ xschem instance ../xschem_library/devices/res.sym 600 -190 0 0 {name=R5 m=1 valu
xschem instance ../xschem_library/devices/gnd.sym 600 -130 0 0 {name=l16 lab=VSS}
xschem instance ../xschem_library/devices/lab_wire.sym 360 -390 0 0 {name=l0 lab=B}
xschem instance ../xschem_library/devices/res.sym 330 -340 0 0 {name=R2 m=1 value=510 footprint=1206 device=resistor}
xschem instance ../xschem_library/devices/pmos.sym 750 -360 0 0 {name=M2
model=IRLML6402
device=IRLML6402
xschem instance ../xschem_library/devices/pmos.sym 750 -360 0 0 {name=M2
model=IRLML6402
device=IRLML6402
footprint=SOT23
spiceprefix=X
m=1
@ -72,11 +72,11 @@ xschem instance ../xschem_library/devices/led.sym 650 -290 0 0 {name=x1 model=D1
xschem instance ../xschem_library/devices/lab_pin.sym 170 -340 0 1 {name=p6 lab=VOUT}
xschem instance ../xschem_library/devices/lab_pin.sym 170 -360 0 1 {name=p7 lab=VSS}
xschem instance ../xschem_library/devices/lab_pin.sym 170 -380 0 1 {name=p8 lab=VCC}
xschem instance ../xschem_library/devices/zener.sym 250 -190 2 0 {name=x4
model=BZX5V1
xschem instance ../xschem_library/devices/zener.sym 250 -190 2 0 {name=x4
model=BZX5V1
device=BZX5V1
area=1
footprint=minimelf
area=1
footprint=minimelf
spice_ignore=true}
xschem instance ../xschem_library/devices/gnd.sym 250 -130 0 0 {name=l1 lab=VSS}
xschem instance ../xschem_library/devices/res.sym 550 -290 0 0 {name=R1 m=1 value=47K footprint=1206 device=resistor}

54
tests/create_save/tests/rom8k.tcl
View File

@ -1,33 +1,33 @@
xschem set rectcolor 3
xschem line 850 -270 850 -60
xschem line 1050 -270 1050 -60
xschem line 1250 -270 1250 -60
xschem line 850 -270 850 -60
xschem line 1050 -270 1050 -60
xschem line 1250 -270 1250 -60
xschem set rectcolor 8
xschem line 820 -220 850 -220
xschem line 850 -220 850 -180
xschem line 850 -180 950 -180
xschem line 950 -220 950 -180
xschem line 950 -220 1050 -220
xschem line 1050 -220 1050 -180
xschem line 1050 -180 1150 -180
xschem line 1150 -220 1150 -180
xschem line 1150 -220 1250 -220
xschem line 1250 -220 1250 -180
xschem line 1250 -180 1300 -180
xschem line 950 -160 950 -120
xschem line 950 -160 980 -160
xschem line 980 -160 980 -120
xschem line 980 -120 1150 -120
xschem line 1150 -160 1150 -120
xschem line 1150 -160 1180 -160
xschem line 1180 -160 1180 -120
xschem line 1180 -120 1300 -120
xschem line 820 -120 950 -120
xschem line 820 -220 850 -220
xschem line 850 -220 850 -180
xschem line 850 -180 950 -180
xschem line 950 -220 950 -180
xschem line 950 -220 1050 -220
xschem line 1050 -220 1050 -180
xschem line 1050 -180 1150 -180
xschem line 1150 -220 1150 -180
xschem line 1150 -220 1250 -220
xschem line 1250 -220 1250 -180
xschem line 1250 -180 1300 -180
xschem line 950 -160 950 -120
xschem line 950 -160 980 -160
xschem line 980 -160 980 -120
xschem line 980 -120 1150 -120
xschem line 1150 -160 1150 -120
xschem line 1150 -160 1180 -160
xschem line 1180 -160 1180 -120
xschem line 1180 -120 1300 -120
xschem line 820 -120 950 -120
xschem set rectcolor 7
xschem rect 950 -250 980 -80
xschem rect 1150 -250 1180 -80
xschem rect 950 -250 980 -80
xschem rect 1150 -250 1180 -80
xschem set rectcolor 21
xschem rect 10 -970 240 -750
xschem rect 10 -970 240 -750
xschem wire 150 -580 150 -560 {lab=vss}
xschem wire 150 -420 150 -400 {lab=vss}
xschem wire 10 -270 10 -250 {lab=vss}
@ -53,7 +53,7 @@ vvss vss 0 0
*.dc vvcc 0 2 0.1
.tran 0.2n 480n uic
** download models from here:
** download models from here:
** http://www.amarketplaceofideas.com/wp-content/uploads/2014/11/180nm-V1.7z
** and save to 'models_rom8k.txt' in simulation directory
.include models_rom8k.txt

18
tests/netlisting.tcl
View File

@ -1,21 +1,21 @@
#
# File: netlisting.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2022 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -37,7 +37,7 @@ set xschem_library_path "../xschem_library"
proc netlisting {dir fn} {
global xschem_library_path testname pathlist xschem_cmd
if { [regexp {\.sch$} $fn ] } {
puts "Testing ($testname) $dir/$fn"
puts "Testing ($testname) $dir/$fn"
set output_dir $dir
regsub -all $xschem_library_path $output_dir {} output_dir
regsub {^/} $output_dir {} output_dir
@ -80,13 +80,13 @@ proc run_xschem_netlist {type output_dir dir fn} {
if {$type eq "tdx"} {set opt t}
set netlist_failed 0 ;# not used here but might be used in the future.
set general_failure 0
cd $dir
set catch_status [catch {eval exec {$xschem_cmd $fn -q -x -r -$opt -o $netlist_output_dir -n 2> $output}} msg opt]
cd $cwd
if {$catch_status} {
set error_code [dict get $opt -errorcode]
# in case of child process error $error_code will be {CHILDSTATUS 11731 10}, second item is processID,
# in case of child process error $error_code will be {CHILDSTATUS 11731 10}, second item is processID,
# 3rd item is child process exit code. In case of netlisting error xschem exit code is 10
if {[regexp {^CHILDSTATUS.* 10$} $error_code]} {
set netlist_failed 1
@ -96,7 +96,7 @@ proc run_xschem_netlist {type output_dir dir fn} {
}
if {$general_failure} {
puts "FATAL: $xschem_cmd $fn -q -x -r -$opt -o $netlist_output_dir -n 2> $output : $msg"
incr num_fatals
incr num_fatals
} else {
lappend pathlist $fn_debug
lappend pathlist $fn_netlist

12
tests/open_close.tcl
View File

@ -1,21 +1,21 @@
#
# File: open_close.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2022 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -38,7 +38,7 @@ proc open_close {dir fn} {
global xschem_library_path testname pathlist xschem_cmd
set fpath "$dir/$fn"
if { [regexp {\.(sym|sch)$} $fn ] } {
puts "Testing (open_close) $fpath"
puts "Testing (open_close) $fpath"
set output_dir $dir
regsub -all $xschem_library_path $output_dir {} output_dir
regsub {^/} $output_dir {} output_dir

18
tests/run_regression.tcl
View File

@ -1,21 +1,21 @@
#
# File: run_regression.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2023 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -29,11 +29,11 @@ proc summarize_all {fn fd} {
set num_fail 0
if (!$b) {
while {[gets $fdread line] >=0} {
if { [regexp {[FAIL]$} $line] || [regexp {[GOLD\?]$} $line] || [regexp {^[FATAL]} $line]} {
puts $fd $line
if { [regexp {[FAIL]$} $line] || [regexp {[GOLD\?]$} $line] || [regexp {^[FATAL]} $line]} {
puts $fd $line
incr num_fail
}
}
}
}
puts $fd "Total num fail: $num_fail"
close $fdread
} else {

22
tests/test_utility.tcl
View File

@ -1,21 +1,21 @@
#
# File: xschem_test_utility.tcl
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2022 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -38,7 +38,7 @@ proc comp_file {file1 file2} {
}
proc print_results {testname pathlist num_fatals} {
if {[file exists ${testname}/gold]} {
set a [catch "open \"$testname.log\" w" fd]
if {$a} {
@ -50,24 +50,24 @@ proc print_results {testname pathlist num_fatals} {
foreach f $pathlist {
incr i
if {![file exists $testname/gold/$f]} {
puts $fd "$i. $f: GOLD?"
puts $fd "$i. $f: GOLD?"
incr num_gold
continue
}
if {![file exists $testname/results/$f]} {
puts $fd "$i. $f: RESULT?"
puts $fd "$i. $f: RESULT?"
continue
}
if ([comp_file $testname/gold/$f $testname/results/$f]) {
puts $fd "$i. $f: PASS"
} else {
puts $fd "$i. $f: FAIL"
puts $fd "$i. $f: FAIL"
incr num_fail
}
}
}
puts $fd "Summary:"
puts $fd "Num failed: $num_fail Num missing gold: $num_gold Num passed: [expr $i-$num_fail-$num_gold]"
if {$num_fatals} {
if {$num_fatals} {
puts $fd "FATAL: $num_fatals. Please search for FATAL in its output file for more detail"
}
close $fd

4
tests/xschemtest.tcl
View File

@ -13,7 +13,7 @@
## optionally with logging to catch memory leaks:
# xschem -d 3 -l log --script /path/to/xschemtest.tcl
## and then running: xschemtest
## running this test with different xschem versions with profiling enabled (-pg)
## running this test with different xschem versions with profiling enabled (-pg)
## allows to see differences in number of function calls / time spent.
## move schematic and redraw in a loop.
@ -172,7 +172,7 @@ proc print_test {{view 0}} {
proc test_xschem_simulation {{f simulate_ff.sch}} {
global tclstop OS
xschem load [abs_sym_path $f]
## search element with tclcommand attribute
## search element with tclcommand attribute
if {$OS ne {Windows}} {
xschem search regex 1 tclcommand {}
} else {

8
xschem_library/analyses/lib_init.tcl
View File

@ -1,4 +1,4 @@
# Analyses library for visual circuit analysis setup.
# Analyses library for visual circuit analysis setup.
# Copyright (C) 2025 Arpad Buermen
#
# This program is free software; you can redistribute it and/or modify
@ -226,8 +226,8 @@ proc netlister {netlist_type} {
try {
# Format analysis and post analysis script
set retval [$func $name]
# retval has 2 members:
# - command and
# retval has 2 members:
# - command and
# - post-command (for writing results in ngpice, empty string for spectre)
lassign $retval cmd postcmd
# Format sweep and add it to analysis
@ -564,7 +564,7 @@ proc format_signal_output_spice {name} {
set outn [string range $outn 1 end-1]
}
# Is outn empty
if {[string length $outn] == 0} {
if {[string length $outn] == 0} {
return "v($outp)"
} else {
return "v($outp,$outn)"

12
xschem_library/examples/0_examples_top.sch
View File

@ -28,8 +28,8 @@ E {}
L 3 860 -680 910 -660 {}
L 3 830 -800 1150 -800 {}
L 3 1190 -800 1510 -800 {}
L 8 850 -660 900 -680 {}
L 11 850 -670 900 -650 {dash=4}
L 8 850 -660 900 -680 {bus=8}
L 11 850 -670 900 -650 {dash=4 bus=3}
L 16 860 -650 910 -670 {}
B 2 1200 -780 1489 -574 {flags=image
alpha=0.9
@ -60,13 +60,13 @@ B 4 890 -630 910 -570 {}
B 6 810 -630 830 -570 {ellipse=0,360}
B 7 850 -610 920 -590 {dash=4}
B 7 850 -580 920 -560 {dash=4 fill=full}
B 8 860 -630 880 -570 {}
B 8 860 -630 880 -570 {bus=6}
A 4 875 -215 35.35533905932738 8.13010235415598 360 {}
A 6 940 -270 70.71067811865476 188.130102354156 89.99999999999997 {}
A 7 884.1666666666666 -210 39.58991173406564 210.3432488842396 198.9246444160511 {}
A 7 884.1666666666666 -210 39.58991173406564 210.3432488842396 198.9246444160511 {bus=4}
P 1 10 880 -480 870 -540 950 -520 910 -500 940 -470 920 -470 910 -450 890 -490 880 -470 880 -480 {dash=3}
P 4 6 830 -460 830 -550 820 -500 780 -560 770 -520 810 -480 {bezier=1}
P 15 11 870 -510 880 -550 900 -520 910 -540 920 -510 940 -520 920 -480 890 -490 860 -470 840 -520 870 -510 {fill=true}
P 15 11 870 -510 880 -550 900 -520 910 -540 920 -510 940 -520 920 -480 890 -490 860 -470 840 -520 870 -510 {fill=true bus=5}
T {Welcome to XSCHEM!} 90 -1180 0 0 1 1 {layer=5}
T {This is a test schematic window
@ -84,7 +84,7 @@ T {XSCHEM OBJECTS} 860 -840 0 0 0.6 0.6 {layer=7}
T {Components} 960 -330 0 0 0.6 0.6 {layer=4}
T {TEXT} 840 -740 0 0 0.5 0.5 {layer=8}
T {TEXT} 840 -790 1 0 0.7 0.7 {layer=6 font=Monospace}
T {Text} 850 -780 0 0 0.5 0.5 {layer=7 font="serif"}
T {Text} 850 -780 0 0 0.5 0.5 {layer=7 font="serif" slant=oblique}
T {TEXT} 940 -780 1 0 0.5 0.5 {weight=bold}
T {Text} 960 -770 0 0 0.6 0.6 {layer=4}
T {Arcs/Circles} 960 -240 0 0 0.6 0.6 {layer=4}

26
xschem_library/generators/mosgen.tcl
View File

@ -13,16 +13,16 @@ K {type=nmos
lvs_format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W nf=@nf m=@mult"
format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W
+ nf=@nf ad=@ad as=@as pd=@pd ps=@ps
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ mult=@mult m=@mult"
template="name=M1
L=0.5
W=1
nf=1
mult=1
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
pd=\\"'2*int((nf+1)/2) * (W/nf + 0.29)'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
ps=\\"'2*int((nf+2)/2) * (W/nf + 0.29)'\\"
nrd=\\"'0.29 / W'\\" nrs=\\"'0.29 / W'\\"
sa=0 sb=0 sd=0
@ -65,16 +65,16 @@ K {type=pmos
lvs_format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W nf=@nf m=@mult"
format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W
+ nf=@nf ad=@ad as=@as pd=@pd ps=@ps
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ mult=@mult m=@mult"
template="name=M1
L=0.5
W=1
nf=1
mult=1
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
pd=\\"'2*int((nf+1)/2) * (W/nf + 0.29)'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
ps=\\"'2*int((nf+2)/2) * (W/nf + 0.29)'\\"
nrd=\\"'0.29 / W'\\" nrs=\\"'0.29 / W'\\"
sa=0 sb=0 sd=0
@ -118,16 +118,16 @@ K {type=pmos
lvs_format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W nf=@nf m=@mult"
format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W
+ nf=@nf ad=@ad as=@as pd=@pd ps=@ps
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ mult=@mult m=@mult"
template="name=M1
L=0.15
W=1
nf=1
mult=1
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
pd=\\"'2*int((nf+1)/2) * (W/nf + 0.29)'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
ps=\\"'2*int((nf+2)/2) * (W/nf + 0.29)'\\"
nrd=\\"'0.29 / W'\\" nrs=\\"'0.29 / W'\\"
sa=0 sb=0 sd=0
@ -173,16 +173,16 @@ K {type=nmos
lvs_format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W nf=@nf m=@mult"
format="@spiceprefix@name @pinlist sky130_fd_pr__@model L=@L W=@W
+ nf=@nf ad=@ad as=@as pd=@pd ps=@ps
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ nrd=@nrd nrs=@nrs sa=@sa sb=@sb sd=@sd
+ mult=@mult m=@mult"
template="name=M1
L=0.15
W=1
nf=1
nf=1
mult=1
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
ad=\\"'int((nf+1)/2) * W/nf * 0.29'\\"
pd=\\"'2*int((nf+1)/2) * (W/nf + 0.29)'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
as=\\"'int((nf+2)/2) * W/nf * 0.29'\\"
ps=\\"'2*int((nf+2)/2) * (W/nf + 0.29)'\\"
nrd=\\"'0.29 / W'\\" nrs=\\"'0.29 / W'\\"
sa=0 sb=0 sd=0

10
xschem_library/generators/res.tcl
View File

@ -8,22 +8,22 @@ proc from_eng {i} {
set str [string tolower $str]
if { [regexp {^meg} $str] } { set str {meg} } else {
set suffix [string index $str 0]
}
}
set mult [switch $suffix {
a { expr {1e-18}}
f { expr {1e-15}}
p { expr {1e-12}}
n { expr { 1e-9}}
u { expr {1e-6}}
u { expr {1e-6}}
m { expr {1e-3}}
k { expr {1e3}}
meg { expr {1e6}}
g { expr {1e9}}
g { expr {1e9}}
t { expr {1e12}}
default { expr {1.0}}
}]
}]
return [expr {$n * $mult}]
}
}
set arg1 [lindex $argv 0]
if {$arg1 eq {}} { puts stderr "empty arg"; set arg1 1K}

2
xschem_library/gschem_import/place.awk
View File

@ -18,7 +18,7 @@ BEGIN{
print "C {" a "} " x*2000,y*2000, 0, 0, "{}"
}
close(command)

16
xschem_library/viewdraw_import/viewdraw_import.awk
View File

@ -1,22 +1,22 @@
#!/usr/bin/awk -f
#
# File: viewdraw_import.awk
#
#
# This file is part of XSCHEM,
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
# simulation.
# Copyright (C) 1998-2021 Stefan Frederik Schippers
#
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
@ -61,7 +61,7 @@ BEGIN{
# read viewdraw file, remove DOS cr characters
{
gsub(/\r/, "")
gsub(/\r/, "")
line[lines++] = $0
}
@ -390,7 +390,7 @@ function yscale(y)
return -y
}
# distance transformations (like circle radius)
# distance transformations (like circle radius)
function lenscale(len)
{
return len
@ -420,7 +420,7 @@ function get_fields_after(n, str, nf, i, a, arr)
#used to poke what's next wihout advancing read to next line
function next_line()
{
return line[lineno + 1]
return line[lineno + 1]
}
# xschem rectangle coordinates are ordered for efficiency reasons