added bit blasting option (default: disabled) in menu for verilog netlists: group bit slices in instance net assignments. Doc updates (FSiC-2022)

XSchemWin/XSchemWix/doc.wxs

@@ -723,9 +723,15 @@
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           </Component>
-          <Component Id="cmpFECBCF2FF410E56CAF5B28079D9092E6" Guid="{0E0F1B3F-4C09-4920-9818-CD984471B7DE}">
-            <File Id="fil0EE152B03813340BCEC692CEAD588D5B" KeyPath="yes" Source="$(var.docSrcDir)\xschem_man\tutorial_xschem_slides082.html" />
-          </Component>
+		  <Component Id="cmp9E8FC6D3F4D0BAEA49D60599C5B9679C" Guid="{F747FFEF-23E6-41E8-9EE3-9403859D1913}">
+			<File Id="fil1A67B7CDCC2D6FE924000D32F90EBF43" KeyPath="yes" Source="$(var.docSrcDir)\xschem_man\tutorial_xschem_slides083.html" />
+		  </Component>
+		  <Component Id="cmp372B72F0070B27C3917E4D4EF5B3AA96" Guid="{9145002E-C8B2-4D82-AD27-3332024F46E5}">
+			<File Id="fil8BCA6F58E08521D4A207CCD4201C447A" KeyPath="yes" Source="$(var.docSrcDir)\xschem_man\tutorial_xschem_slides084.html" />
+		  </Component>
+		  <Component Id="cmpE0730B3DCCC559E42C0979B05EB89CC2" Guid="{823B5933-F7DB-4DC2-95FD-65C653128F6A}">
+			<File Id="filB7FFAA6EB9C163E5B17EA5B73DA21392" KeyPath="yes" Source="$(var.docSrcDir)\xschem_man\tutorial_xschem_slides085.html" />
+		  </Component>
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@@ -1100,7 +1106,9 @@
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       <ComponentRef Id="cmpAAFAC577840296567AE39EC857468CD8" />
-      <ComponentRef Id="cmpFECBCF2FF410E56CAF5B28079D9092E6" />
+	  <ComponentRef Id="cmp9E8FC6D3F4D0BAEA49D60599C5B9679C" />
+	  <ComponentRef Id="cmp372B72F0070B27C3917E4D4EF5B3AA96" />
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doc/xschem_man/tutorial_xschem_slides02.html

@@ -31,9 +31,10 @@ p{padding: 15px  30px 10px;}
     <li>Memory Hog, keeps growing until all Virtual memory exhausted, then crash.</li>
     <li>Start your icfb session, go get a coffee, when back it's hopefully up and running.</li>
     <li>One process handles all design windows. Process crashes, all work on all windows lost.</li>
-    <li>Many functions (search/replace and others) take way too long to complete. Everything is done in skill.</li>
+    <li>Many functions (search/replace/highlight and others) take way too long
+        to complete. Everything is done in skill.</li>
     <li>Proprietary file format.</li>
-    <li>I hate Skill and Lisp. Not that these are bad languages, its my fault.</li>
+    <li>Computation intensive tasks should not be done in any scripting language (Skill, Lisp, Python)</li>
    </ul>
   </h3>
 

src/verilog.awk

@@ -23,6 +23,15 @@
 
 
 BEGIN{
+ bitblast = 0
+ while( (ARGV[1] ~ /^[-]/) || (ARGV[1] ~ /^$/) ) {
+   if(ARGV[1] == "-bitblast") bitblast = 1
+   for(i=2; i<= ARGC;i++) {
+     ARGV[i-1] = ARGV[i]
+   }
+   ARGC--
+ }
+
  net_types["wire"]=1
  net_types["tri"]=1
  net_types["wor"]=1
@@ -269,7 +278,7 @@ begin_module && $1 ~/^\);$/ {
     if(nmult==1) printf "\n .%s( %s )" ,s_b($(j-1)),pin
     else {
       # old code
-      if(1) {
+      if(!bitblast) {
         split(pin,pin_array,",")
         basename=s_b(pin_array[1])
         if(check2(pin_array,nmult) && net_ascending==0) {  ## 20140416 if ascending nets print single bits

src/xschem.tcl

@@ -361,7 +361,7 @@ proc ev {s} {
 }
 proc netlist {source_file show netlist_file} {
  global XSCHEM_SHAREDIR flat_netlist hspice_netlist netlist_dir
- global verilog_2001 debug_var OS
+ global verilog_2001 debug_var OS verilog_bitblast
  
  simuldir
  set netlist_type [xschem get netlist_type]
@@ -409,7 +409,11 @@ proc netlist {source_file show netlist_file} {
  }
  if {$netlist_type eq {verilog}} {
    set cmd  ${XSCHEM_SHAREDIR}/verilog.awk
-   eval exec {awk -f $cmd $source_file > $dest}
+   if { $verilog_bitblast == 1 } {
+     eval exec {awk -f $cmd -- -bitblast $source_file > $dest}
+   } else {
+     eval exec {awk -f $cmd $source_file > $dest}
+   }
    if { $verilog_2001==1 } { 
      set cmd ${XSCHEM_SHAREDIR}/convert_to_verilog2001.awk
      set interm ${dest}[pid]
@@ -4542,7 +4546,7 @@ set tctx::global_list {
   spiceprefix split_files svg_colors svg_font_name symbol symbol_width sym_txt tclcmd_txt tclstop
   text_line_default_geometry textwindow_fileid textwindow_filename textwindow_w tmp_bus_char 
   toolbar_horiz toolbar_visible top_subckt transparent_svg undo_type
-  use_label_prefix use_lab_wire user_wants_copy_cell verilog_2001
+  use_label_prefix use_lab_wire user_wants_copy_cell verilog_2001 verilog_bitblast
   viewdata_fileid viewdata_filename viewdata_w vsize xschem_libs xschem_listen_port
 }
 
@@ -4899,6 +4903,8 @@ proc build_widgets { {topwin {} } } {
        } 
      }
   $topwin.menubar.option.menu add checkbutton -label "Verilog 2001 netlist variant" -variable verilog_2001
+  $topwin.menubar.option.menu add checkbutton \
+    -label "Group bus slices in Verilog instances" -variable verilog_bitblast
   $topwin.menubar.option.menu add checkbutton -label "Draw grid" -variable draw_grid \
      -accelerator {%} \
      -command {
@@ -5482,6 +5488,7 @@ set_ne top_subckt 0
 set_ne hide_empty_graphs 0 ;# if set to 1 waveform boxes will be hidden if no raw file loaded
 set_ne spiceprefix 1
 set_ne verilog_2001 1
+set_ne verilog_bitblast 0
 set_ne split_files 0
 set_ne flat_netlist 0
 set_ne netlist_show 0

xschem_library/logic/testbench.sch

@@ -260,3 +260,12 @@ C {adc_bridge.sym} 190 -260 0 0 {name=v6 delay=1}
 C {adc_bridge.sym} 190 -240 0 0 {name=v7 delay=1}
 C {adc_bridge.sym} 190 -220 0 0 {name=v8 delay=1}
 C {adc_bridge.sym} 190 -200 0 0 {name=v9 delay=1}
+C {ram.sym} 1390 -470 0 0 {name=xcoderam1   dim=5 width=8 hex=1 datafile=ram.list}
+C {lab_pin.sym} 1540 -530 0 1 {name=p56 lab=DOUT[7:0]}
+C {lab_pin.sym} 1240 -530 0 0 {name=p57 lab=CK,ADD[1:0],ADD[3:4]}
+C {lab_pin.sym} 1240 -490 0 0 {name=p58 lab=DIN[7:0]}
+C {lab_pin.sym} 1240 -470 0 0 {name=p59 lab=WEN}
+C {lab_pin.sym} 1240 -430 0 0 {name=p60 lab=OEN}
+C {lab_pin.sym} 1240 -410 0 0 {name=p61 lab=CK}
+C {lab_pin.sym} 1240 -450 0 0 {name=p62 lab=CEN}
+C {lab_pin.sym} 1240 -510 0 0 {name=p63 lab=M[7:0]}