Version bump

- Change .cvsignore to .gitignore
- Remove Id metacomments
- Cleanup whitespace at end of lines

.gitignore

@@ -7,7 +7,7 @@
 *.1
 *.tmp
 *.tex
-Makefile
+/Makefile
 README
 config.cache
 config.status

Changes

@@ -3,6 +3,95 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.665 2008/06/25
+
+**** Ignore "// verilator" comments alone on endif lines.  [Rodney Sinclair]
+
+**** "Make install" now installs verilator_includer and verilator_profcfunc.
+
+**** Fix tracing missing changes on undriven public wires. [Rodney Sinclair]
+
+**** Fix syntax error when "`include `defname" is ifdefed.  [John Dickol]
+
+**** Fix error when macro call has commas in concatenate. [John Dickol]
+
+**** Fix compile errors under Fedora 9, GCC 4.3.0.  [by Jeremy Bennett]
+
+**** Fix Makefile to find headers/libraries under prefix. [by Holger_Waechtler]
+
+* Verilator 3.664 2008/05/08
+
+**** Fix missing file in kit.
+
+* Verilator 3.663 2008/05/07
+
+**** Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer]
+
+**** Fix compiler warnings under GCC 4.2.1.
+
+**** Fix preprocessor `else after series of `elsif.  [Mark Nodine]
+
+**** Fix parametrized defines calling define with comma.  [Joshua Wise]
+
+**** Fix comma separated list of primitives.  [by Bryan Brady]
+
+* Verilator 3.662 2008/04/25
+
+***  Add Verilog 2005 $clog2() function.
+     This is useful in calculating bus-widths from parameters.
+
+***  Support /**/ comments in -f option files. [Stefan Thiede]
+
+**** Add error message when modules have duplicate names. [Stefan Thiede]
+
+**** Support defines terminated in EOF, though against spec. [Stefan Thiede]
+
+**** Support optional argument to $finish and $stop.  [by Stefan Thiede]
+
+**** Support ranges on gate primitive instantiations. [Stefan Thiede]
+
+**** Ignore old standard(ish) Verilog-XL defines.  [by Stefan Thiede]
+
+**** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu]
+
+**** Fix "output reg name=expr;" syntax error. [Martin Scharrer]
+
+**** Fix multiple .v files being read in random order. [Stefan Thiede]
+
+**** Fix internal error when params get non-constants. [Johan Wouters]
+
+**** Fix bug introduced in 3.661 with parametrized defines.
+
+* Verilator 3.661 2008/04/04
+
+***  The --enable-defenv configure option added in 3.660 is now the default.
+     This hard-codes a default for VERILATOR_ROOT etc in the executables.
+
+***  Add --language option for supporting older code. [Stefan Thiede]
+
+***  Add --top-module option to select between multiple tops. [Stefan Thiede]
+
+***  Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt]
+     Previously they threw fatal errors, which in most cases is correct
+     according to spec, but can be incorrect in presence of parameter values.
+
+**** Support functions with "input integer".  [Johan Wouters]
+
+**** Ignore delays attached to gate UDPs.  [Stefan Thiede]
+
+**** Fix SystemVerilog parameterized defines with `` expansion,
+     and fix extra whitespace inserted on substitution.  [Vladimir Matveyenko]
+
+**** Fix no-module include files on command line.  [Stefan Thiede]
+
+**** Fix dropping of backslash quoted-quote at end of $display.
+
+**** Fix task output pin connected to non-variables. [Jonathan Kimmitt]
+
+**** Fix missing test_v in install datadir. [Holger Waechtler]
+
+**** Fix internal error after MSB < LSB error reported to user. [Stefan Thiede]
+
 * Verilator 3.660 2008/03/23
 
 ***  Add support for hard-coding VERILATOR_ROOT etc in the executables,
@@ -1163,8 +1252,6 @@ of input ports exists for tracing.
 **** First code written.
 
 ----------------------------------------------------------------------
-$Id$
-----------------------------------------------------------------------
 
 This uses outline mode in Emacs.  See C-h m [M-x describe-mode].
 

MANIFEST.SKIP

@@ -0,0 +1,26 @@
+^CVS/
+/CVS/
+\.git/
+\.svn/
+\.(bak|old)/
+\.(bak|old)$
+\bMakefile$
+\.tar\.
+.*\.tgz
+.*\.log
+.*\.tmp
+.*\.tex
+.*\.key
+.*\.vcd
+/obj_dir/
+/obj_dbg/
+/obj_opt/
+/logs/
+Makefile
+src/Makefile_obj
+include/verilated.mk
+config.cache
+config.status
+verilator_bin.*
+autom4te\.cache/
+nodist/

Makefile.in

@@ -1,24 +1,23 @@
-# $Id$
 #*****************************************************************************
 # DESCRIPTION: Verilator top level: Makefile pre-configure version
-# 
-# This file is part of Verilator.  
-# 
+#
+# This file is part of Verilator.
+#
 # Author: Wilson Snyder <[email protected]>
-# 
-# Code available from: http://www.veripool.com/verilator
-# 
+#
+# Code available from: http://www.veripool.org/verilator
+#
 #*****************************************************************************
-# 
+#
 # Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
 # General Public License or the Perl Artistic License.
-# 
+#
 # Verilator is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 #****************************************************************************/
 #
 # make all	to compile and build Verilator.
@@ -38,7 +37,7 @@
 #      source and built the program without creating any other files,
 #      `make distclean' should leave only the files that were in the
 #      distribution.
-# 
+#
 # make maintainer-clean
 #      Delete everything from the current directory that can be
 #      reconstructed with this Makefile.  This typically includes
@@ -61,6 +60,9 @@ MAKEINFO = makeinfo
 TEXI2DVI = texi2dvi
 PERL = @PERL@
 
+# Destination prefix for RPMs
+DESTDIR =
+
 #### Don't edit: You're much better using configure switches to set these
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -81,6 +83,9 @@ infodir = @infodir@
 # Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@
 
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
 #### End of system configuration section. ####
 ######################################################################
 
@@ -95,21 +100,27 @@ DISTDEP = info Makefile
 # Files to distribute.
 DISTBIN = $(wildcard bin/verilator-*)
 
-DISTFILES_INC = $(INFOS) .cvsignore COPYING *.in *.ac \
+DISTFILES_INC = $(INFOS) .gitignore COPYING *.in *.ac \
 	Changes README TODO \
+	MANIFEST.SKIP \
 	bin/* \
 	install-sh configure mkinstalldirs *.texi \
 	include/verilated.[chv]* \
 	include/verilatedos.[chv]* \
 	include/*.in \
-	src/.cvsignore src/*.in src/*.cpp src/*.[chly] src/astgen src/flexfix \
+	include/.*ignore \
+	.*attributes */.*attributes  */*/.*attributes \
+	src/.*ignore src/*.in src/*.cpp src/*.[chly] src/astgen src/*fix \
 	src/*.pl \
-	test_*/.cvsignore test_*/Makefile* test_*/*.cpp \
+	test_*/.*ignore test_*/Makefile* test_*/*.cpp \
 	test_*/*.pl test_*/*.v test_*/*.vc test_*/vlint \
 	test_verilated/vgen*.pl \
-	test_regress/t/*.v* \
-	test_regress/t/*.pl \
+	test_regress/t/*.cpp \
+	test_regress/t/*.h \
+	test_regress/t/*.mem \
 	test_regress/t/*.out \
+	test_regress/t/*.pl \
+	test_regress/t/*.v* \
 	verilator.* \
 
 INST_PROJ_FILES = \
@@ -186,16 +197,18 @@ verilator.html: bin/verilator
 verilator.pdf: bin/verilator $(DISTCONFIG)
 	pod2latex --full --out verilator.tex bin/verilator
 	cat < verilator.tex \
+	   | sed 's/\\begin{document}/\\usepackage[left=1.7in,right=1.7in,top=1.3in,bottom=1.3in]{geometry}\n\\begin{document}/' \
+	   | sed 's/\\begin{document}/\\usepackage[pdftex,bookmarks=true,bookmarksnumbered=true,hypertexnames=false,breaklinks=true,linkbordercolor={0 0 1}]{hyperref}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\usepackage{fancyhdr} \\pagestyle{fancy}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\setlength{\\parindent}{0pt} \\setlength{\\parskip}{\\baselineskip}\n\\begin{document}/' \
-	   | sed 's/\\begin{document}/\\title{$(DISTTITLE)} \\date{${DISTDATE}} \\author{Wilson Snyder\\\\ http:\/\/www.veripool.com}\n\\begin{document}/' \
+	   | sed 's/\\begin{document}/\\title{$(DISTTITLE)} \\date{${DISTDATE}} \\author{Wilson Snyder\\\\ http:\/\/www.veripool.org}\n\\begin{document}/' \
 	   | sed 's/\\begin{document}/\\lhead[$(DISTTITLE)]{$(DISTTITLE)}\n\\begin{document}/' \
 	   | sed 's/\\tableofcontents/\\begin{titlepage} \\maketitle \\end{titlepage}\n\\tableofcontents/' \
 	   > verilator2.tex
 	mv verilator2.tex verilator.tex
 	pdflatex verilator.tex
 	pdflatex verilator.tex
-	-rm -f verilator.toc verilator.aux verilator.idx
+	-rm -f verilator.toc verilator.aux verilator.idx verilator.out
 
 INSTALL: install.texi
 	$(MAKEINFO) -I$(srcdir) $(srcdir)/install.texi --output=$@ \
@@ -206,27 +219,31 @@ README: readme.texi
 	--no-headers --no-validate
 
 # See uninstall also
-VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg
+VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg \
+	verilator_includer verilator_profcfunc
 installbin:
-	$(SHELL) ${srcdir}/mkinstalldirs $(bindir)
-	( cd bin ; $(INSTALL_PROGRAM) verilator $(bindir)/verilator )
-	( $(INSTALL_PROGRAM) verilator_bin $(bindir)/verilator_bin )
-	( $(INSTALL_PROGRAM) verilator_bin_dbg $(bindir)/verilator_bin_dbg )
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(bindir)
+	( cd bin ; $(INSTALL_PROGRAM) verilator $(DESTDIR)$(bindir)/verilator )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(bindir)/verilator_includer )
+	( cd bin ; $(INSTALL_PROGRAM) verilator_profcfunc $(DESTDIR)$(bindir)/verilator_profcfunc )
+	( $(INSTALL_PROGRAM) verilator_bin $(DESTDIR)$(bindir)/verilator_bin )
+	( $(INSTALL_PROGRAM) verilator_bin_dbg $(DESTDIR)$(bindir)/verilator_bin_dbg )
 
 VL_INST_MAN_FILES = verilator.1
 installman:
-	$(SHELL) ${srcdir}/mkinstalldirs $(mandir)
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(mandir)/man1
 	for p in $(VL_INST_MAN_FILES) ; do \
-	  $(INSTALL_PROGRAM) $$p $(mandir)/man1/$$p; \
+	  $(INSTALL_PROGRAM) $$p $(DESTDIR)$(mandir)/man1/$$p; \
 	done
 
 installdata:
-	$(SHELL) ${srcdir}/mkinstalldirs $(pkgdatadir)/examples
-	cp -r include $(pkgdatadir)
-	cp -r src     $(pkgdatadir)
-	cp -r test_c  $(pkgdatadir)/examples
-	cp -r test_sc $(pkgdatadir)/examples
-	cp -r test_sp $(pkgdatadir)/examples
+	$(SHELL) ${srcdir}/mkinstalldirs $(DESTDIR)$(pkgdatadir)/examples
+	cp -r include $(DESTDIR)$(pkgdatadir)
+	cp -r src     $(DESTDIR)$(pkgdatadir)
+	cp -r test_c  $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sc $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_sp $(DESTDIR)$(pkgdatadir)/examples
+	cp -r test_v  $(DESTDIR)$(pkgdatadir)/examples
 
 VL_INST_DATA_FILES = verilator.1
 install: all_nomsg installbin installman installdata install-msg
@@ -244,8 +261,8 @@ install-project: dist
 	for p in verilator.1 ; do \
 	  $(INSTALL_PROGRAM) -m 0666 $$p $(DIRPROJECT_PREFIX)/man/man1/$$p; \
 	done
-	$(INST_PROJ_CVS) $(DISTNAME).tar.gz $(DIRPROJECT)/hw/utils/verilator/verilator.tgz
-	rm $(DISTNAME).tar.gz
+	$(INST_PROJ_CVS) $(DISTNAME).tgz $(DIRPROJECT)/hw/utils/verilator/verilator.tgz
+	rm $(DISTNAME).tgz
 
 install-project-quick:
 	@echo "Install-project-quick (no strip) to $(DIRPROJECT)"
@@ -258,9 +275,6 @@ install-project-quick:
 endif
 
 ftp: info
-	echo "http://www.veripool.com/verilator3.html"
-	cp verilator.html verilator_man.html
-	ftp_tree --password $(VERIPOOL_PW) --user $(VERIPOOL_USER) verilator_man.html webftp.veripool.com:/web
 
 install-msg:
 	@echo "Installed!"
@@ -273,9 +287,9 @@ install-msg:
 	@echo
 
 uninstall:
-	-cd $(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
-	-cd $(bindir) && rm -f $(VL_INST_BIN_FILES)
-	-rm -f $(pkgdatadir)
+	-cd $(DESTDIR)$(mandir)/man1 && rm -f $(VL_INST_MAN_FILES)
+	-cd $(DESTDIR)$(bindir) && rm -f $(VL_INST_BIN_FILES)
+	-rm -f $(DESTDIR)$(pkgdatadir)
 
 # autoheader might not change config_build.h.in, so touch a stamp file.
 IN_WILD := ${srcdir}/*.in ${srcdir}/*/*.in ${srcdir}/*/*/*.in \
@@ -300,7 +314,7 @@ configure: configure.ac
 maintainer-clean::
 	@echo "This command is intended for maintainers to use;"
 	@echo "rebuilding the deleted files requires makeinfo."
-	rm -f *.info* $(INFOS) faq.html verilator.html configure bin/*
+	rm -f *.info* $(INFOS) faq.html verilator.html configure
 
 clean mostlyclean distclean maintainer-clean maintainer-copy::
 	for dir in $(SUBDIRS); do \
@@ -309,7 +323,7 @@ clean mostlyclean distclean maintainer-clean maintainer-copy::
 	done
 
 clean mostlyclean distclean maintainer-clean::
-	rm -f $(SCRIPTS) *.tmp 
+	rm -f $(SCRIPTS) *.tmp
 	rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log
 	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
 	rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas
@@ -325,6 +339,13 @@ TAGFILES=${srcdir}/*/*.cpp ${srcdir}/*/*.h ${srcdir}/*/[a-z]*.in \
 TAGS:	$(TAGFILES)
 	etags $(TAGFILES)
 
+######################################################################
+# Test targets
+
+dist-file-list:
+	@echo "begin-dist-file-list:";  # Scripts look for this
+	@echo $(wildcard $(DISTFILES))
+	@echo "end-dist-file-list:";  # Scripts look for this
 
 ######################################################################
 # Distributions
@@ -333,7 +354,7 @@ DISTCONFIG = src/config_build.h.in
 
 DISTTITLE := $(shell sed -e '/DTVERSION/!d' -e 's/[^0-9]*\([0-9.a-z]*\).*/verilator-\1/' -e 's/v/V/' -e q $(DISTCONFIG))
 DISTNAME := $(shell sed -e '/DTVERSION/!d' -e 's/[^0-9]*\([0-9.a-z]*\).*/verilator-\1/' -e q $(DISTCONFIG))
-DISTDATEPRE := $(shell sed -e '/DTVERSION/!d' -e 's/.*\([0-3]\?[0-9].[0-3]\?[0-9].[1-2][0-9][0-9][0-9]\).*/\1/' -e q $(DISTCONFIG))
+DISTDATEPRE := $(shell sed -e '/DTVERSION/!d' -e 's/.*\([1-2][0-9][0-9][0-9].[0-9]*[0-9].[0-9]*[0-9]\).*/\1/' -e q $(DISTCONFIG))
 
 DISTTAGNAME := $(subst .,_,$(subst -,_,$(DISTNAME)))
 DISTDATE := $(subst /,-,$(DISTDATEPRE))
@@ -352,14 +373,14 @@ dist: $(DISTDEP) maintainer-copy
 	chmod -R a+r $(DISTNAME)
 	tar chf $(DISTNAME).tar $(DISTNAME)
 	gzip --force --best $(DISTNAME).tar
+	mv $(DISTNAME).tar.gz $(DISTNAME).tgz
 	rm -fr $(DISTNAME)
 
 maintainer-diff:
 	svnorcvs diff $(DISTTAGNAME)
 
 preexist:
-	test ! -r ~/src/kits/$(DISTNAME).tar.gz
+	svnorcvs nexists $(DISTTAGNAME)
 
 maintainer-dist: preexist dist tag
-	cp *.gz ~/backpack
-	cp *.gz ~/src/kits
+	svnorcvs release $(DISTNAME).tgz

TODO

@@ -1,4 +1,3 @@
-// $Id$
 // DESCRIPTION: Verilator: List of To Do issues.
 //
 // Copyright 2004-2008 by Wilson Snyder. This program is free software; you can
@@ -7,7 +6,7 @@
 
 
 Features:
- 	Finish 3.400 new ordering fixes
+	Finish 3.400 new ordering fixes
 	Latch optimizations {Need here}
 	Task I/Os connecting to non-simple variables.
 	Fix nested casez statements expanding into to huge C++. [JeanPaul Vanitegem]
@@ -50,7 +49,7 @@ Testing:
 
 Usability:
 	Better reporting of unopt problems, including what lines of code
-	Report more errors (all of them?) before exiting [Eugene Weber]	
+	Report more errors (all of them?) before exiting [Eugene Weber]
 
 Internal Code:
 	Eliminate the AstNUser* passed to all visitors; its only needed in V3Width,
@@ -69,7 +68,7 @@ Performance:
 	Multithreaded execution
 	Bit-multiply for faster bit swapping and a=b[1,3,2] random bit reorderings.
 	Move _last sets and all other combo logic inside master
-		if() that triggers on all possible sense items 
+		if() that triggers on all possible sense items
 	Rewrite and combine V3Life, V3Subst
 		If block temp only ever set in one place to constant, propagate it
 			Used in t_mem for array delayed assignments
@@ -139,15 +138,15 @@ Selectable SystemC types based on widths (see notes below)
        c) a conditional whose possible values are (a) or (b)
 
  2) One can lose that fact that a node is a tristate node.  This happens
-    if a tristate node is assigned to a 'standard' node, or is used on 
+    if a tristate node is assigned to a 'standard' node, or is used on
     RHS of a conditional. The following infer tristate signals:
-       a) inout <SIGNAL> 
-       b) tri <SIGNAL> 
+       a) inout <SIGNAL>
+       b) tri <SIGNAL>
        c) assigning to 'Z' (maybe through a conditional)
     Note: tristate-ness of an output port determined only by
           statements in the module (not the instances it calls)
-  
+
  4) Tristate variables can't be multidimensional arrays
- 5) Only check tristate contention between modules (not within!)	
+ 5) Only check tristate contention between modules (not within!)
  6) Only simple compares with 'Z' are allowed (===)
 

bin/verilator

@@ -1,7 +1,6 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 ######################################################################
 #
 # Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@@ -84,7 +83,6 @@ run ($vcmd);
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Revision$$Date$ ', "\n";
     pod2usage(-exitstatus=>2, -verbose=>2);
 }
 
@@ -161,7 +159,7 @@ code, lints it, and optionally adds coverage and waveform tracing code.
 For C++ and SystemC formats, it outputs .cpp and .h files.  For SystemPerl
 format, it outputs .sp files for the SystemPerl preprocessor, which greatly
 simplifies writing SystemC code and is available at
-L<http://www.veripool.com>.
+L<http://www.veripool.org>.
 
 The files created by Verilator are then compiled with C++.  The user writes
 a little C++ wrapper file, which instantiates the top level module, and
@@ -197,6 +195,7 @@ descriptions in the next sections for more information.
     -I<dir>                     Directory to search for includes
     --inhibit-sim               Create function to turn off sim
     --inline-mult <value>       Tune module inlining
+    --language <lang>           Language standard to parse
     --lint-only                 Lint, but do not make output
     --MMD                       Create .d dependency files
     --MP                        Create phony dependency targets
@@ -217,6 +216,7 @@ descriptions in the next sections for more information.
     --sc                        Create SystemC output
     --sp                        Create SystemPerl output
     --stats                     Create statistics file
+    --top-module <topname>      Name of top level input module
     --trace                     Enable waveform creation
     --trace-depth <levels>      Depth of tracing
     -U<var>                     Undefine preprocessor define
@@ -379,6 +379,14 @@ values, or a value <= 1 will inline everything, will lead to longer compile
 times, but potentially faster runtimes.  This setting is ignored for very
 small modules; they will always be inlined, if allowed.
 
+=item --language I<value>
+
+Select the language to be used when first processing each Verilog file.
+The language value must be "1364-1995", "1364-2001", "1364-2001",
+"1364-2005", or "1800-2005".  This should only be used for legacy code, as
+the preferable option is to edit the code to repair new keywords, or add
+appropriate `begin_keywords.
+
 =item --lint-only
 
 Check the files for lint violations only, do not create any other output.
@@ -451,8 +459,9 @@ the backward-compatible default of sc_bv's.
 
 =item --prefix I<topname>
 
-Specifies the name of the top level class.  Defaults to the name of the first
-Verilog file passed on the command line.
+Specifies the name of the top level class and makefile.  Defaults to V
+prepended to the name of the --top-module switch, or V prepended to the
+first Verilog filename passed on the command line.
 
 =item --profile-cfuncs
 
@@ -498,11 +507,22 @@ Specifies SystemPerl output mode; see also --cc and -sc.
 
 Creates a dump file with statistics on the design in {prefix}__stats.txt.
 
+=item --top-module I<topname>
+
+When the input Verilog contains more than one top level module, specifies
+the name of the top level Verilog module to become the top, and sets the
+default for if --prefix is not used.  This is not needed with standard
+designs with only one top.
+
 =item --trace
 
-Adds waveform tracing code to the model, this will create additional
-{prefix}__Trace*.cpp files you will need to add to your Makefiles, if
-you're not using the ones generated for you.
+Adds waveform tracing code to the model.  Verilator will generate
+additional {prefix}__Trace*.cpp files that will need to be compiled.  In
+addition Sp.cpp (for SystemC traces) or SpTraceVcdC.c (for C++ only) from
+the SystemPerl kit's src directory must be compiled and linked in.  If
+using the Verilator generated Makefiles, these will be added as source
+targets for you.  If you're not using the Verilator makefiles, you will
+need to add these to your Makefile manually.
 
 Having tracing compiled in may result in some small performance losses,
 even when waveforms are not turned on during model execution.
@@ -897,7 +917,7 @@ example:
 	unsigned int main_time = 0;	// Current simulation time
 
 	double sc_time_stamp () {	// Called by $time in Verilog
-    	    return main_time;
+	    return main_time;
 	}
 
 	int main() {
@@ -985,6 +1005,8 @@ declarations inside port lists.
 Verilator supports the `begin_keywords and `end_keywords compiler
 directives.
 
+Verilator supports $clog2.
+
 Verilator partially supports the uwire keyword.
 
 =head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
@@ -1528,6 +1550,10 @@ argument (as with C's printf), you cannot simply list variables standalone.
 The sized display functions are rarely used and so not supported.  Replace
 them with a $write with the appropriate format specifier.
 
+=item $finish, $stop
+
+The rarely used optional parameter to $finish and $stop is ignored.
+
 =item $fopen, $fclose, $fdisplay, $fwrite
 
 File descriptors passed to the file PLI calls must be file descriptors, not
@@ -1667,7 +1693,7 @@ output from a sub-module.)  While legal in Verilog, implicit declarations
 only work for single bit wide signals (not buses), do not allow using a
 signal before it is implicitly declared by a cell, and can lead to dangling
 nets.  A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
-Emacs, available from L<http://www.veripool.com/>
+Emacs, available from L<http://www.veripool.org/>
 
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.
@@ -1875,6 +1901,24 @@ The best fix, which clarifies intent and will also make all tools happy is:
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.
 
+=item WIDTHCONCAT
+
+Warns that based on width rules of Verilog, a concatenate or replication
+has a undeterminate width.  In most cases this violates the Verilog rule
+that widths inside concatenates and replicates must be sized, and should be
+fixed in the code.
+
+    wire [63:0] concat = {1,2};
+
+An example where this is technically legal (though still bad form) is:
+
+    parameter PAR = 1;
+    wire [63:0] concat = {PAR,PAR};
+
+The correct fix is to either size the 1 ("32'h1"), or add the width to the
+parameter definition ("parameter [31:0]"), or add the width to the
+parameter usage ("{PAR[31:0],PAR[31:0]}".
+
 =back
 
 The following describes the less obvious errors:
@@ -2075,7 +2119,7 @@ use GCC 2.95, or GCC 3.4 you'll have faster builds.  Two ways to cheat are
 to compile on parallel machines and avoid compilations altogether.  See the
 --output-split option, and the web for the ccache, distcc and icecream
 packages, and the Make::Cache package available from
-L<http://www.veripool.com/>. Make::Cache will skip GCC runs between
+L<http://www.veripool.org/>. Make::Cache will skip GCC runs between
 identical source builds, even across different users.
 
 =item Why do so many files need to recompile when I add a signal?
@@ -2160,7 +2204,10 @@ outputs.  Now, the following should fail:
     cd test_regress
     t/t_BUG.pl
 
-Finally, Mail the bug report to C<[email protected]>.
+Finally, report the bug using the bug tracker at
+L<http://www.veripool.org/verilator>.  The bug will become publicly
+visible; if this is unacceptable, mail the bug report to
+C<[email protected]>.
 
 =head1 HISTORY
 
@@ -2213,7 +2260,7 @@ Eugene Weber, Leon Wildman, and Mat Zeno.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/>.
 
 Copyright 2003-2008 by Wilson Snyder.  Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser

bin/verilator_difftree

@@ -1,7 +1,6 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 ######################################################################
 #
 # Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
@@ -115,7 +114,6 @@ sub filter {
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -130,7 +128,7 @@ sub parameter {
 	$Opt_A = $param;
     } elsif (!defined $Opt_B) {
 	$Opt_B = $param;
-    } else {	
+    } else {
 	die "%Error: Unknown parameter: $param\n";
     }
 }
@@ -178,7 +176,7 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/verilator>.
 
 Copyright 2005-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU

bin/verilator_includer

@@ -1,7 +1,6 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 # DESCRIPTION: Print include statements for each ARGV
 #
 # Copyright 2003-2008 by Wilson Snyder. This program is free software; you can

bin/verilator_profcfunc

@@ -1,7 +1,6 @@
 : # -*-Mode: perl;-*- use perl, wherever it is
 eval 'exec perl -wS $0 ${1+"$@"}'
   if 0;
-# $Id$
 ######################################################################
 #
 # Copyright 2007-2008 by Wilson Snyder <[email protected]>.  This
@@ -50,7 +49,6 @@ profcfunc($Opt_File);
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -63,7 +61,7 @@ sub parameter {
     my $param = shift;
     if (!defined $Opt_File) {
 	$Opt_File = $param;
-    } else {	
+    } else {
 	die "%Error: Unknown parameter: $param\n";
     }
 }
@@ -189,7 +187,7 @@ Displays this message and program version and exits.
 
 =head1 DISTRIBUTION
 
-The latest version is available from L<http://www.veripool.com/>.
+The latest version is available from L<http://www.veripool.org/>.
 
 Copyright 2007-2008 by Wilson Snyder.  This package is free software; you
 can redistribute it and/or modify it under the terms of either the GNU

configure.ac

@@ -1,24 +1,36 @@
-dnl $Id$
 dnl DESCRIPTION: Process this file with autoconf to produce a configure script.
 dnl Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
 dnl redistribute it and/or modify it under the terms of either the GNU
 dnl General Public License or the Perl Artistic License.
 
-AC_REVISION($Revision$)dnl
 AC_INIT(src/Verilator.cpp)
 AC_CONFIG_HEADER(src/config_build.h)
 
 dnl Special Substitutions
 AC_ARG_ENABLE(defenv,
-   [AS_HELP_STRING([--enable-defenv], [hardcode default environment variables])],
-   CFG_WITH_DEFENV=1,)
+   [AS_HELP_STRING([--disable-defenv], [disable hardcoded default environment variables])],
+   CFG_WITH_DEFENV=$enableval,
+   CFG_WITH_DEFENV=yes)
 AC_SUBST(CFG_WITH_DEFENV)
 
-dnl Checks for programs.
+dnl Compiler flags
 CXX=g++
+CFLAGS=-I${includedir}
+CPPFLAGS=-I${includedir}
+CXXFLAGS=-I${includedir}
+LDFLAGS=-L${libdir}
+
+dnl Checks for programs.
 AC_PROG_CC
 AC_PROG_CXX
 AC_PROG_INSTALL
+
+AC_LANG_PUSH(C++)
+AC_MSG_CHECKING([that C++ compiler can compile simple program])
+AC_TRY_RUN([int main() { return 0; }],
+           AC_MSG_RESULT(yes),
+           AC_MSG_RESULT(no);AC_MSG_ERROR([a working C++ compiler is required]))
+
 AC_PATH_PROG(PERL,perl)
 if test "x$PERL" = "x" ; then
    AC_MSG_ERROR([Cannot find "perl" in your PATH, please install it])

include/verilated.cpp

@@ -1,4 +1,4 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
 // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@@ -9,7 +9,7 @@
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //=========================================================================
 ///
 /// \file
@@ -18,7 +18,7 @@
 ///	This file must be compiled and linked against all objects
 ///	created from Verilator.
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //=========================================================================
 
@@ -86,7 +86,7 @@ IData VL_RAND_RESET_I(int outBits) {
     if (Verilated::randReset()!=1) {	// if 2, randomize
 	data = VL_RAND32();
     }
-    if (outBits<32) data &= VL_MASK_I(outBits); 
+    if (outBits<32) data &= VL_MASK_I(outBits);
     return data;
 }
 
@@ -96,7 +96,7 @@ QData VL_RAND_RESET_Q(int outBits) {
     if (Verilated::randReset()!=1) {	// if 2, randomize
 	data = ((QData)VL_RAND32()<<VL_ULL(32)) | (QData)VL_RAND32();
     }
-    if (outBits<64) data &= VL_MASK_Q(outBits); 
+    if (outBits<64) data &= VL_MASK_Q(outBits);
     return data;
 }
 
@@ -276,7 +276,7 @@ void VL_READMEM_W(bool hex, int width, int depth, int array_lsb, int fnwords,
 	else if (c=='\t' || c==' ' || c=='\r' || c=='\f') { if (innum) reading_addr=false; innum=false; }
 	// Skip // comments and detect /* comments
 	else if (ignore_to_cmt && lastc=='*' && c=='/') {
-	    ignore_to_cmt = false; if (innum) reading_addr=false; innum=false; 
+	    ignore_to_cmt = false; if (innum) reading_addr=false; innum=false;
 	} else if (!ignore_to_eol && !ignore_to_cmt) {
 	    if (lastc=='/' && c=='*') { ignore_to_cmt = true; }
 	    else if (lastc=='/' && c=='/') { ignore_to_eol = true; }
@@ -355,7 +355,7 @@ const char* Verilated::catName(const char* n1, const char* n2) {
     // Used by symbol table creation to make module names
     static char* strp = NULL;
     static int   len  = -1;
-    int newlen = strlen(n1)+strlen(n2)+2;    
+    int newlen = strlen(n1)+strlen(n2)+2;
     if (newlen > len) {
 	if (strp) delete [] strp;
 	strp = new char[newlen];

include/verilated.h

@@ -1,4 +1,4 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
 // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@@ -9,7 +9,7 @@
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //*************************************************************************
 ///
 /// \file
@@ -19,7 +19,7 @@
 ///	all C++ files it generates.  It contains standard macros and
 ///	classes required by the Verilated code.
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //*************************************************************************
 
@@ -129,7 +129,7 @@ struct Verilated {
     // Extern Vars
     // Below two are used as bool, but having as uint32_t avoids conversion time
 private:
-    static int  	s_randReset;		///< Random reset: 0=all 0s, 1=all 1s, 2=random
+    static int		s_randReset;		///< Random reset: 0=all 0s, 1=all 1s, 2=random
     static int		s_debug;		///< See accessors... only when VL_DEBUG set
     static bool		s_calcUnusedSigs;	///< Waves file on, need all signals calculated
     static bool		s_gotFinish;		///< A $finish statement executed
@@ -152,7 +152,7 @@ public:
 #endif
     /// Internal: Create a new module name by concatenating two strings
     static const char* catName(const char* n1, const char* n2); // Returns new'ed data
-    /// Enable calculation of unused signals 
+    /// Enable calculation of unused signals
     static void calcUnusedSigs(bool flag) { s_calcUnusedSigs=flag; }
     static bool calcUnusedSigs() { return s_calcUnusedSigs; }	///< Return calcUnusedSigs value
     /// Did the simulation $finish?
@@ -165,7 +165,7 @@ public:
     /// Enable/disable assertions
     static void assertOn(bool flag) { s_assertOn=flag; }
     static bool assertOn() { return s_assertOn; }
-};    
+};
 
 //=========================================================================
 // Extern functions -- User may override -- See verilated.cpp
@@ -236,7 +236,7 @@ static inline QData  VL_EXTENDSIGN_Q(int lbits, QData lhs) { return (-((lhs)&(VL
 
 // Debugging prints
 static inline void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) {
-    printf("  Data: w%d: ", lbits); 
+    printf("  Data: w%d: ", lbits);
     for (int i=VL_WORDS_I(lbits)-1; i>=0; i--) { printf("%08x ",iwp[i]); }
     printf("\n");
 }
@@ -460,43 +460,92 @@ static inline IData VL_REDOR_W(int words, WDataInP lwp) {
 }
 
 // EMIT_RULE: VL_REDXOR:  oclean=dirty; obits=1;
-static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
-    IData r = lwp[0];
-    for (int i=1; i < words; i++) r ^= lwp[i];
-    r=(r^(r>>1));
-    r=(r^(r>>2));
-    r=(r^(r>>4));
-    r=(r^(r>>8));
-    r=(r^(r>>16));
-    return r;
-}
 static inline IData VL_REDXOR_2(IData r) {
+    // Experiments show VL_REDXOR_2 is faster than __builtin_parityl
     r=(r^(r>>1));
     return r;
 }
 static inline IData VL_REDXOR_4(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_8(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_16(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_32(IData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityl(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8)); r=(r^(r>>16));
     return r;
+#endif
 }
 static inline IData VL_REDXOR_64(QData r) {
+#if defined(__GNUC__) && (__GNUC__ >= 4) && !defined(VL_NO_BUILTINS)
+    return __builtin_parityll(r);
+#else
     r=(r^(r>>1)); r=(r^(r>>2)); r=(r^(r>>4)); r=(r^(r>>8)); r=(r^(r>>16)); r=(r^(r>>32));
     return r;
+#endif
+}
+static inline IData VL_REDXOR_W(int words, WDataInP lwp) {
+    IData r = lwp[0];
+    for (int i=1; i < words; i++) r ^= lwp[i];
+    return VL_REDXOR_32(r);
+}
+
+static inline IData VL_CLOG2_I(IData lhs) {
+    // Perhaps can do better using fls GCC4 builtins
+    int n=1;
+    IData chk;
+    if (!lhs) return 0;
+    chk = lhs >> VL_UL(16); if (chk) { n += 16; lhs = chk; }
+    chk = lhs >> VL_UL(8);  if (chk) { n += 8; lhs = chk; }
+    chk = lhs >> VL_UL(4);  if (chk) { n += 4; lhs = chk; }
+    chk = lhs >> VL_UL(2);  if (chk) { n += 2; lhs = chk; }
+    chk = lhs >> VL_UL(1);  if (chk) { n += 1; lhs = chk; }
+    return n;
+}
+static inline IData VL_CLOG2_Q(QData lhs) {
+    // Perhaps can do better using fls GCC4 builtins
+    int n=1;
+    QData chk;
+    if (!lhs) return 0;
+    chk = lhs >> VL_ULL(32); if (chk) { n += 32; lhs = chk; }
+    chk = lhs >> VL_ULL(16); if (chk) { n += 16; lhs = chk; }
+    chk = lhs >> VL_ULL(8);  if (chk) { n += 8; lhs = chk; }
+    chk = lhs >> VL_ULL(4);  if (chk) { n += 4; lhs = chk; }
+    chk = lhs >> VL_ULL(2);  if (chk) { n += 2; lhs = chk; }
+    chk = lhs >> VL_ULL(1);  if (chk) { n += 1; lhs = chk; }
+    return n;
+}
+static inline IData VL_CLOG2_W(int words, WDataInP lwp) {
+    for (int i=words-1; i>=0; i--) {
+	if (lwp[i]) return VL_CLOG2_I(lwp[i])+i*VL_WORDSIZE;
+    }
+    return 0;
 }
 
 // EMIT_RULE: VL_COUNTONES_II:  oclean = false; lhs clean
 static inline IData VL_COUNTONES_I(IData lhs) {
+    // This is faster than __builtin_popcountl
     IData r = lhs - ((lhs >> 1) & 033333333333) - ((lhs >> 2) & 011111111111);
     r = (r + (r>>3)) & 030707070707;
     r = (r + (r>>6));
@@ -829,7 +878,7 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
     return out;
 }
 
-#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs) 
+#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
 
 static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
     if (lhs==0) return 0;
@@ -847,23 +896,23 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
 
 // INTERNAL: Stuff LHS bit 0++ into OUTPUT at specified offset
 // ld may be "dirty", output is clean
-static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) {
     IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) {
     IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) {
     IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) {
     QData insmask = (VL_MASK_Q(hbit-lbit+1))<<lbit;
     lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
 }
-static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) {
     int hoffset = VL_BITBIT_I(hbit);
     int loffset = VL_BITBIT_I(lbit);
     if (hoffset==VL_SIZEBITS_I && loffset==0) {
@@ -888,7 +937,7 @@ static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbi
 
 // INTERNAL: Stuff large LHS bit 0++ into OUTPUT at specified offset
 // lwp may be "dirty"
-static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) { 
+static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) {
     int hoffset = hbit & VL_SIZEBITS_I;
     int loffset = lbit & VL_SIZEBITS_I;
     int lword = VL_BITWORD_I(lbit);
@@ -934,7 +983,7 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int
     }
 }
 
-static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) { 
+static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) {
     WData lwp[2]; VL_SET_WQ(lwp,ld);
     _VL_INSERT_WW(obits,owp,lwp,hbit,lbit);
 }
@@ -1214,7 +1263,7 @@ static inline QData VL_SEL_QWII(int, int lbits, int, int, WDataInP lwp, IData ls
 static inline WDataOutP VL_SEL_WWII(int obits,int lbits,int,int,WDataOutP owp,WDataInP lwp, IData lsb, IData width) {
     int msb = lsb+width-1;
     int word_shift = VL_BITWORD_I(lsb);
-    if (msb>lbits) { // Outside bounds, 
+    if (msb>lbits) { // Outside bounds,
 	for (int i=0; i<VL_WORDS_I(obits)-1; i++) owp[i] = ~0;
 	owp[VL_WORDS_I(obits)-1] = VL_MASK_I(obits);
     } else if (VL_BITBIT_I(lsb)==0) {
@@ -1311,32 +1360,32 @@ static inline WDataOutP VL_CONST_W_3X(int obits, WDataOutP o,
     o[0]=d0;  o[1]=d1;  o[2]=d2;
     _END(obits,3);  }
 #define VL_HAVE_CONST_W_4X
-static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o, 
+static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o,
 				      I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;
     _END(obits,4);  }
 #define VL_HAVE_CONST_W_5X
-static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o, 
+static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o,
 				      I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;
     _END(obits,5);  }
 #define VL_HAVE_CONST_W_6X
-static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o, 
+static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o,
 				      I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;
     _END(obits,6);  }
 #define VL_HAVE_CONST_W_7X
-static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o, 
+static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o,
 				      I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;
     _END(obits,7);  }
 #define VL_HAVE_CONST_W_8X
-static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o, 
+static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o,
 				      I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;
     _END(obits,8);  }
 #define VL_HAVE_CONST_W_9X
-static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o, 
+static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o,
 				      I d8,
 				      I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
     o[0]=d0;  o[1]=d1;  o[2]=d2;  o[3]=d3;  o[4]=d4;  o[5]=d5;  o[6]=d6;  o[7]=d7;

include/verilated.mk.in

@@ -1,4 +1,4 @@
-# $Id$ -*- Makefile -*-
+# -*- Makefile -*-
 ######################################################################
 # DESCRIPTION: Makefile commands for all verilated target files
 #
@@ -44,7 +44,7 @@ CPPFLAGS += -I. $(VK_CPPFLAGS_ALWAYS) $(VK_CPPFLAGS_WALL)
 VPATH += ..
 VPATH += $(VERILATOR_ROOT)/include
 
-#OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE 
+#OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE
 #OPT = -ggdb -DPRINTINITSTR
 CPPFLAGS += $(OPT)
 
@@ -59,11 +59,11 @@ LDFLAGS  += $(USER_LDFLAGS)
 # See the benchmarking section of bin/verilator.
 # Support class optimizations.  This includes the tracing and symbol table.
 # SystemC takes minutes to optimize, thus it is off by default.
-#OPT_SLOW = 
+#OPT_SLOW =
 # Fast path optimizations.  Most time is spent in these classes.
 #OPT_FAST = -O2 -fstrict-aliasing
 #OPT_FAST = -O
-#OPT_FAST = 
+#OPT_FAST =
 
 #######################################################################
 ##### Aggregates

include/verilated.v

@@ -1,7 +1,7 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 //*************************************************************************
 //
@@ -13,7 +13,7 @@
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //=========================================================================
 //
 // DESCRIPTION: Verilator: Include in verilog files to hide verilator defines
@@ -25,7 +25,7 @@
  `ifdef verilator `else
   `define coverage_block_off
  `endif
- 
+
  // Hide file descriptor difference
  `ifdef verilator
   `define verilator_file_descriptor reg [63:0]

include/verilatedos.h

@@ -1,4 +1,4 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 //
 // Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@@ -9,7 +9,7 @@
 // but WITHOUT ANY WARRANTY; without even the implied warranty of
 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 // GNU General Public License for more details.
-// 
+//
 //*************************************************************************
 ///
 /// \file
@@ -21,7 +21,7 @@
 ///	config_build.h.in, code needed by Verilated code only goes into
 ///	verilated.h, and code needed by both goes here (verilatedos.h).
 ///
-/// Code available from: http://www.veripool.com/verilator
+/// Code available from: http://www.veripool.org/verilator
 ///
 //*************************************************************************
 
@@ -84,7 +84,7 @@ typedef unsigned char           vluint8_t;	///< 8-bit unsigned type
 typedef unsigned short int      vluint16_t;	///< 16-bit unsigned type
 typedef long  			vlsint32_t;	///< 32-bit signed type
 typedef unsigned long           vluint32_t;	///< 32-bit unsigned type
-typedef long long      		vlsint64_t;	///< 64-bit signed type
+typedef long long		vlsint64_t;	///< 64-bit signed type
 typedef unsigned long long      vluint64_t;	///< 64-bit unsigned type
 #elif defined(_WIN32) && !defined(__MINGW32__)
 typedef unsigned char           uint8_t;	///< 8-bit unsigned type (backward compatibility)
@@ -92,18 +92,18 @@ typedef unsigned short int      uint16_t;	///< 16-bit unsigned type (backward co
 typedef unsigned long           uint32_t;	///< 32-bit unsigned type (backward compatibility)
 typedef unsigned char           vluint8_t;	///< 8-bit unsigned type
 typedef unsigned short int      vluint16_t;	///< 16-bit unsigned type
-typedef int  			vlsint32_t;	///< 32-bit signed type
+typedef int			vlsint32_t;	///< 32-bit signed type
 typedef unsigned int            vluint32_t;	///< 32-bit unsigned type
-typedef __int64      		vlsint64_t;	///< 64-bit signed type
+typedef __int64			vlsint64_t;	///< 64-bit signed type
 typedef unsigned __int64        vluint64_t;	///< 64-bit unsigned type
 #else // Linux or compliant Unix flavors, -m64
 # include <stdint.h>	// Linux and most flavors
 # include <inttypes.h>	// Solaris
 typedef uint8_t			vluint8_t;	///< 32-bit unsigned type
 typedef uint16_t		vluint16_t;	///< 32-bit unsigned type
-typedef int  			vlsint32_t;	///< 32-bit signed type
+typedef int			vlsint32_t;	///< 32-bit signed type
 typedef uint32_t		vluint32_t;	///< 32-bit signed type
-typedef long long      		vlsint64_t;	///< 64-bit signed type
+typedef long long		vlsint64_t;	///< 64-bit signed type
 typedef unsigned long long	vluint64_t;	///< 64-bit unsigned type
 #endif
 

install-sh

@@ -115,7 +115,7 @@ fi
 if [ x"$dir_arg" != x ]; then
 	dst=$src
 	src=""
-	
+
 	if [ -d $dst ]; then
 		instcmd=:
 	else

mkinstalldirs

@@ -4,8 +4,6 @@
 # Created: 1993-05-16
 # Public domain
 
-# $Id:$
-
 errstatus=0
 
 for file

nodist/bisonreader

@@ -1,5 +1,4 @@
 #!/usr/bin/perl -w
-#$Id$
 ######################################################################
 #
 # Copyright 2007-2008 by Wilson Snyder.
@@ -7,16 +6,16 @@
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of either the GNU General Public License or the
 # Perl Artistic License.
-# 
+#
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-# 
+#
 # You should have received a copy of the Perl Artistic License
 # along with this module; see the file COPYING.  If not, see
 # www.cpan.org
-#                                                                           
+#
 ######################################################################
 
 # DESCRIPTION: Debugging of bison output

nodist/dot_importer

@@ -1,5 +1,4 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
 # Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
@@ -50,7 +49,6 @@ cwrite ("graph_export.cpp");
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -120,7 +118,7 @@ sub cwrite {
     foreach my $edge (@Edges) {
 	$fh->printf("    new V3GraphEdge(gp, %s, %s, %s, %s);\n",
 		    $edge->{from}, $edge->{to},
-		    $edge->{weight}, $edge->{cutable}?"true":"false");	       
+		    $edge->{weight}, $edge->{cutable}?"true":"false");
     }
     $fh->print("}\n");
 }

nodist/dot_pruner

@@ -1,5 +1,4 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
 # Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
@@ -55,7 +54,6 @@ dotwrite();
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -175,7 +173,7 @@ __END__
 
 =head1 NAME
 
-dot_pruner - 
+dot_pruner -
 
 =head1 SYNOPSIS
 

nodist/invoke_ncverilog

@@ -1,5 +1,4 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
 # Copyright 2007-2008 by Wilson Snyder <[email protected]>.  This

nodist/leakchecking.txt

@@ -0,0 +1,4 @@
+export GLIBCPP_FORCE_NEW=1
+compile with -DVL_LEAK_CHECKS
+valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc -f /home/wsnyder/src/verilator/v4/verilator/test_c/../test_v/input.vc top.v --no-skip-identical 2>&1 | tee ~/d/aa
+valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc /home/wsnyder/src/verilator/v4/verilator/test_regress/t/t_case_huge.v --no-skip-identical -I/home/wsnyder/src/verilator/v4/verilator/test_regress/t 2>&1 | tee ~/d/aa

nodist/vtree_importer

@@ -1,5 +1,4 @@
 #!/usr/bin/perl -w
-# $Id$
 ######################################################################
 #
 # Copyright 2005-2008 by Wilson Snyder <[email protected]>.  This
@@ -52,7 +51,6 @@ print '(query-replace-regexp "(\\([0-9a-z_]+\\))" "\\1" nil nil nil)',"\n";
 #----------------------------------------------------------------------
 
 sub usage {
-    print '$Id$ ', "\n";
     pod2usage(-verbose=>2, -exitval => 2);
     exit (1);
 }
@@ -292,7 +290,7 @@ sub p_var {
     }
     p "\t";
     {
-	local $Avoid_Hex=1; 
+	local $Avoid_Hex=1;
 	t1;
     }
     p "\t";
@@ -322,7 +320,7 @@ __END__
 
 =head1 NAME
 
-vtree_importer - 
+vtree_importer -
 
 =head1 SYNOPSIS
 

readme.texi

@@ -1,6 +1,5 @@
 \input texinfo @c -*-texinfo-*-
 @c %**start of header
-$c $Id$
 @setfilename readme.info
 @settitle Verilator Installation
 @c %**end of header
@@ -15,13 +14,13 @@ $c $Id$
 This is the Verilator Package.
 
 @menu
-* Copyright::                   
-* Description::                 
-* Obtaining Distribution::      
-* Directory Structure::         
-* Supported Systems::           
-* Installation::                
-* Limitations::                 
+* Copyright::
+* Description::
+* Obtaining Distribution::
+* Directory Structure::
+* Supported Systems::
+* Installation::
+* Limitations::
 @end menu
 
 @node Copyright, Description, Top, Top
@@ -45,7 +44,7 @@ Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
 reads the specified Verilog code, lints it, and optionally adds coverage
 code.  For C++ format, it outputs .cpp and .h files.  For SystemC format,
 it outputs .sp files for the SystemPerl preprocessor available at
-http://veripool.com.
+http://www.veripool.org.
 
 The resulting files are then compiled with C++.  The user writes a little
 C++ wrapper file, which instantiates the top level module.  This is
@@ -56,11 +55,11 @@ The resulting executable will perform the actual simulation.
 @node Obtaining Distribution, Directory Structure, Description, Top
 @section Obtaining Distribution
 
-The latest version is available at 
-@uref{http://veripool.com/verilator.htm}
+The latest version is available at
+@uref{http://www.veripool.org/verilator}
 
 Download the latest package from that site, and decompress.
-@samp{gunzip verilator_version.tar.gz ; tar xvf verilator_version.tar}
+@samp{tar xvzf verilator_version.tgz}
 
 @node Directory Structure, Supported Systems, Obtaining Distribution, Top
 @section Directory Structure

src/Makefile.in

@@ -1,9 +1,9 @@
-# $Id$ */
+# -*- Makefile -*-
 #*****************************************************************************
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 #
 #*****************************************************************************
 #
@@ -40,7 +40,7 @@ export OBJCACHE_HOSTS := $(shell rschedule --no-allow-reserved --similar hostnam
 endif
 
 ifeq ($(OBJCACHE_HOSTS),)
-export OBJCACHE := 
+export OBJCACHE :=
 else
 export OBJCACHE_JOBS := -j $(shell objcache --jobs "$(OBJCACHE_HOSTS)")
 export OBJCACHE := @objcache --read --write
@@ -74,7 +74,7 @@ prefiles::
 ifeq ($(VERILATOR_AUTHOR_SITE),1)	# Local... Else don't burden users
 prefiles:: config_rev.h
 # This output goes into srcdir, as we need to distribute it as part of the kit.
-config_rev.h:	config_rev.pl .svn/entries
+config_rev.h:	config_rev.pl ../.git/index
 	$(PERL) config_rev.pl . >$@
 endif
 

src/Makefile_obj.in

@@ -1,9 +1,9 @@
-# $Id$ -*- Makefile -*-
+# -*- Makefile -*-
 #*****************************************************************************
 #
 # DESCRIPTION: Verilator: Makefile for verilog source
 #
-# Code available from: http://www.veripool.com/verilator
+# Code available from: http://www.veripool.org/verilator
 #
 #*****************************************************************************
 #
@@ -23,21 +23,30 @@
 srcdir = ..
 incdir = ../../include
 
-PERL = @PERL@
+# Programs
 CC = @CC@
 CXX = @CXX@
 LINK = @CXX@
-
-LDFLAGS += @LDFLAGS@
-
-CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
+LEX = @LEX@
+LFLAGS = -d
+PERL = @PERL@
+YACC = @YACC@
+YFLAGS = -y -d -v
 
 prefix = @prefix@
 
+# Directory in which to install data across multiple architectures
+datarootdir = @datarootdir@
+
 # Directory in which to install package specific files
 # Generally ${prefix}/share/verilator
 pkgdatadir = @pkgdatadir@
 
+# Compile options
+CFG_WITH_DEFENV = @CFG_WITH_DEFENV@
+CPPFLAGSNOWALL += @CPPFLAGS@
+LDFLAGS += @LDFLAGS@
+
 #### End of system configuration section. ####
 
 VPATH += . $(srcdir)
@@ -56,17 +65,12 @@ COPT = -ggdb -DVL_DEBUG
 endif
 #################
 
-LEX = @LEX@
-LFLAGS = -d
-YACC = @YACC@
-YFLAGS = -y -d -v
-
 #LIBS += -ldl
 #CCMALLOC = /usr/local/lib/ccmalloc-gcc.o -lccmalloc -ldl
 
 LIBS = -lm -lfl
 
-CPPFLAGSNOWALL = -MMD
+CPPFLAGSNOWALL += -MMD
 CPPFLAGSNOWALL += -I. -I$(srcdir) -I$(incdir)
 CPPFLAGSNOWALL += -DYYDEBUG 	# Required to get nice error messages
 #CPPFLAGSNOWALL += -DVL_LEAK_CHECKS 	# If running valgrind or other hunting tool
@@ -80,7 +84,7 @@ endif
 
 # Allow RPM builds to specify hardcoded data directories
 # To do this:
-ifneq ($(CFG_WITH_DEFENV),)
+ifeq ($(CFG_WITH_DEFENV),yes)
  CPPFLAGS += -DDEFENV_SYSTEMC=\"$(SYSTEMC)\"
  CPPFLAGS += -DDEFENV_SYSTEMC_ARCH=\"$(SYSTEMC_ARCH)\"
  CPPFLAGS += -DDEFENV_SYSTEMPERL=\"$(SYSTEMPERL)\"
@@ -242,14 +246,19 @@ V3PreProc.o:	V3PreProc.cpp V3PreLex.yy.cpp
 #### Generated files
 
 # Target rule called before parallel build to make generated files
-serial:: V3Ast__gen_classes.h
+serial:: V3Ast__gen_classes.h y.tab.c
 
 V3Ast__gen_classes.h : $(ASTGEN) V3Ast.h V3AstNodes.h
 	$(PERL) $(ASTGEN) -I$(srcdir)  --classes
 
-y.tab.c y.tab.h:	verilog.y $(HEADERS)
+y.tab.h: y.tab.c
+
+# Have only one output file in this rule to prevent parallel make issues
+y.tab.c: verilog.y $(HEADERS)
 	@echo "If you get errors from verilog.y below, try upgrading bison to version 1.875 or newer."
 	${YACC} ${YFLAGS} $<
+	mv y.tab.c y_pregen.tab.c && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.c > y.tab.c
+	mv y.tab.h y_pregen.tab.h && $(PERL) $(srcdir)/bisonfix < y_pregen.tab.h > y.tab.h
 
 V3Lexer_pregen.yy.cpp:	verilog.l y.tab.h $(HEADERS)
 	${LEX} ${LFLAGS} -o$@ $<

src/V3Active.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Active's Transformations:
-//		
+//
 // Note this can be called multiple times.
 //   Create a IACTIVE(initial), SACTIVE(combo)
 //	ALWAYS: Remove any-edges from sense list

src/V3Active.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3ActiveTop.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity active domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Active's Transformations:
-//		
+//
 // Note this can be called multiple times.
 //   Across all ACTIVES
 //	SenTrees are now under each ACTIVE statement, we want them global:

src/V3ActiveTop.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Assert.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -106,7 +105,7 @@ private:
 	sentreep->unlinkFrBack();
 	//
 	AstNode* bodysp = NULL;
-	bool selfDestruct = false;	
+	bool selfDestruct = false;
 	if (AstPslCover* snodep = nodep->castPslCover()) {
 	    if (!v3Global.opt.coverageUser()) {
 		selfDestruct = true;

src/V3Assert.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion expansion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3AssertPre.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Collect and print statistics
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3AssertPre.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Assertion pre-expansion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Ast.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -255,8 +254,8 @@ void AstNode::addNextHere(AstNode* newp) {
 void AstNode::setOp1p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp1p\n");
     UDEBUGONLY(if (m_op1p) this->v3fatalSrc("Adding to non-empty, non-list op1"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1"););
     this->debugTreeChange("-setOp1pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp1pNew: ", __LINE__, true);
     m_op1p = newp;
@@ -268,8 +267,8 @@ void AstNode::setOp1p(AstNode* newp) {
 void AstNode::setOp2p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp2p\n");
     UDEBUGONLY(if (m_op2p) this->v3fatalSrc("Adding to non-empty, non-list op2"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2"););
     this->debugTreeChange("-setOp2pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp2pNew: ", __LINE__, true);
     m_op2p = newp;
@@ -281,8 +280,8 @@ void AstNode::setOp2p(AstNode* newp) {
 void AstNode::setOp3p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp3p\n");
     UDEBUGONLY(if (m_op3p) this->v3fatalSrc("Adding to non-empty, non-list op3"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3"););
     this->debugTreeChange("-setOp3pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp3pNew: ", __LINE__, true);
     m_op3p = newp;
@@ -294,8 +293,8 @@ void AstNode::setOp3p(AstNode* newp) {
 void AstNode::setOp4p(AstNode* newp) {
     UASSERT(newp,"Null item passed to setOp4p\n");
     UDEBUGONLY(if (m_op4p) this->v3fatalSrc("Adding to non-empty, non-list op4"););
-    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node");); 
-    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4");); 
+    UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
+    UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4"););
     this->debugTreeChange("-setOp4pThs: ", __LINE__, false);
     newp->debugTreeChange("-setOp4pNew: ", __LINE__, true);
     m_op4p = newp;
@@ -644,7 +643,7 @@ void AstNode::iterateListBackwards(AstNVisitor& v, AstNUser* vup) {
     while (nodep->m_nextp) nodep=nodep->m_nextp;
     while (nodep) {
 	// Edits not supported: nodep->m_iterpp = &nodep;
-  	nodep->accept(v, vup);
+	nodep->accept(v, vup);
 	if (nodep->backp()->m_nextp == nodep) nodep=nodep->backp();
 	else nodep = NULL;  // else: backp points up the tree.
     }
@@ -665,7 +664,7 @@ void AstNode::iterateAndNext(AstNVisitor& v, AstNUser* vup) {
     for (AstNode* nodep=this; nodep;) {
 	AstNode* niterp = nodep;
 	niterp->m_iterpp = &niterp;
-  	niterp->accept(v, vup);
+	niterp->accept(v, vup);
 	// accept may do a replaceNode and change niterp on us...
 	if (!niterp) return;
 	niterp->m_iterpp = NULL;
@@ -682,7 +681,7 @@ void AstNode::iterateAndNextIgnoreEdit(AstNVisitor& v, AstNUser* vup) {
     if (!this) return;
     for (AstNode* nodep=this; nodep; ) {
 	AstNode* nnextp = nodep->m_nextp;
-  	nodep->accept(v, vup);
+	nodep->accept(v, vup);
 	nodep = nnextp;
     }
 }

src/V3Ast.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -1009,7 +1009,7 @@ public:
     AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp)
 	:AstNode(fl)
 	, m_taskp(NULL) {
-	setOp1p(namep);	addNOp2p(pinsp); 
+	setOp1p(namep);	addNOp2p(pinsp);
     }
     virtual ~AstNodeFTaskRef() {}
     virtual bool broken() const { return m_taskp && !m_taskp->brokeExists(); }

src/V3AstNodes.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structures
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -304,6 +303,10 @@ void AstCellInline::dump(ostream& str) {
     this->AstNode::dump(str);
     str<<" -> "<<origModName();
 }
+void AstDisplay::dump(ostream& str) {
+    this->AstNode::dump(str);
+    //str<<" "<<displayType().ascii();
+}
 void AstPin::dump(ostream& str) {
     this->AstNode::dump(str);
     if (modVarp()) { str<<" -> "; modVarp()->dump(str); }

src/V3AstNodes.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Ast node structure
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -254,7 +254,7 @@ private:
 	m_sc=false; m_scClocked=false; m_scSensitive=false;
 	m_usedClock=false; m_usedParam=false;
 	m_sigPublic=false; m_sigModPublic=false;
-	m_funcLocal=false; m_funcReturn=false; 
+	m_funcLocal=false; m_funcReturn=false;
 	m_attrClockEn=false; m_attrIsolateAssign=false;
 	m_fileDescr=false; m_isConst=false; m_isStatic=false;
 	m_trace=false;
@@ -554,7 +554,7 @@ public:
     virtual AstNode* clone() { return new AstVarXRef(*this);}
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
     virtual void dump(ostream& str);
-    string	dotted() const { return m_dotted; }	
+    string	dotted() const { return m_dotted; }
     string	prettyDotted() const { return prettyName(dotted()); }
     string	inlinedDots() const { return m_inlinedDots; }
     void	inlinedDots(const string& flag) { m_inlinedDots = flag; }
@@ -755,7 +755,7 @@ public:
     AstNode*	stmtsp() 	const { return op1p()->castNode(); }	// op1 = List of statements
     void addStmtp(AstNode* nodep) { addOp1p(nodep); }
 };
-  
+
 struct AstGenerate : public AstNode {
     // A Generate/end block
     // Parents: MODULE
@@ -1117,7 +1117,7 @@ private:
 public:
     AstCoverDecl(FileLine* fl, int column, const string& type, const string& comment)
 	: AstNodeStmt(fl) {
-	m_text = comment; m_typeText = type; m_column = column; 
+	m_text = comment; m_typeText = type; m_column = column;
     }
     virtual ~AstCoverDecl() {}
     virtual AstType type() const { return AstType::COVERDECL;}
@@ -1254,6 +1254,7 @@ public:
     virtual AstType type() const { return AstType::DISPLAY;}
     virtual AstNode* clone() { return new AstDisplay(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void dump(ostream& str);
     virtual string verilogKwd() const { return (filep() ? (string)"$f"+(string)displayType().ascii()
 						: (string)"$"+(string)displayType().ascii()); }
     virtual bool isGateOptimizable() const { return false; }
@@ -1970,6 +1971,20 @@ struct AstUnsigned : public AstNodeUniop {
     virtual bool sizeMattersLhs() {return true;}  // Eliminated before matters
     virtual int instrCount()	const { return 0; }
 };
+struct AstCLog2 : public AstNodeUniop {
+    AstCLog2(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}
+    virtual ~AstCLog2() {}
+    virtual AstType type() const { return AstType::CLOG2;}
+    virtual AstNode* clone() { return new AstCLog2(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opCLog2(lhs); }
+    virtual string emitVerilog() { return "%k$clog2(%l)"; }
+    virtual bool emitWordForm() { return true; }
+    virtual string emitOperator() { return "VL_CLOG2"; }
+    virtual bool cleanOut() {return false;} virtual bool cleanLhs() {return true;}
+    virtual bool sizeMattersLhs() {return false;}
+    virtual int instrCount()	const { return widthInstrs()*16; }
+};
 struct AstCountOnes : public AstNodeUniop {
     // Number of bits set in vector
     AstCountOnes(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {}

src/V3Begin.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Begin's Transformations:
-//		
+//
 // Each module:
 //	Look for BEGINs
 //	    BEGIN(VAR...) -> VAR ... {renamed}
@@ -32,6 +31,7 @@
 #include <stdio.h>
 #include <stdarg.h>
 #include <unistd.h>
+#include <cstring>
 #include <algorithm>
 #include <vector>
 

src/V3Begin.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Removal of named begin blocks
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Branch.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Branch.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Branch prediction
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Broken.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Broken's Transformations:
-//		
+//
 // Entire netlist
 //	Mark all nodes
 //	Check all links point to marked nodes

src/V3Broken.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Find broken links in tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Case.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Case's Transformations:
-//		
+//
 // Each module:
 //	TBD: Eliminate tristates by adding __in, __inen, __en wires in parallel
 //	    Need __en in changed list if a signal is on the LHS of a assign
@@ -235,7 +234,7 @@ private:
 	    //                            new AstConst(cexprp->fileline(), nummask));
 	    AstNode* and1p = new AstSel(cexprp->fileline(), cexprp->cloneTree(false),
 					msb, 1);
-	    AstNode* eqp = new AstNeq(cexprp->fileline(), 
+	    AstNode* eqp = new AstNeq(cexprp->fileline(),
 				      new AstConst(cexprp->fileline(), 0),
 				      and1p);
 	    AstIf* ifp = new AstIf(cexprp->fileline(), eqp, tree1p, tree0p);
@@ -293,7 +292,7 @@ private:
 		for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondNextp) {
 		    icondNextp = icondp->nextp();
 		    icondp->unlinkFrBack();
-		    
+
 		    AstNode* and1p;
 		    AstNode* and2p;
 		    AstConst* iconstp = icondp->castConst();
@@ -305,7 +304,7 @@ private:
 			numval.opBitsOne(iconstp->num());
 			and1p = new AstAnd(itemp->fileline(), cexprp->cloneTree(false),
 					   new AstConst(itemp->fileline(), nummask));
-			and2p = new AstAnd(itemp->fileline(), 
+			and2p = new AstAnd(itemp->fileline(),
 					   new AstConst(itemp->fileline(), numval),
 					   new AstConst(itemp->fileline(), nummask));
 			icondp->deleteTree(); icondp=NULL; iconstp=NULL;

src/V3Case.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Cast.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Cast's Transformations:
-//		
+//
 // Each module:
 //	For each math operator, if above operator requires 32 bits,
 //	and this isn't, cast to 32 bits.
@@ -148,7 +147,7 @@ private:
 	    && nodep->backp()->width()
 	    && castSize(nodep) != castSize(nodep->varp())) {
 	    // Cast vars to IData first, else below has upper bits wrongly set
-	    //  CData x=3;  out = (QData)(x<<30); 
+	    //  CData x=3;  out = (QData)(x<<30);
 	    insertCast (nodep, castSize(nodep));
 	}
 	nodep->user(1);

src/V3Cast.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Add C++ casts across expression size changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Changed.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for changed nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Changed's Transformations:
-//		
+//
 // Each module:
 //	Each combo block
 //	    For each variable that comes from combo block and is generated AFTER a usage

src/V3Changed.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Clean.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for clean nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Clean's Transformations:
-//		
+//
 // Each module:
 //	For each math operator, if it requires a clean operand,
 //	and the operand is dirty, insert a CLEAN node.
@@ -55,7 +54,7 @@ private:
 
     // ENUMS
     enum CleanState { UNKNOWN, CLEAN, DIRTY };
-    
+
     // METHODS
     // Width resetting
     int  cppWidth(AstNode* nodep) {

src/V3Clean.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Clock.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Clock's Transformations:
-//		
+//
 // Top Scope:
 //   Check created ACTIVEs
 //      Compress adjacent ACTIVEs with same sensitivity list
@@ -245,12 +244,12 @@ private:
 	//UINFO(4," MOD   "<<nodep<<endl);
 	m_modp = nodep;
 	m_stableNum = 0;
-  	nodep->iterateChildren(*this);
+	nodep->iterateChildren(*this);
     }
     virtual void visit(AstScope* nodep, AstNUser*) {
 	//UINFO(4," SCOPE   "<<nodep<<endl);
 	m_scopep = nodep;
-  	nodep->iterateChildren(*this);
+	nodep->iterateChildren(*this);
 	if (AstNode* movep = nodep->finalClksp()) {
 	    if (!m_topScopep) nodep->v3fatalSrc("Final clocks under non-top scope");
 	    movep->unlinkFrBackWithNext();
@@ -416,7 +415,7 @@ private:
 					 new AstConst(fl, 1)));
         preUntilp->addNext(new AstAssign(fl, new AstVarRef(fl, countVarp, true),
 					 new AstConst(fl, 0)));
-	
+
 	// Add stable variables & preinits
 	AstNode* setChglastp = NULL;
 	for (AstVarRef* varrefp = nodep->stablesp(); varrefp; varrefp=varrefp->nextp()->castVarRef()) {

src/V3Clock.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Combine.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Combine's Transformations:
-//		
+//
 //	For every function that we spit out
 //	Examine code to find largest common blocks
 //	    Hash each node depth first
@@ -32,7 +31,7 @@
 //		Make new function
 //		Move common block to function
 //		Replace each common block ref with funccall
-//		
+//
 //*************************************************************************
 
 #include "config_build.h"
@@ -392,7 +391,7 @@ private:
 	m_hashed.clear();
 	// Compute hash of all statement trees in the function
 	m_state = STATE_HASH;
-  	nodep->iterateChildren(*this);
+	nodep->iterateChildren(*this);
 	m_state = STATE_IDLE;
 	// Walk the hashes removing empty functions
 	if (emptyFunctionDeletion()) {

src/V3Combine.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Combine common code into functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Const.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Constant folding
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -102,7 +101,7 @@ private:
     bool	m_wremove;	// Inside scope, no assignw removal
     bool	m_warn;		// Output warnings
     bool	m_cpp;		// C++ conversions only
-    AstModule*	m_modp;		// Current module	
+    AstModule*	m_modp;		// Current module
     AstNode*	m_scopep;	// Current scope
     //int debug() { return 9; }
 
@@ -143,7 +142,7 @@ private:
     }
     bool operandIsTwo(AstNode* nodep) {
 	return (nodep->castConst()
-		&& nodep->width() <= VL_QUADSIZE 
+		&& nodep->width() <= VL_QUADSIZE
 		&& nodep->castConst()->asQuad()==2);
     }
     bool operandIsTwostate(AstNode* nodep) {
@@ -745,7 +744,7 @@ private:
 	    // Recurse rather then calling node->iterate to prevent 2^n recursion!
 	    if (operandConcatMove(abConcp)) moveConcat(abConcp);
 	    bcConcp->deleteTree(); bcConcp=NULL;
-	} else { 
+	} else {
 	    AstConcat* abConcp = nodep->lhsp()->castConcat(); abConcp->unlinkFrBack();
 	    AstNode* ap = abConcp->lhsp()->unlinkFrBack();
 	    AstNode* bp = abConcp->rhsp()->unlinkFrBack();
@@ -1017,7 +1016,7 @@ private:
 		 && nodep->ifsp() && nodep->elsesp()) {
 	    UINFO(4,"IF(NOT {x})  => IF(x) swapped if/else"<<nodep<<endl);
 	    AstNode* condp = nodep->condp()->castNot()->lhsp()->unlinkFrBackWithNext();
-	    AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();	
+	    AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
 	    AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext();
 	    AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp);
 	    ifp->branchPred(nodep->branchPred().invert());
@@ -1038,7 +1037,7 @@ private:
 	    nodep->deleteTree(); nodep=NULL;
 	}
 	else if (0	// Disabled, as vpm assertions are faster without due to short-circuiting
-		 && operandIfIf(nodep)) {  
+		 && operandIfIf(nodep)) {
 	    UINFO(0,"IF({a}) IF({b}) => IF({a} && {b})"<<endl);
 	    AstNodeIf* lowerIfp = nodep->ifsp()->castNodeIf();
 	    AstNode* condp = nodep->condp()->unlinkFrBack();

src/V3Const.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Propagate constants across AST
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Coverage.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Netlist (top level) functions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -53,7 +52,7 @@ private:
     bool	m_checkBlock;	// Should this block get covered?
     AstModule*	m_modp;		// Current module to add statement to
     FileMap	m_fileps;	// Column counts for each fileline
-   
+
     //int debug() { return 9; }
 
     // METHODS
@@ -66,7 +65,7 @@ private:
 	    column = (it->second)++;
 	}
 
-	AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment); 
+	AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment);
 	m_modp->addStmtp(declp);
 
 	return new AstCoverInc(fl, declp);

src/V3Coverage.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Coverage modules/signals together
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Dead.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead code elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -21,7 +20,7 @@
 // DEAD TRANSFORMATIONS:
 //	Remove any unreferenced modules
 //	Remove any unreferenced variables
-//	    
+//
 //*************************************************************************
 
 #include "config_build.h"

src/V3Dead.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Dead branch elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Delayed.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for delayed nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,9 +18,9 @@
 //
 //*************************************************************************
 // V3Delayed's Transformations:
-//		
+//
 // Each module:
-//	Replace ASSIGNDLY var, exp 
+//	Replace ASSIGNDLY var, exp
 //	    With   ASSIGNDLY newvar, exp
 //	    At top of block:  VAR  newvar
 //	    At bottom of block: ASSIGNW var newvar
@@ -269,7 +268,7 @@ private:
 	AstAlwaysPost* finalp = varrefp->varScopep()->user4p()->castNode()->castAlwaysPost();
 	if (!finalp) {
 	    finalp = new AstAlwaysPost(nodep->fileline(), NULL/*sens*/, NULL/*body*/);
-	    UINFO(9,"     Created "<<finalp<<endl); 
+	    UINFO(9,"     Created "<<finalp<<endl);
 	    m_activep->addStmtsp(finalp);
 	    varrefp->varScopep()->user4p(finalp);
 	}
@@ -284,7 +283,7 @@ private:
 				    new AstVarRef(nodep->fileline(), setvscp, false),
 				    NULL,
 				    NULL);
-	    UINFO(9,"     Created "<<postLogicp<<endl); 
+	    UINFO(9,"     Created "<<postLogicp<<endl);
 	    finalp->addBodysp(postLogicp);
 	    finalp->user5p(setvscp);	// Remember IF's vset variable
 	    finalp->user4p(postLogicp);	// and the associated IF, as we may be able to reuse it
@@ -347,7 +346,7 @@ private:
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	if (!nodep->user2()) {  // Not done yet
 	    nodep->user2(true);
-	    
+
 	    if (m_inDly && nodep->lvalue()) {
 		UINFO(4,"AssignDlyVar: "<<nodep<<endl);
 		markVarUsage(nodep->varp(), VU_DLY);
@@ -401,7 +400,7 @@ private:
 							m_activep->sensesp());
 		    newactp->addStmtsp(prep);	// Add to FRONT of statements
 		    newactp->addStmtsp(postp);
-		    m_activep->addNext(newactp);					
+		    m_activep->addNext(newactp);
 		    dlyvscp->user2p(newactp);
 		}
 		AstVarRef* newrefp = new AstVarRef(nodep->fileline(), dlyvscp, true);

src/V3Delayed.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Pre C-Emit stage changes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Depth.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Depth's Transformations:
-//		
+//
 // Each module:
 //	For each wide OP, assign a temporary variable.
 //	For each deep expression, assign expression to temporary.
@@ -111,7 +110,7 @@ private:
 	// We have some operator defines that use 2 parens, so += 2.
 	m_depth += 2;
 	if (m_depth>m_maxdepth) m_maxdepth=m_depth;
-	nodep->iterateChildren(*this); 
+	nodep->iterateChildren(*this);
 	m_depth -= 2;
 
 	if (m_stmtp

src/V3Depth.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3DepthBlock.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3DepthBlock's Transformations:
-//		
+//
 // Each module:
 //	For each deep block, create cfunc including that block.
 //

src/V3DepthBlock.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Prevent very deep expressions
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Descope.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -24,7 +23,7 @@
 //		Change varref name() to be relative to current module
 //		Remove varScopep()
 //	    This allows for better V3Combine'ing.
-//	    
+//
 //*************************************************************************
 
 #include "config_build.h"

src/V3Descope.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Rename scope references to module-local references
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3EmitC.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -80,9 +79,9 @@ public:
 
     // METHODS
     void displayEmit(AstDisplay* nodep);
-    string displayFormat(AstNode* widthNode, string in, 
+    string displayFormat(AstNode* widthNode, string in,
 			 char fmtLetter, bool padZero, bool reallyString);
-    void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter); 
+    void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter);
 
     void emitVarDecl(AstVar* nodep, const string& prefixIfImp);
     typedef enum {EVL_IO, EVL_SIG, EVL_TEMP, EVL_STATIC, EVL_ALL} EisWhich;
@@ -212,7 +211,7 @@ public:
     }
     virtual void visit(AstCoverDecl* nodep, AstNUser*) {
 	puts("__vlCoverInsert(");	// As Declared in emitCoverageDecl
-	puts("&__Vcoverage["); 	
+	puts("&__Vcoverage[");
 	puts(cvtToStr(m_coverIds.remap(nodep))); puts("]");
 	puts(", \"");	puts(nodep->fileline()->filebasename()); puts("\"");
 	puts(", ");	puts(cvtToStr(nodep->fileline()->lineno()));
@@ -458,7 +457,7 @@ public:
     // Terminals
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	puts(nodep->hiername());
- 	puts(nodep->varp()->name());
+	puts(nodep->varp()->name());
     }
     void emitConstant(AstConst* nodep, AstVarRef* assigntop, const string& assignString) {
 	// Put out constant set to the specified variable, or given variable in a string
@@ -639,7 +638,7 @@ class EmitCImp : EmitCStmts {
 	puts(modClassName(m_modp)+"::"+nodep->name()
 	     +"("+cFuncArgs(nodep)+") {\n");
 
-	puts("VL_DEBUG_IF(cout<<\"  "); 
+	puts("VL_DEBUG_IF(cout<<\"  ");
 	for (int i=0;i<m_modp->level();i++) { puts("  "); }
 	puts(modClassName(m_modp)+"::"+nodep->name()
 	     +"\"<<endl; );\n");
@@ -1027,10 +1026,8 @@ void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
     emitDispState.clear();
     string fmt = "";
     string::iterator pos = vformat.begin();
-    if (*pos == '"') pos++;
     bool inPct = false;
     for (; pos != vformat.end(); ++pos) {
-	if (pos[0]=='"' && (pos+1)==vformat.end()) break;
 	if (inPct && pos[0]=='%') {
 	    emitDispState.pushFormat("%%");  // We're printf'ing it, so need to quote the %
 	    inPct = false;
@@ -1680,7 +1677,7 @@ void EmitCImp::main(AstModule* modp, bool slow, bool fast) {
     }
 
     emitImp (modp);
-	 
+
     for (AstNode* nodep=modp->stmtsp(); nodep; nodep = nodep->nextp()) {
 	if (AstCFunc* funcp = nodep->castCFunc()) {
 	    if (v3Global.opt.outputSplit() > 1 && splitSize()
@@ -1741,7 +1738,7 @@ class EmitCTrace : EmitCStmts {
 	puts("if (!Verilated::calcUnusedSigs()) vl_fatal(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
 	puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
 	puts("}\n");
-    
+
 	puts("void "+topClassName()+"::traceFull(SpTraceVcd* vcdp, void* userthis, uint32_t code) {\n");
 	puts("// Callback from vcd->dump()\n");
 	puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
@@ -1911,7 +1908,7 @@ class EmitCTrace : EmitCStmts {
     }
     virtual void visit(AstCoverInc* nodep, AstNUser*) {
     }
-    
+
 public:
     EmitCTrace(bool slow) {
 	m_funcp = NULL;

src/V3EmitC.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ code for module tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3EmitCBase.h

@@ -1,8 +1,8 @@
-// $Id$ -*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3EmitCInlines.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3EmitCSyms.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit C++ for tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -68,7 +67,7 @@ class EmitCSyms : EmitCBaseVisitor {
     virtual void visit(AstNetlist* nodep, AstNUser*) {
 	// Collect list of scopes
 	nodep->iterateChildren(*this);
-	
+
 	// Sort m_scopes by scope name
 	sort(m_scopes.begin(), m_scopes.end(), CmpName());
 	// Output

src/V3EmitMk.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3EmitMk.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Makefile
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3EmitV.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog from tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -368,12 +367,12 @@ public:
     // Terminals
     virtual void visit(AstVarRef* nodep, AstNUser*) {
 	puts(nodep->hiername());
- 	puts(nodep->varp()->name());
+	puts(nodep->varp()->name());
     }
     virtual void visit(AstVarXRef* nodep, AstNUser*) {
 	puts(nodep->dotted());
 	puts(".");
- 	puts(nodep->varp()->name());
+	puts(nodep->varp()->name());
     }
     virtual void visit(AstConst* nodep, AstNUser*) {
 	puts(nodep->num().ascii(true,true));

src/V3EmitV.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+//-*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Emit Verilog code for module tree
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Error.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -21,7 +20,7 @@
 
 #include <stdio.h>
 #include <stdarg.h>
-#include <string.h>
+#include <cstring>
 #include <set>
 #include "V3Error.h"
 #ifndef _V3ERROR_NO_GLOBAL_
@@ -47,7 +46,7 @@ bool V3Error::s_pretendError[V3ErrorCode::MAX];
 struct v3errorIniter {
     v3errorIniter() {  V3Error::init(); };
 };
-v3errorIniter v3errorInit; 
+v3errorIniter v3errorInit;
 
 //######################################################################
 // ErrorCode class functions
@@ -203,7 +202,7 @@ void FileLine::deleteAllRemaining() {
     while (1) {
 	FileLineCheckSet::iterator it=fileLineLeakChecks.begin();
 	if (it==fileLineLeakChecks.end()) break;
-	delete *it;  
+	delete *it;
 	// Operator delete will remove the iterated object from the list.
 	// Eventually the list will be empty and terminate the loop.
     }

src/V3Error.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Error handling
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -61,6 +61,7 @@ public:
 	UNUSED,		// No receivers
 	VARHIDDEN,	// Hiding variable
 	WIDTH,		// Width mismatch
+	WIDTHCONCAT,	// Unsized numbers/parameters in concatenations
 	MAX
 	// ***Add new elements below also***
     };
@@ -81,7 +82,7 @@ public:
 	    "COMBDLY", "STMTDLY", "GENCLK", "IMPLICIT", "IMPURE",
 	    "MULTIDRIVEN", "REDEFMACRO",
 	    "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED",
-	    "VARHIDDEN", "WIDTH",
+	    "VARHIDDEN", "WIDTH", "WIDTHCONCAT",
 	    " MAX"
 	};
 	return names[m_e];

src/V3Expand.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Add temporaries, such as for expand nodes
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Expand's Transformations:
-//		
+//
 // Each module:
 //	Expand verilated.h macros into internal micro optimizations (RTL)
 //	this will enable later optimizations.
@@ -168,7 +167,7 @@ private:
 	}
 	return newp;
     }
-	
+
     AstNode* newSelBitWord(AstNode* lsbp, int wordAdder) {
 	// Return equation to get the VL_BITWORD of a constant or non-constant
 	if (lsbp->castConst()) {
@@ -355,7 +354,7 @@ private:
 	    AstNode* lowwordp = new AstWordSel (nodep->fromp()->fileline(),
 						nodep->fromp()->cloneTree(true),
 						newSelBitWord(nodep->lsbp(), 0));
-	    if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep); 
+	    if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep);
 	    AstNode* lowp = new AstShiftR (nodep->fileline(),
 					   lowwordp,
 					   newSelBitBit(nodep->lsbp()),
@@ -368,7 +367,7 @@ private:
 		    new AstWordSel (nodep->fromp()->fileline(),
 				    nodep->fromp()->cloneTree(true),
 				    newSelBitWord(nodep->lsbp(), 1));
-		if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep); 
+		if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep);
 		// If we're selecting bit zero, then all 32 bits in word 1 get shifted << by 32 bits
 		// else we need to form the lower word, so we << by 31 or less
 		// nbitsfromlow <= (lsb==0) ? 64-bitbit(lsb) : 32-bitbit(lsb)
@@ -406,7 +405,7 @@ private:
 		    new AstWordSel (nodep->fromp()->fileline(),
 				    nodep->fromp()->cloneTree(true),
 				    newSelBitWord(nodep->lsbp(), 2));
-		if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep); 
+		if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep);
 		AstNode* himayp =
 		    new AstShiftL (nodep->fileline(),
 				   hiwordp,
@@ -434,7 +433,7 @@ private:
 	    UINFO(8,"    SEL->SHIFT "<<nodep<<endl);
 	    AstNode* fromp = nodep->fromp()->unlinkFrBack();
 	    AstNode* lsbp = nodep->lsbp()->unlinkFrBack();
-	    if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep); 
+	    if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep);
 	    AstNode* newp = new AstShiftR (nodep->fileline(),
 					   fromp,
 					   dropCondBound(lsbp),
@@ -504,7 +503,7 @@ private:
 	bool destwide = lhsp->fromp()->isWide();
 	bool ones = nodep->rhsp()->isAllOnesV();
 	if (lhsp->lsbp()->castConst()) {
-	    // The code should work without this constant test, but it won't 
+	    // The code should work without this constant test, but it won't
 	    // constify as nicely as we'd like.
 	    AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
 	    AstNode* destp = lhsp->fromp()->unlinkFrBack();
@@ -592,7 +591,7 @@ private:
 		//   For wide destp, we can either form a equation for every destination word,
 		// with the appropriate long equation of if it's being written or not.
 		//   Or, we can use a LHS variable arraysel with non-constant index to set the vector.
-		// Doing the variable arraysel is better for globals and large arrays, 
+		// Doing the variable arraysel is better for globals and large arrays,
 		// doing every word is better for temporaries and if we're setting most words
 		// since it may result in better substitution optimizations later.
 		//   This results in so much code, we're better off leaving a function call.
@@ -630,7 +629,7 @@ private:
 		//newp->dumpTree(cout,"-  new: ");
 		insertBefore(nodep,newp);
 		return true;
-	    }		
+	    }
 	}
     }
 
@@ -641,10 +640,10 @@ private:
 	} else {
 	    UINFO(8,"    CONCAT "<<nodep<<endl);
 	    AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
-	    AstNode* rhsp = nodep->rhsp()->unlinkFrBack();	
+	    AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
 	    int rhsshift = rhsp->widthMin();
-	    if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); 
-	    if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep); 
+	    if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
+	    if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep);
 	    AstNode* newp = new AstOr (nodep->fileline(),
 				       new AstShiftL (nodep->fileline(),
 						      lhsp,
@@ -657,7 +656,7 @@ private:
     }
     bool expandWide (AstNodeAssign* nodep, AstConcat* rhsp) {
 	UINFO(8,"    Wordize ASSIGN(CONCAT) "<<nodep<<endl);
-	// Lhs or Rhs may be word, long, or quad. 
+	// Lhs or Rhs may be word, long, or quad.
 	// newAstWordSelClone nicely abstracts the difference.
 	int rhsshift = rhsp->rhsp()->widthMin();
 	// Sometimes doing the words backwards is preferrable.
@@ -670,7 +669,7 @@ private:
 						      rhsp->lhsp(), rhsshift),
 				     newAstWordSelClone (rhsp->rhsp(), w)));
 	}
- 	return true;
+	return true;
     }
 
     virtual void visit(AstReplicate* nodep, AstNUser*) {
@@ -690,7 +689,7 @@ private:
 		AstConst* constp = nodep->rhsp()->castConst();
 		if (!constp) nodep->v3fatalSrc("Replication value isn't a constant.  Checked earlier!");
 		uint32_t times = constp->asInt();
-		if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep); 
+		if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
 		newp = lhsp->cloneTree(true);
 		for (unsigned repnum=1; repnum<times; repnum++) {
 		    int rhsshift = repnum*lhswidth;
@@ -731,7 +730,7 @@ private:
 	    }
 	    addWordAssign(nodep, w, newp);
 	}
- 	return true;
+	return true;
     }
 
     virtual void visit(AstChangeXor* nodep, AstNUser*) {

src/V3Expand.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Expansion of wide operator macros to C operators
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3File.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3File.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: File stream wrapper that understands indentation
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Gate.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Gate optimizations, such as wire elimination
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -19,7 +18,7 @@
 //
 //*************************************************************************
 // V3Gate's Transformations:
-//		
+//
 // Extract a graph of the *entire* netlist with cells expanded
 // Perform constant optimization across the graph
 // Create VARSCOPEs for any variables we can rip out
@@ -170,7 +169,7 @@ private:
 	// V3Const cleans up any NOTs by flipping the edges for us
 	if (m_buffersOnly
 	    && !(nodep->rhsp()->castVarRef()
-		 // Until NEW_ORDERING, avoid making non-clocked logic into clocked, 
+		 // Until NEW_ORDERING, avoid making non-clocked logic into clocked,
 		 // as it slows down the verilator_sim_benchmark
 		 || (nodep->rhsp()->castNot()
 		     && nodep->rhsp()->castNot()->lhsp()->castVarRef()
@@ -343,7 +342,7 @@ private:
 	    UINFO(5," VARREF to "<<varscp<<endl);
 	    // We use weight of one; if we ref the var more than once, when we simplify,
 	    // the weight will increase
-	    if (nodep->lvalue()) {	
+	    if (nodep->lvalue()) {
 		new V3GraphEdge(&m_graph, m_logicVertexp, varvertexp, 1);
 	    } else {
 		new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, 1);
@@ -490,7 +489,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
 			if (debug()>=5) substp->dumpTree(cout,"\t  subst:  ");
 			m_statSigs++;
 			while (V3GraphEdge* edgep = vvertexp->outBeginp()) {
- 			    GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
+			    GateLogicVertex* consumeVertexp = dynamic_cast<GateLogicVertex*>(edgep->top());
 			    AstNode* consumerp = consumeVertexp->nodep();
 			    optimizeElimVar(vvertexp->varScp(), substp, consumerp);
 			    // If the new replacement referred to a signal,

src/V3Gate.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Break always into sensitivity block domains
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3GenClk.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Generated Clock repairs
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -21,7 +20,7 @@
 // GENCLK TRANSFORMATIONS:
 //	Follow control-flow graph with assignments and var usages
 //	    ASSIGNDLY to variable later used as clock requires change detect
-//	    
+//
 //*************************************************************************
 
 #include "config_build.h"
@@ -93,7 +92,7 @@ private:
     }
     //----
     virtual void visit(AstVarRef* nodep, AstNUser*) {
-	// Consumption/generation of a variable, 
+	// Consumption/generation of a variable,
 	AstVarScope* vscp = nodep->varScopep();
 	if (!vscp) nodep->v3fatalSrc("Scope not assigned");
 	if (m_activep && !nodep->user3()) {
@@ -172,7 +171,7 @@ private:
     //----
 
     virtual void visit(AstVarRef* nodep, AstNUser*) {
-	// Consumption/generation of a variable, 
+	// Consumption/generation of a variable,
 	AstVarScope* vscp = nodep->varScopep();
 	if (!vscp) nodep->v3fatalSrc("Scope not assigned");
 	if (m_activep) {

src/V3GenClk.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+//-*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Generated Clock Repairs
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Global.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Common headers
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3Graph.cpp

@@ -1,8 +1,8 @@
-// $Id$
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -106,7 +106,7 @@ ostream& operator<<(ostream& os, V3GraphVertex* vertexp) {
 //######################################################################
 // Edges
 
-V3GraphEdge::V3GraphEdge(V3Graph* graphp, 
+V3GraphEdge::V3GraphEdge(V3Graph* graphp,
 			 V3GraphVertex* fromp, V3GraphVertex* top, int weight,
 			 bool cutable) {
     UASSERT(fromp, "Null from pointer\n");

src/V3Graph.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+//-*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -67,7 +67,7 @@ public:
     virtual ~V3Graph();
     static void debug(int level) { s_debug = level; }
     virtual string dotRankDir() { return "TB"; }	// rankdir for dot plotting
-    
+
     // METHODS
     void clear();	// Empty it of all vertices/edges, as if making a new object
 

src/V3GraphAcyc.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph acyclic algorithm
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3GraphAlg.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -345,7 +344,7 @@ private:
 	if (m_done) return;
 
 	m_callTrace.reserve(currentRank+10);   // Leave slop for speed
-	m_callTrace[currentRank++] = vertexp; 
+	m_callTrace[currentRank++] = vertexp;
 
 	if (vertexp->user() == 1) {
 	    for (unsigned i=0; i<currentRank; i++) {

src/V3GraphAlg.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph algorithm base class
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //

src/V3GraphDfa.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph optimizations
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -224,7 +223,7 @@ private:
 	    }
 	}
     }
-	
+
     void main() {
 	UINFO(5,"Dfa to Nfa conversion...\n");
 	// Vertex::color() begin: 1 indicates vertex on DFA graph, 0=NFA graph
@@ -236,7 +235,7 @@ private:
 
 	// Find NFA start
 	DfaVertex* nfaStartp = graphp()->findStart();
-	    
+
 	// Create new DFA State (start state) from the NFA states
 	DfaVertex* dfaStartp = newDfaVertex(nfaStartp);
 
@@ -267,7 +266,7 @@ private:
 	    }
 	}
 	if (debug()>=6) m_graphp->dumpDotFilePrefixed("dfa_start");
-	insertDfaOrigins(dfaStartp); 
+	insertDfaOrigins(dfaStartp);
 
 	int i=0;
 	UINFO(5,"Main state conversion...\n");
@@ -293,7 +292,7 @@ private:
 		    }
 		}
 	    }
-	    
+
 	    // Foreach input state (NFA inputs of this DFA state)
 	    for (set<DfaInput>::const_iterator inIt=inputs.begin(); inIt!=inputs.end(); ++inIt) {
 		DfaInput input = *inIt;
@@ -303,7 +302,7 @@ private:
 		// Find all states reachable for given input
 		DfaStates nfasWithInput;
 		findNfasWithInput(dfaStatep, input, nfasWithInput/*ref*/);
-		
+
 		// nfasWithInput now maps to the DFA we want a transition to.
 		// Does a DFA already exist with this, and only this subset of NFA's?
 		DfaVertex* toDfaStatep = findDfaOrigins(nfasWithInput);
@@ -317,7 +316,7 @@ private:
 			new DfaEdge (graphp(), toDfaStatep, *nfaIt, DfaEdge::NA());
 			if ((*nfaIt)->accepting()) toDfaStatep->accepting(true);
 		    }
-		    insertDfaOrigins(toDfaStatep); 
+		    insertDfaOrigins(toDfaStatep);
 		}
 		// Add input transition
 		new DfaEdge (graphp(), dfaStatep, toDfaStatep, input);
@@ -375,7 +374,7 @@ private:
     }
 
     void optimize_accepting_out() {
-	// Delete outbound edges from accepting states 
+	// Delete outbound edges from accepting states
 	// (As once we've accepted, we no longer care about anything else.)
 	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
@@ -496,7 +495,7 @@ void DfaGraph::dfaReduce() {
 // 2. All vertexes except start/accept get edges to NEW accept for any
 // non-existing case.  Weedely we don't have a nice way of representing
 // this so we just create a edge for each case and mark it "complemented."
-// 
+//
 // 3. Delete temp vertex (old accept/new reject) and related edges.
 // The user's old accept is now the new accept.  This is imporant as
 // we want the virtual type of it to be intact.
@@ -513,7 +512,7 @@ private:
     void add_complement_edges() {
 	// Find accepting vertex
 	DfaVertex* acceptp = NULL;
- 	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
+	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	    if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
 		if (vvertexp->accepting()) {
 		    acceptp = vvertexp;
@@ -521,7 +520,7 @@ private:
 		}
 	    }
 	}
- 	if (!acceptp) v3fatalSrc("No accepting vertex in DFA\n");
+	if (!acceptp) v3fatalSrc("No accepting vertex in DFA\n");
 
 	// Remap edges
 	for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {

src/V3GraphDfa.h

@@ -1,8 +1,8 @@
-// $Id$ //-*- C++ -*-
+// -*- C++ -*-
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph automata base class
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -46,7 +46,7 @@ class DfaEdge;
 /// at the end of the transformations.  (If we want the complement, we
 /// call complement and the algorithm makes a REJECT state, then flips
 /// accept and reject for you.)
-///	
+///
 /// Common transforms:
 ///
 ///	"*":	DfaVertex(START) --> [epsilon] -->DfaVertex(ACCEPT)
@@ -87,7 +87,7 @@ public:
 // Vertex
 
 class DfaVertex : public V3GraphVertex {
-    // Each DFA state is captured in this vertex.  
+    // Each DFA state is captured in this vertex.
     // Start and accepting are members, rather than the more intuitive
     // subclasses, as subclassing them would make it harder to inherit from here.
     bool	m_start;	// Start state
@@ -98,7 +98,7 @@ public:
 	: V3GraphVertex(graphp)
 	, m_start(start), m_accepting(accepting) {}
     virtual DfaVertex* clone(DfaGraph* graphp) {
-    	return new DfaVertex(graphp, start(), accepting()); }
+	return new DfaVertex(graphp, start(), accepting()); }
     virtual ~DfaVertex() {}
     // ACCESSORS
     virtual string dotShape() const { return (accepting()?"doublecircle":""); }

src/V3GraphTest.cpp

@@ -1,8 +1,7 @@
-// $Id$
 //*************************************************************************
 // DESCRIPTION: Verilator: Graph tests
 //
-// Code available from: http://www.veripool.com/verilator
+// Code available from: http://www.veripool.org/verilator
 //
 // AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
 //
@@ -112,7 +111,7 @@ public:
 	new V3GraphEdge(gp, g1, q, 2, true);
 	new V3GraphEdge(gp, g2, q, 2, true);
 	new V3GraphEdge(gp, g3, q, 2, true);
-	
+
 	gp->stronglyConnected(&V3GraphEdge::followAlwaysTrue);
 	dump();
 
@@ -143,7 +142,7 @@ public:
 	new V3GraphEdge(gp, g1, a, 2, true);
 	new V3GraphEdge(gp, g2, a, 2, true);
 	new V3GraphEdge(gp, g3, a, 2, true);
-	
+
 	gp->acyclic(&V3GraphEdge::followAlwaysTrue);
 	gp->order();
 	dump();
@@ -157,7 +156,7 @@ public:
 	V3Graph* gp = &m_graph;
 
 	V3GraphTestVertex* clk	= new V3GraphTestVarVertex(gp,"$clk");
-	
+
 	V3GraphTestVertex* a	= new V3GraphTestVarVertex(gp,"$a");
 	V3GraphTestVertex* a_dly	= new V3GraphTestVarVertex(gp,"$a_dly");
 	V3GraphTestVertex* a_dlyblk= new V3GraphTestVarVertex(gp,"$a_dlyblk");
@@ -166,13 +165,13 @@ public:
 	V3GraphTestVertex* b_dlyblk= new V3GraphTestVarVertex(gp,"$b_dlyblk");
 	V3GraphTestVertex* c	= new V3GraphTestVarVertex(gp,"$c");
 	V3GraphTestVertex* i	= new V3GraphTestVarVertex(gp,"$i");
-	
+
 	V3GraphTestVertex* ap	= new V3GraphTestVarVertex(gp,"$a_pre");
 	V3GraphTestVertex* bp	= new V3GraphTestVarVertex(gp,"$b_pre");
 	V3GraphTestVertex* cp	= new V3GraphTestVarVertex(gp,"$c_pre");
-	
+
 	V3GraphTestVertex* n;
-	
+
 	// Logical order between clk, and posedge blocks
 	//   implemented by special CLK prod/cons?
 	// Required order between first x_DLY<=x_pre and final x<=x_DLY
@@ -183,23 +182,23 @@ public:
 	//   implemented by producer/consumer on a_dly signals
 	// Desired order between different _DLY blocks so we can elim temporaries
 	//   implemented by cutable "pre" signal dependencies
-	
-	
+
+
 	n = new V3GraphTestVertex(gp,"*INPUTS*"); {
 	    new V3GraphEdge(gp, n, clk, 2);
 	    new V3GraphEdge(gp, n, i, 2);
 	}
-	
+
 	V3GraphTestVertex* posedge = n = new V3GraphTestVertex(gp,"*posedge clk*"); {
 	    new V3GraphEdge(gp, clk, n, 2);
 	}
-	
+
 	// AssignPre's     VarRefs on LHS:  generate special BLK
 	//    normal:      VarRefs on LHS:  generate normal
 	//    underSBlock: VarRefs on RHS:  consume 'pre' (required to save cutable tests)
 	n = new V3GraphTestVertex(gp,"a_dly<PRE=a"); {
 	    new V3GraphEdge(gp, n, a_dlyblk, 2);  // Block ordering
-	    new V3GraphEdge(gp, n, a_dly, 2); 
+	    new V3GraphEdge(gp, n, a_dly, 2);
 	    new V3GraphEdge(gp, ap, n, 2, true);   // DESIRED delayed ordering (inp is required)
 	    new V3GraphEdge(gp, posedge, n, 2);
 	}
@@ -209,7 +208,7 @@ public:
 	    new V3GraphEdge(gp, bp, n, 2, true);   // DESIRED delayed ordering
 	    new V3GraphEdge(gp, posedge, n, 2);
 	}
-	
+
 	// AssignDly's     VarRefs on LHS:  consume special BLK
 	//    normal:      VarRefs on LHS:  generate normal
 	//    underSBlock: VarRefs on RHS:  generate 'pre' signals (cutable)
@@ -228,7 +227,7 @@ public:
 	    new V3GraphEdge(gp, n, ap, 2);   // DESIRED delayed usage
 	    new V3GraphEdge(gp, posedge, n, 2);
 	}
-	
+
 	// AssignPost's
 	//    normal:      VarRefs on LHS:  generate normal
 	//    underSBlock: VarRefs on RHS:  consume normal
@@ -242,11 +241,11 @@ public:
 	    new V3GraphEdge(gp, b_dly, n, 3);
 	    new V3GraphEdge(gp, posedge, n, 2);
 	}
-	
+
 	// COMBO
 	// Inbound edges are always uncutable, because we must put combo logic after sequential
 	// Outbound are cutable, as we may need to evaluate multiple times
-	
+
 	{
 	    V3GraphTestVertex* n	= new V3GraphTestVertex(gp,"c=a|b|i");
 	    new V3GraphEdge(gp, n, c, 1, true);
@@ -254,7 +253,7 @@ public:
 	    new V3GraphEdge(gp, b, n, 1, false);
 	    new V3GraphEdge(gp, i, n, 1, false);
 	}
-	
+
 	gp->acyclic(&V3GraphEdge::followAlwaysTrue);
 	gp->order();
 
@@ -288,7 +287,7 @@ public:
 	DfaTestVertex*  sr  = new DfaTestVertex(gp,"sR");
 	DfaTestVertex*  sz  = new DfaTestVertex(gp,"sZ");
 	DfaTestVertex*  sac = new DfaTestVertex(gp,"*ACCEPT*");  sac->accepting(true);
-	
+
 	AstNUser* L = AstNUser::fromInt(0xaa);
 	AstNUser* R = AstNUser::fromInt(0xbb);
 	AstNUser* Z = AstNUser::fromInt(0xcc);
@@ -340,7 +339,7 @@ public:
 
 #if 0
 # include "graph_export.cpp"
-#else 
+#else
 void V3GraphTestImport::dotImport() {
 }
 #endif