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8367 Commits

Author SHA1 Message Date
Artur Bieniek 53c59e7ac7
Fix referencing module variables above classes (#6304) 
Signed-off-by: Artur Bieniek <abieniek@internships.antmicro.com>
 2025-08-18 08:51:25 -04:00
Geza Lore 9dc31e4556
Fix unsound assertion in V3Delayed (#6305) 2025-08-18 13:46:35 +01:00
Geza Lore c172cc2ab0
Internals: Simplify port connect after instance dearray (#6302) 
Pre pull for #6298
 2025-08-18 09:55:54 +01:00
Wilson Snyder 25d71a43a5 For hier-generated Verilog, use always_comb 2025-08-17 20:14:19 -04:00
Wilson Snyder 88046c8063 Internals: Rename AstSenTree pointers to sentreep. No functional change intended except JSON. 2025-08-17 19:14:34 -04:00
Wilson Snyder dbdf235115 Commentary: Changes update 2025-08-17 14:53:59 -04:00
Wilson Snyder eaecdf7477 Tests: Improve check for member brace initialization. 2025-08-17 14:40:10 -04:00
Geza Lore f6edf26eb2
Fix hierarchical NBAs (#6286) (#6300) 
NBAs targeting a variable in a different scope are now allocated
temporary variables for captured values in the scope of the NBA, not the
scope of the target variable.

Fixes #6286
 2025-08-17 19:35:40 +01:00
Wilson Snyder b14539569f Internals: Check and enforce member brace initialization. No functional change intended 2025-08-17 13:20:52 -04:00
Wilson Snyder 7126293086 Support enum.next with a parameter 2025-08-16 21:06:35 -04:00
Wilson Snyder 36c4a24661 Internals: constifyParamsEdit return value was unused. No functional change. 2025-08-16 21:03:12 -04:00
Wilson Snyder 49ca1cfdd7 Commentary 2025-08-16 18:32:40 -04:00
Wilson Snyder 48a12fb0f4 Document and test `+verilator+rand+reset+2` usage (#6285 partial) 2025-08-16 11:47:19 -04:00
Wilson Snyder 340d1aff4a Tests: Cleanup to favor '--binary'. No test change intended. 2025-08-16 09:26:42 -04:00
Wilson Snyder 000d697b51 Commentary: Changes update 2025-08-16 09:08:09 -04:00
Geza Lore a300bfc538
Internals: Add AstNodeStmt.h (#6295) 
Move AstNodeStmt and all its subtypes into AstNodeStmt.h.

This is the first step for #6280.

No functional change
 2025-08-16 09:46:18 +01:00
Geza Lore 6f69c990fd
Internals: Remove AstCondBound and AstNodeCond (#6293) (#6294) 
Fixes #6293
 2025-08-15 15:49:06 -07:00
Geza Lore d273e2cbd0 Internals: Do not astgen useless Dfg vertex subtypes 2025-08-15 20:06:58 +01:00
Sergey Fedorov ece4469869
Fix PowerPC support (#6292) 2025-08-15 11:25:32 -07:00
Geza Lore 9c11f5e05d Fix DFG circular driver tracing 2025-08-15 10:20:20 +01:00
Mateusz Gancarz e753480b19
Fix no matching function calls for randomized `VlWide` in unpacked and dynamic arrays (#6290) 2025-08-14 05:19:33 -07:00
Wilson Snyder 047a12cc62 Fix variables hiding package imports (#6289). 2025-08-13 18:05:37 -04:00
Wilson Snyder 75c6745868 Test driver.py: Pass-through +verilator+ arguments to runtime 2025-08-12 19:32:56 -04:00
Wilson Snyder 60cbbf0ec1 Add error on mismatching prototypes (#6207). 2025-08-11 19:50:47 -04:00
Geza Lore 762c5f573c Improve DFG to enable breaking more combinational cycles 2025-08-11 09:44:31 +01:00
Geza Lore 7696b0651c Internals: Improve DFG dumping functions 2025-08-10 16:48:40 +01:00
Wilson Snyder e6e52dd60a Tests: Fix t_constraint_nosolver_bad.py (#6273) 2025-08-10 08:43:04 -04:00
Wilson Snyder eb80db9397 Clarify extern error message 2025-08-10 08:38:26 -04:00
Wilson Snyder 641dd756c0 Add check for mis-assignment of dynamic/automatics per IEEE 2025-08-10 07:23:28 -04:00
Wilson Snyder a74a3bb689 Internals: No need for 'if' before VL_FFLUSH_I 2025-08-10 06:13:18 -04:00
Geza Lore d28436dccc
Fix stray ']' in Verilog code output for non-constant select (#6277) 2025-08-09 14:59:58 +01:00
Wilson Snyder 3ca1c9b6dd Internals: Fix and enforce brace new constructors. No functional change intended. 2025-08-08 18:21:12 -04:00
Wilson Snyder 1eccfa64b5 Commentary 2025-08-08 17:54:48 -04:00
Wilson Snyder 1d05028087 Add compiler warning disable '-Wno-int-in-bool-context' 2025-08-08 17:54:48 -04:00
Geza Lore 16d32cdd4a
Internals: Refactor Ast to Dfg conversion for reusability. (#6276) 
This is mainly code motion, with minimal algorithmic changes to
facilitate reusing parts in future code. No functional change intended.
 2025-08-08 22:53:12 +01:00
Wilson Snyder d1f851e1e1 Internals: Optimize empty 'if' into StmtExpr 2025-08-08 05:10:40 -04:00
Wilson Snyder 6a225d5d00 Internals: Remove AstSysFuncAsTask 2025-08-08 05:09:54 -04:00
Wilson Snyder b12b1c9658 Commentary: Changes update 2025-08-08 05:09:16 -04:00
Geza Lore dbb8cbece2 CI: Improve RTLMeter failure issue body (#6275) 2025-08-08 09:13:29 +01:00
Geza Lore 9ddbf5f4b8 CI: Only raise RTLMeter failure issue on failure 2025-08-08 08:07:55 +01:00
Geza Lore b2388faa5e
CI: Add running RTLMeter workflow on selective PRs (#6271) 
Runs RTLMeter on PRs if the PR has the 'pr: rtlmeter' label applied to
it. This should make it easy to selectively require the RTLMeter
workflows to pass on a PR that is potentially invasive, per our own
judgement.
 2025-08-07 19:30:43 +01:00
Geza Lore 188a12f609
CI: Add raising GitHub issue on failure of scheduled RTLMeter job (#6270) 2025-08-07 18:17:00 +01:00
Todd Strader 6bd6663dc9
Fix spurious VPI value change callbacks (#6274) 2025-08-07 16:37:33 +01:00
Artur Bieniek 5b7188fcaf
Fix same variable on the RHS forced to two different LHSs. (#6269) 2025-08-06 17:37:00 -04:00
github action dc049fdd74 Apply 'make format' 2025-08-06 21:30:37 +00:00
Michael Bedford Taylor 218659f4e8
Support parameter resolution of 1D unpacked array slices (#6257) (#6268) 2025-08-06 17:29:40 -04:00
Igor Zaworski 6c1cfc68cf
Fix dynamic cast purity (#6267) 
Signed-off-by: Igor Zaworski <izaworski@internships.antmicro.com>
 2025-08-06 07:09:44 -04:00
Wilson Snyder fbaff52668 Change runtime to exit() instead of abort(), unless under +verilated+debug. 2025-08-05 18:43:29 -04:00
Wilson Snyder 06c570e159 Commentary 2025-08-05 17:56:12 -04:00
Wilson Snyder c005486acf Support by ignoring delay2 on UDPs 2025-08-05 17:34:42 -04:00