Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.

docs/gen/ex_ASSIGNEQEXPR_faulty.rst

@@ -1,9 +1,8 @@
 .. comment: generated by t_lint_assigneqexpr_bad
 .. code-block:: sv
    :linenos:
-   :emphasize-lines: 3
 
-     assign d_o =  // Note = not == below
+       output logic c_o,
-         (
+       output logic d_o
-         c_o = 1  // <--- Warning: ASSIGNEQEXPR
+   );
-         ) ? 1 : (
+     assign c_o = (a_i != 0) ? 1 : 0;

docs/gen/ex_FUNCTIMECTL_faulty.rst

@@ -4,4 +4,4 @@
    :emphasize-lines: 2
 
      function void calls_timing_ctl;
-       @e; // <--- Bad IEEE 1800-2023 13.4 time-controlling
+       @e;  // <--- Bad IEEE 1800-2023 13.4 time-controlling

examples/json_py/sub.v

@@ -5,12 +5,12 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub #(
-  #(parameter type TYPE_t = logic)
+    parameter type TYPE_t = logic
-  (
+) (
-   input  TYPE_t in,
+    input TYPE_t in,
-   output TYPE_t out
+    output TYPE_t out
-   );
+);
 
   // Some simple logic
   always_comb out = ~in;

examples/json_py/top.v

@@ -5,29 +5,37 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module top
+module top (
-  (
+    input clk,
-   input              clk,
+    input fastclk,
-   input              fastclk,
+    input reset_l,
-   input              reset_l,
 
-   output wire [1:0]  out_small,
+    output wire [1:0] out_small,
-   output wire [39:0] out_quad,
+    output wire [39:0] out_quad,
-   output wire [69:0] out_wide,
+    output wire [69:0] out_wide,
-   input [1:0]        in_small,
+    input [1:0] in_small,
-   input [39:0]       in_quad,
+    input [39:0] in_quad,
-   input [69:0]       in_wide
+    input [69:0] in_wide
-   );
+);
 
-   sub #(.TYPE_t(logic [1:0])) sub_small
+  sub #(
-     (.in(in_small),
+      .TYPE_t(logic [1:0])
-      .out(out_small));
+  ) sub_small (
+      .in(in_small),
+      .out(out_small)
+  );
 
-   sub #(.TYPE_t(logic [39:0])) sub_quad
+  sub #(
-     (.in(in_quad),
+      .TYPE_t(logic [39:0])
-      .out(out_quad));
+  ) sub_quad (
+      .in(in_quad),
+      .out(out_quad)
+  );
 
-   sub #(.TYPE_t(logic [69:0])) sub_wide
+  sub #(
-     (.in(in_wide),
+      .TYPE_t(logic [69:0])
-      .out(out_wide));
+  ) sub_wide (
+      .in(in_wide),
+      .out(out_wide)
+  );
 endmodule

examples/make_protect_lib/secret_impl.v

@@ -7,13 +7,13 @@
 // This module will be used as libsecret.a or libsecret.so without
 // exposing the source.
 
-module secret_impl
+module secret_impl (
-  (
+    input [31:0] a,
-   input [31:0]      a,
+    input [31:0] b,
-   input [31:0]      b,
+    output logic [31:0] x,
-   output logic [31:0] x,
+    input clk,
-   input          clk,
+    input reset_l
-   input          reset_l);
+);
 
   logic [31:0] accum_q;
   logic [31:0] secret_value;
@@ -27,10 +27,8 @@ module secret_impl
     end
     else begin
       accum_q <= accum_q + a;
-      if (accum_q > 10)
+      if (accum_q > 10) x <= b;
-        x <= b;
+      else x <= a + b + secret_value;
-      else
-        x <= a + b + secret_value;
     end
   end
 

examples/make_protect_lib/top.v

@@ -6,7 +6,9 @@
 
 // See also https://verilator.org/guide/latest/examples.html"
 
-module top (input clk);
+module top (
+    input clk
+);
 
   int cyc;
   logic reset_l;
@@ -14,7 +16,13 @@ module top (input clk);
   logic [31:0] b;
   logic [31:0] x;
 
-  verilated_secret secret (.a, .b, .x, .clk, .reset_l);
+  verilated_secret secret (
+      .a,
+      .b,
+      .x,
+      .clk,
+      .reset_l
+  );
 
   always @(posedge clk) begin
     $display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);

examples/make_tracing_c/sub.v

@@ -5,11 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub (
-  (
+    input clk,
-   input clk,
+    input reset_l
-   input reset_l
+);
-   );
 
   // Example counter/flop
   reg [31:0] count_c;

examples/make_tracing_c/top.v

@@ -8,24 +8,23 @@
 // This is intended to be a complex example of several features, please also
 // see the simpler examples/make_hello_c.
 
-module top
+module top (
-  (
+    // Declare some signals so we can see how I/O works
-   // Declare some signals so we can see how I/O works
+    input clk,
-   input          clk,
+    input reset_l,
-   input          reset_l,
 
-   output wire [1:0]  out_small,
+    output wire [1:0] out_small,
-   output wire [39:0] out_quad,
+    output wire [39:0] out_quad,
-   output wire [69:0] out_wide,
+    output wire [69:0] out_wide,
-   input [1:0]      in_small,
+    input [1:0] in_small,
-   input [39:0]     in_quad,
+    input [39:0] in_quad,
-   input [69:0]     in_wide
+    input [69:0] in_wide
-   );
+);
 
   // Connect up the outputs, using some trivial logic
   assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
-  assign out_quad  = ~reset_l ? '0 : (in_quad + 40'b1);
+  assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
-  assign out_wide  = ~reset_l ? '0 : (in_wide + 70'b1);
+  assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
 
   // And an example sub module. The submodule will print stuff.
   sub sub (/*AUTOINST*/

examples/make_tracing_sc/sub.v

@@ -5,12 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub (
-  (
+    input clk,
-   input clk,
+    input fastclk,
-   input fastclk,
+    input reset_l
-   input reset_l
+);
-   );
 
   // Example counter/flop
   reg [31:0] count_f;

examples/make_tracing_sc/top.v

@@ -8,25 +8,24 @@
 // This is intended to be a complex example of several features, please also
 // see the simpler examples/make_hello_c.
 
-module top
+module top (
-  (
+    // Declare some signals so we can see how I/O works
-   // Declare some signals so we can see how I/O works
+    input clk,
-   input              clk,
+    input fastclk,
-   input              fastclk,
+    input reset_l,
-   input              reset_l,
 
-   output wire [1:0]  out_small,
+    output wire [1:0] out_small,
-   output wire [39:0] out_quad,
+    output wire [39:0] out_quad,
-   output wire [69:0] out_wide,
+    output wire [69:0] out_wide,
-   input [1:0]        in_small,
+    input [1:0] in_small,
-   input [39:0]       in_quad,
+    input [39:0] in_quad,
-   input [69:0]       in_wide
+    input [69:0] in_wide
-   );
+);
 
   // Connect up the outputs, using some trivial logic
   assign out_small = ~reset_l ? '0 : (in_small + 2'b1);
-  assign out_quad  = ~reset_l ? '0 : (in_quad + 40'b1);
+  assign out_quad = ~reset_l ? '0 : (in_quad + 40'b1);
-  assign out_wide  = ~reset_l ? '0 : (in_wide + 70'b1);
+  assign out_wide = ~reset_l ? '0 : (in_wide + 70'b1);
 
   // And an example sub module. The submodule will print stuff.
   sub sub (/*AUTOINST*/

test_regress/t/t_alias_force.v

@@ -22,11 +22,13 @@ module t (  /*AUTOARG*/
       force a = 16'h1234;
       if (a != 16'h1234 || a != b) $stop;
       release a;
-    end else if (cyc == 2) begin
+    end
+    else if (cyc == 2) begin
       force b = 16'h5678;
       if (a != 16'h5678 || a != b) $stop;
       release b;
-    end else if (cyc == 3) begin
+    end
+    else if (cyc == 3) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end

test_regress/t/t_alias_hier_ref_bad.v

@@ -12,7 +12,7 @@ module t (  /*AUTOARG*/
 );
   input clk;
 
-  reg  [15:0] out;
+  reg [15:0] out;
   wire [15:0] a;
 
   alias a = sub_i.btw;
@@ -29,7 +29,7 @@ module sub (
     output wire [15:0] out
 );
 
-  reg  [31:0] counter = 32'h0;
+  reg [31:0] counter = 32'h0;
   wire [15:0] btw;
 
   assign btw = {counter[15:0]};

test_regress/t/t_alw_reorder_inlined_func.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+// verilog_format: on
 
 module t;
 
@@ -18,15 +20,16 @@ module t;
   // Constant 1 set in initial block, but not known at compile time
   logic enable = 1'b0;
 
-  int array [32];
+  int array[32];
 
   function automatic int get(logic en, logic [4:0] idx);
-    if (en) begin // Always taken, but need the 'if' to show bug
+    if (en) begin  // Always taken, but need the 'if' to show bug
       int tmp;
       idx = ~idx;
       tmp = array[~idx];
       return tmp;
-    end else begin
+    end
+    else begin
       return 0;
     end
   endfunction

test_regress/t/t_alw_sen_compare.v

@@ -5,13 +5,16 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module top;
-   sub inst(
+  sub inst (
       .a({128{1'b1}}),
       .b({128{1'b1}})
   );
 endmodule
 
-module sub(a, b);
+module sub (
+    a,
+    b
+);
   input [127:0] a;
   input [127:0] b;
   always @(a or b) begin

test_regress/t/t_array_index_side.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
 
 class Cls;
    int m_index;

test_regress/t/t_array_method_map.out

@@ -1,11 +1,11 @@
-%Error-UNSUPPORTED: t/t_array_method_map.v:17:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
+%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
                                                 : ... note: In instance 't'
-   17 |       res = a.map(el) with (el == 200);
+   19 |       res = a.map(el) with (el == 200);
       |               ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: t/t_array_method_map.v:17:15: Unknown built-in array method 'map'
+%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map'
                                     : ... note: In instance 't'
-   17 |       res = a.map(el) with (el == 200);
+   19 |       res = a.map(el) with (el == 200);
       |               ^~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_array_method_map.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 

test_regress/t/t_assert_elab_p.v

@@ -25,7 +25,8 @@ module t #(
       .ID_T(ID_T),
       .STAGE_IDS(STAGE_IDS)
   ) pipe (
-      .*);
+      .*
+  );
 
   initial $finish;
 

test_regress/t/t_assert_future.v

@@ -10,11 +10,8 @@
 // verilog_format: on
 
 module t (
-    /*AUTOARG*/
+    input clk
-  // Inputs
+);
-  clk
-  );
-  input clk;
 
   global clocking @(posedge clk);
   endclocking

test_regress/t/t_assert_future_bad.out

@@ -1,22 +1,22 @@
-%Error: t/t_assert_future_bad.v:18:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:16:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   18 |   else $display("Future=%0d", $future_gclk(a));
+   16 |   else $display("Future=%0d", $future_gclk(a));
       |                               ^~~~~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_assert_future_bad.v:21:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:19:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   21 |   else $display("Future=%0d", $rising_gclk(a));
+   19 |   else $display("Future=%0d", $rising_gclk(a));
       |                               ^~~~~~~~~~~~
-%Error: t/t_assert_future_bad.v:24:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:22:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   24 |   else $display("Future=%0d", $falling_gclk(a));
+   22 |   else $display("Future=%0d", $falling_gclk(a));
       |                               ^~~~~~~~~~~~~
-%Error: t/t_assert_future_bad.v:27:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:25:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   27 |   else $display("Future=%0d", $steady_gclk(a));
+   25 |   else $display("Future=%0d", $steady_gclk(a));
       |                               ^~~~~~~~~~~~
-%Error: t/t_assert_future_bad.v:30:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:28:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   30 |   else $display("Future=%0d", $changing_gclk(a));
+   28 |   else $display("Future=%0d", $changing_gclk(a));
       |                               ^~~~~~~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_assert_future_bad.v

@@ -4,12 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (  /*AUTOARG*/
+module t (
-  // Inputs
+    input a,
-  a, clk
+    input clk
-  );
+);
-  input a;
-  input clk;
 
   global clocking @(posedge clk);
   endclocking

test_regress/t/t_assert_future_unsup.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_assert_future_unsup.v:21:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func'
+%Error-UNSUPPORTED: t/t_assert_future_unsup.v:19:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func'
                                                    : ... note: In instance 't'
-   21 |   assert property (@(posedge clk) $future_gclk(a) == func(a));
+   19 |   assert property (@(posedge clk) $future_gclk(a) == func(a));
       |                                                      ^~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_assert_future_unsup.v

@@ -4,12 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (  /*AUTOARG*/
+module t (
-  // Inputs
+    input a,
-  a, clk
+    input clk
-  );
+);
-  input a;
-  input clk;
 
   function logic func(input logic i);
     return i;

test_regress/t/t_assert_implication_coverage.v

@@ -4,13 +4,12 @@
 // without warranty, 2025 by Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-  // Inputs
+    input clk
-  clk
 );
 
-  input clk;
+  integer cyc;
-  integer cyc; initial cyc=1;
+  initial cyc = 1;
 
   Test test (
     /*AUTOINST*/
@@ -19,13 +18,13 @@ module t (/*AUTOARG*/
     .cyc(cyc)
   );
 
-  always @ (posedge clk) begin
+  always @(posedge clk) begin
-    if (cyc!=0) begin
+    if (cyc != 0) begin
       cyc <= cyc + 1;
 `ifdef TEST_VERBOSE
       $display("cyc=%0d", cyc);
 `endif
-      if (cyc==10) begin
+      if (cyc == 10) begin
         $write("*-* All Finished *-*\n");
         $finish;
       end
@@ -35,7 +34,9 @@ module t (/*AUTOARG*/
 endmodule
 
 // Interface for data validation with coverage
-interface data_valid_if (input logic clk);
+interface data_valid_if (
+    input logic clk
+);
   logic enable_invalid_data_checks;
   logic valid;
   logic [7:0] data;
@@ -49,16 +50,15 @@ interface data_valid_if (input logic clk);
 
 endinterface
 
-module Test
+module Test (
-  (
+    input clk,
-   input clk,
+    input integer cyc
-   input integer cyc
+);
-   );
 
   logic rst_n;
 
   // Instantiate the interface
-  data_valid_if dv_if(clk);
+  data_valid_if dv_if (clk);
 
   // Reset logic
   initial begin

test_regress/t/t_assert_pre.v

@@ -4,15 +4,14 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkh(gotv,
+`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
-               expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
 
-module t (  /*AUTOARG*/
+module t (
-    // Inputs
+    input clk
-    clk
 );
-  input clk;
 
   bit toggle = 0;
   int inc = 0;
@@ -49,7 +48,8 @@ module t (  /*AUTOARG*/
 `endif
     if (cyc % 3 == 0) begin
       toggle <= 1;
-    end else begin
+    end
+    else begin
       toggle <= 0;
     end
 

test_regress/t/t_assign_automatic_bad.out

@@ -1,34 +1,34 @@
-%Error: t/t_assign_automatic_bad.v:35:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5'
+%Error: t/t_assign_automatic_bad.v:36:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5'
                                         : ... note: In instance 't'
-   35 |   assign bad_dyn5[0] = empty_dyn;   
+   36 |   assign bad_dyn5[0] = empty_dyn;   
       |          ^~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_assign_automatic_bad.v:37:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1'
+%Error: t/t_assign_automatic_bad.v:38:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1'
                                         : ... note: In instance 't'
-   37 |   assign c.m_bad1 = 2;   
+   38 |   assign c.m_bad1 = 2;   
       |            ^~~~~~
-%Error: t/t_assign_automatic_bad.v:47:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6'
+%Error: t/t_assign_automatic_bad.v:48:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6'
                                        : ... note: In instance 't'
-   47 |     bad_dyn6[0] <= 2;   
+   48 |     bad_dyn6[0] <= 2;   
       |     ^~~~~~~~
-%Error: t/t_assign_automatic_bad.v:49:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue'
+%Error: t/t_assign_automatic_bad.v:50:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue'
                                        : ... note: In instance 't'
-   49 |     bad_queue[0] <= 2;  
+   50 |     bad_queue[0] <= 2;   
       |     ^~~~~~~~~
-%Error: t/t_assign_automatic_bad.v:51:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc'
+%Error: t/t_assign_automatic_bad.v:52:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc'
                                        : ... note: In instance 't'
-   51 |     bad_assoc[0] <= 2;  
+   52 |     bad_assoc[0] <= 2;   
       |     ^~~~~~~~~
-%Error: t/t_assign_automatic_bad.v:54:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2'
+%Error: t/t_assign_automatic_bad.v:55:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2'
                                        : ... note: In instance 't'
-   54 |     c.m_bad2 <= 2;   
+   55 |     c.m_bad2 <= 2;   
       |       ^~~~~~
-%Error: t/t_assign_automatic_bad.v:56:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
+%Error: t/t_assign_automatic_bad.v:57:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
                                         : ... note: In instance 't'
-   56 |     Cls::s_dyn[0] <= 2;   
+   57 |     Cls::s_dyn[0] <= 2;   
       |          ^~~~~
-%Error: t/t_assign_automatic_bad.v:58:26: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
+%Error: t/t_assign_automatic_bad.v:63:7: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
-                                        : ... note: In instance 't'
+                                       : ... note: In instance 't'
-   58 |     clist[bad_dyn6[0]++].s_dyn[0] <= '1;  
+   63 |     ].s_dyn[0] <= '1;   
-      |                          ^~~~~
+      |       ^~~~~
 %Error: Exiting due to

test_regress/t/t_assign_automatic_bad.v

@@ -18,8 +18,9 @@ class Cls;
   int m_bad2;
 endclass
 
-module t(clk);
+module t (
-  input clk;
+    input clk
+);
 
   Cls c;
 
@@ -46,16 +47,20 @@ module t(clk);
   always @(posedge clk) begin
     bad_dyn6[0] <= 2;  // <--- Error: nonblocking dynarray element
     bad_dyn6 <= empty_dyn;  // <--- OK: nonblocking dynarray assignment, not to its element
-    bad_queue[0] <= 2; // Error: nonblocking queue element assignment
+    bad_queue[0] <= 2;  // Error: nonblocking queue element assignment
-    bad_queue <= empty_queue; // OK: nonblocking assignment to queue itself, not to its element
+    bad_queue <= empty_queue;  // OK: nonblocking assignment to queue itself, not to its element
-    bad_assoc[0] <= 2; // Error: nonblocking associative array element assignment
+    bad_assoc[0] <= 2;  // Error: nonblocking associative array element assignment
     bad_assoc <= empty_assoc; // OK: nonblocking assignment to associative array itself, not to its element
     Cls::s_ok2 <= 2;  // OK: nonblocking class static
     c.m_bad2 <= 2;  // <--- Error: nonblocking class automatic
     Cls::s_dyn <= 2;  // OK: nonblocking class static dynarray assignment, not to its element
     Cls::s_dyn[0] <= 2;  // Error: nonblocking class static dynarray element
-    clist[bad_dyn6[0]++].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array
+    clist[
-    clist[bad_dyn6[0]++].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element
+    bad_dyn6[0]++
+    ].s_dyn <= '1;  // OK: direct nonblocking assignment to dynamically-sized array
+    clist[
+    bad_dyn6[0]++
+    ].s_dyn[0] <= '1;  // Error: nonblocking assigment to dynamically-sized array element
     mt(ok_7);
     $stop;
   end

test_regress/t/t_assigndly_deep_ref.v

@@ -38,8 +38,8 @@ class Bar;
 endclass
 
 module t;
-  Iface iface();
+  Iface iface ();
-  Iface iface2();
+  Iface iface2 ();
 
   task clockSome();
     #2;

test_regress/t/t_assigndly_deep_ref_array.v

@@ -5,13 +5,13 @@
 // SPDX-License-Identifier: CC0-1.0
 
 interface Iface;
-   bit clk;
+  bit clk;
-   int x[2:0];
+  int x[2:0];
 
-   clocking cb @(posedge clk);
+  clocking cb @(posedge clk);
-      default input #0 output #0;
+    default input #0 output #0;
-      inout x;
+    inout x;
-   endclocking
+  endclocking
 endinterface
 
 class Foo;
@@ -42,8 +42,8 @@ class Bar;
 endclass
 
 module t;
-  Iface iface();
+  Iface iface ();
-  Iface iface2();
+  Iface iface2 ();
 
   task clockSome();
     #2;

test_regress/t/t_assoc_enum.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 class X;
    typedef enum int {
@@ -31,14 +33,11 @@ class X;
 
 endclass
 
-module t;/*AUTOARG*/
+module t;
-
-
-initial begin
-   X x = new;
-   $finish;
-end
-
 
+  initial begin
+    X x = new;
+    $finish;
+  end
 
 endmodule

test_regress/t/t_assoc_method_map.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 
 module t;
 

test_regress/t/t_assoc_wildcard_map.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:17:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
+%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
                                                   : ... note: In instance 't'
-   17 |       res = a.map(el) with (el == 2);
+   19 |       res = a.map(el) with (el == 2);
       |               ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_assoc_wildcard_map.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2023 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 

test_regress/t/t_bitsel_concat.v

@@ -9,7 +9,10 @@
 // warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 // Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects
 

test_regress/t/t_bitsel_lvalue.v

@@ -4,17 +4,16 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t
+module t (
-  (
+    input wire [31:0] foo,
-   input  wire [ 31:0] foo,
+    output reg [144:0] bar,
-   output reg  [144:0] bar,
+    output reg [144:0] bar2,
-   output reg  [144:0] bar2,
+    output reg [144:0] bar3,
-   output reg  [144:0] bar3,
+    output reg [144:0] bar4
-   output reg  [144:0] bar4
+);
-   );
+  // verilator lint_off SELRANGE
-   // verilator lint_off SELRANGE
+  assign bar[159:128] = foo;
-   assign bar[159:128] = foo;
+  assign bar2[159] = foo[1];
-   assign bar2[159] = foo[1];
+  assign bar3[159-:32] = foo;
-   assign bar3[159 -: 32] = foo;
+  assign bar4[128+:32] = foo;
-   assign bar4[128 +: 32] = foo;
 endmodule

test_regress/t/t_c_width_bad.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_c_width_bad.v:9:22: Unsupported: $c can't generate wider than 64 bits
+%Error-UNSUPPORTED: t/t_c_width_bad.v:9:21: Unsupported: $c can't generate wider than 64 bits
                                           : ... note: In instance 't'
-    9 |    bit [99:0] wide = $c100("0");
+    9 |   bit [99:0] wide = $c100("0");
-      |                      ^~~~~
+      |                     ^~~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_c_width_bad.v

@@ -6,8 +6,8 @@
 
 module t;
 
-   bit [99:0] wide = $c100("0");
+  bit [99:0] wide = $c100("0");
 
-   initial $display("%d", wide);
+  initial $display("%d", wide);
 
 endmodule

test_regress/t/t_cast_stream.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 typedef enum {
    UVM_TLM_READ_COMMAND,

test_regress/t/t_class_defaultparam_import.v

@@ -5,8 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 
 package foo;
-   class bar#(type T=int);
+  class bar #(
-   endclass
+      type T = int
-endpackage;
+  );
+  endclass
+endpackage
+;
 
 import foo::bar;

test_regress/t/t_class_extern_typeref.v

@@ -4,7 +4,9 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-class uvm_process_guard#(type T=int);
+class uvm_process_guard #(
+    type T = int
+);
   T m_context;
   extern function T get_context();
   extern function new(T ctxt);

test_regress/t/t_class_hier_construction.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Petr Nohavica
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 interface class IBottomMid;
   pure virtual function void moo(int i);
@@ -48,7 +50,7 @@ class middle_class extends bottom_class implements IMid, IBottom;
   endfunction
 
   virtual function string bar();
-   return name;
+    return name;
   endfunction
 endclass
 
@@ -75,10 +77,10 @@ module t;
     top_class t = s;
     IMid im;
 
-    `checks( b.name, "middle ahoj 42" );
+    `checks(b.name, "middle ahoj 42");
-    `checks( s.name, "middle ahoj 42" );
+    `checks(s.name, "middle ahoj 42");
-    `checks( t.name, "middle ahoj 42" );
+    `checks(t.name, "middle ahoj 42");
-    `checkh( t.i, 42);
+    `checkh(t.i, 42);
     `checks(s.bar(), "middle ahoj 42");
     im = s;
     im.moo(42);

test_regress/t/t_class_modscope.v

@@ -4,10 +4,12 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
-module m();
+module m ();
   class c;
     static function void fstatic();
       `checkh(v, 42);
@@ -23,7 +25,7 @@ module m();
   int v;
 
   initial begin
-    v=42;
+    v = 42;
     `checkh(v, 42);
     c::fstatic();
     classinst = new();

test_regress/t/t_class_param_extends_static_member_function_access.v

@@ -4,16 +4,20 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-class Class1 #(type T);
+class Class1 #(
+    type T
+);
   static function int get_p();
     return 7;
   endfunction
 endclass
 
-class Class2 #(type T) extends Class1 #(T);
+class Class2 #(
-   static function int get_p2;
+    type T
-     return T::get_p();
+) extends Class1 #(T);
-   endfunction
+  static function int get_p2;
+    return T::get_p();
+  endfunction
 endclass
 
 module t;

test_regress/t/t_class_param_super.v

@@ -5,14 +5,14 @@
 // SPDX-License-Identifier: CC0-1.0
 
 class base #(
-   type T = int
+    type T = int
 );
-   function void fbase();
+  function void fbase();
-   endfunction
+  endfunction
 endclass
 
 class ext extends base;
-   function void fext();
+  function void fext();
-      super.fbase();
+    super.fbase();
-   endfunction
+  endfunction
 endclass

test_regress/t/t_class_param_typedef3.v

@@ -4,40 +4,44 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-class func_c #(parameter p_width=4);
+class func_c #(
-   static function logic[p_width-1:0] func(
+    parameter p_width = 4
-      input logic[p_width-1:0] inb
+);
-   );
+  static function logic [p_width-1:0] func(input logic [p_width-1:0] inb);
-      func = inb;
+    func = inb;
-   endfunction
+  endfunction
 endclass
 
-module modA #(parameter p_width = 7)(
+module modA #(
-   input logic [p_width-1:0] sig_a
+    parameter p_width = 7
-   ,output logic [p_width-1:0] sig_b
+) (
+    input logic [p_width-1:0] sig_a,
+    output logic [p_width-1:0] sig_b
 );
-   assign sig_b = func_c#(p_width)::func(sig_a);
+  assign sig_b = func_c#(p_width)::func(sig_a);
 endmodule
 
-module the_top();
+module the_top ();
-   localparam int Size = 3;
+  localparam int Size = 3;
 
-   logic [Size-1:0] sig_a;
+  logic [Size-1:0] sig_a;
-   logic [Size-1:0] sig_b;
+  logic [Size-1:0] sig_b;
 
-   modA #(.p_width(Size)) modA(
+  modA #(
-      .sig_a(sig_a)
+      .p_width(Size)
-      ,.sig_b(sig_b)
+  ) modA (
-   );
+      .sig_a(sig_a),
+      .sig_b(sig_b)
+  );
 
-   //assign sig_b = func_c#(p_width)::func(inb_i);
+  //assign sig_b = func_c#(p_width)::func(inb_i);
 
-   initial begin
+  initial begin
-      sig_a = 'h3;
+    sig_a = 'h3;
-      #1;
+    #1;
-      $display("sig_a=%d, sig_b=%d", sig_a, sig_b);
+    $display("sig_a=%d, sig_b=%d", sig_a, sig_b);
-      if(sig_b != 'h3) $stop;
+    if (sig_b != 'h3) $stop;
-      $write("*-* All Finished *-*\n");
+    $write("*-* All Finished *-*\n");
-      $finish;
+    $finish;
-   end
+  end
 endmodule

test_regress/t/t_class_param_typedef4.v

@@ -4,39 +4,43 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-class func_c #(parameter p_width=4);
+class func_c #(
-  static function logic[p_width-1:0] func(
+    parameter p_width = 4
-    input logic[p_width-1:0] inb
+);
-  );
+  static function logic [p_width-1:0] func(input logic [p_width-1:0] inb);
     func = inb;
   endfunction
 endclass
 
-module modA #(parameter p_width = 7)(
+module modA #(
-  input logic [p_width-1:0] sig_a
+    parameter p_width = 7
-  ,output logic [p_width-1:0] sig_b
+) (
+    input logic [p_width-1:0] sig_a,
+    output logic [p_width-1:0] sig_b
 );
   assign sig_b = func_c#(p_width)::func(sig_a);
 endmodule
 
-module the_top();
+module the_top ();
   localparam int Size = 3;
 
   logic [Size-1:0] sig_a;
   logic [Size-1:0] sig_b;
   logic [Size-1:0] sig_c;
 
-  modA #(.p_width(Size)) modA(
+  modA #(
-    .sig_a(sig_a)
+      .p_width(Size)
-    ,.sig_b(sig_b)
+  ) modA (
+      .sig_a(sig_a),
+      .sig_b(sig_b)
   );
 
   initial begin
     sig_a = 'h3;
     sig_c = func_c#(Size)::func('h5);
     #1;
-    if(sig_b != 'h3) $stop;
+    if (sig_b != 'h3) $stop;
-    if(sig_c != 'h5) $stop;
+    if (sig_c != 'h5) $stop;
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_class_param_typedef5.v

@@ -4,40 +4,42 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-class func_c #(parameter p_width=4);
+class func_c #(
-  typedef struct packed {
+    parameter p_width = 4
-    logic[p_width-1:0] data;
+);
-  } my_type_t;
+  typedef struct packed {logic [p_width-1:0] data;} my_type_t;
-  static function my_type_t func(
+  static function my_type_t func(input logic [p_width-1:0] inb);
-    input logic[p_width-1:0] inb
-  );
     func.data = inb;
   endfunction
 endclass
 
-module modA #(parameter p_width = 7)(
+module modA #(
-  input func_c#(p_width)::my_type_t sig_a,
+    parameter p_width = 7
-  output func_c#(p_width)::my_type_t sig_b
+) (
+    input func_c#(p_width)::my_type_t sig_a,
+    output func_c#(p_width)::my_type_t sig_b
 );
   assign sig_b.data = func_c#(p_width)::func(sig_a);
 endmodule
 
-module the_top();
+module the_top ();
   localparam int Size = 3;
 
-  func_c#(Size)::my_type_t sig_a, sig_b, sig_c;
+  func_c #(Size)::my_type_t sig_a, sig_b, sig_c;
 
-  modA #(.p_width(Size)) modA(
+  modA #(
-    .sig_a(sig_a),
+      .p_width(Size)
-    .sig_b(sig_b)
+  ) modA (
+      .sig_a(sig_a),
+      .sig_b(sig_b)
   );
 
   initial begin
     sig_a.data = 'h3;
     sig_c.data = func_c#(Size)::func('h5);
     #1;
-    if(sig_b.data != 'h3) $stop;
+    if (sig_b.data != 'h3) $stop;
-    if(sig_c.data != 'h5) $stop;
+    if (sig_c.data != 'h5) $stop;
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_class_param_typedef6.v

@@ -4,28 +4,22 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-
+// verilog_format: off
 `define stop $stop
-`define checkd(gotv,expv) \
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-  do if ((gotv) !== (expv)) begin \
+// verilog_format: on
-    $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", \
-            `__FILE__,`__LINE__, (gotv), (expv)); \
-    `stop; \
-  end while(0);
 
 class pipeline_class #(
-  parameter type XWORD = logic
+    parameter type XWORD = logic
 );
 
-  typedef struct packed {
+  typedef struct packed {XWORD pc;} if_id_t;
-    XWORD pc;
-  } if_id_t;
 
 endclass
 
 module pipe_reg #(
-  parameter type T = logic
+    parameter type T = logic
-)();
+) ();
   initial begin
     #1;
     `checkd($bits(T), 8);
@@ -35,9 +29,9 @@ endmodule
 module the_top #() ();
 
   typedef logic [7:0] my_t;
-  typedef pipeline_class #(my_t)::if_id_t if_id2_t;
+  typedef pipeline_class#(my_t)::if_id_t if_id2_t;
   typedef if_id2_t if_id_t;
-  pipe_reg #(if_id_t) if_id_reg();
+  pipe_reg #(if_id_t) if_id_reg ();
 
   initial begin
     #1;

test_regress/t/t_class_param_upcast.v

@@ -4,7 +4,9 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-class factory #(type T);
+class factory #(
+    type T
+);
   static function T create;
     T obj = new;
     return obj;
@@ -24,10 +26,9 @@ endclass
 module t;
   initial begin
     foo f;
-    if (bit'($random))
+    if (bit'($random)) f = bar::create;
-      f = bar::create;
+    else f = factory#(foo)::create();
-    else
-      f = factory#(foo)::create();
     $finish;
   end
-endmodule;
+endmodule
+;

test_regress/t/t_class_scope_import_bad.out

@@ -1,5 +1,5 @@
-%Error: t/t_class_scope_import_bad.v:11:11: Import statement directly within a class scope is illegal
+%Error: t/t_class_scope_import_bad.v:11:10: Import statement directly within a class scope is illegal
-   11 |    import pkg::*;
+   11 |   import pkg::*;
-      |           ^~~
+      |          ^~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_scope_import_bad.v

@@ -8,8 +8,8 @@ package pkg;
 endpackage
 
 class genericClass;
-   import pkg::*;
+  import pkg::*;
 endclass
 
-module tb_top();
+module tb_top ();
 endmodule

test_regress/t/t_class_super_new_noextend_bad.out

@@ -1,5 +1,5 @@
-%Error: t/t_class_super_new_noextend_bad.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15)
+%Error: t/t_class_super_new_noextend_bad.v:10:10: 'super' used on non-extended class (IEEE 1800-2023 8.15)
-   10 |       super.new();   
+   10 |     super.new();   
-      |            ^
+      |          ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_super_new_noextend_bad.v

@@ -6,7 +6,7 @@
 //
 
 class Cls;
-   function new();
+  function new();
-      super.new();  // Bad - no extends
+    super.new();  // Bad - no extends
-   endfunction
+  endfunction
 endclass

test_regress/t/t_class_to_basic_assignment_bad.out

@@ -1,5 +1,5 @@
-%Error: t/t_class_to_basic_assignment_bad.v:26:29: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
+%Error: t/t_class_to_basic_assignment_bad.v:26:27: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
-   26 |         new_node.phase_done = get();
+   26 |       new_node.phase_done = get();
-      |                             ^
+      |                           ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_class_to_basic_assignment_bad.v

@@ -12,21 +12,21 @@ class Foo;
     return ans;
   endfunction
 
-  static function int create ();
+  static function int create();
     return 3;
   endfunction
 
-  function string get_name ();
+  function string get_name();
     return "bar";
   endfunction
 
   function void add(Foo phase);
     Foo new_node;
     if (new_node.get_name() == "run") begin
-        new_node.phase_done = get();
+      new_node.phase_done = get();
     end
     else begin
-        new_node.phase_done = create();
+      new_node.phase_done = create();
     end
   endfunction
 endclass

test_regress/t/t_clocking_input_0_delay.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`timescale 1ms/1ns
+`timescale 1ms / 1ns
 module t;
   bit clk = 0;
   bit data = 1;
@@ -21,12 +21,11 @@ module t;
   end
 
   initial begin
-    #4
+    #4 if (data != 1) $stop;
-    if (data != 1) $stop;
     if (cb.data != 0) $stop;
     #1;
     #1step;
-    if(cb.data != 0) $stop;
+    if (cb.data != 0) $stop;
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_clocking_input_default.v

@@ -4,7 +4,7 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`timescale 1ms/1ns
+`timescale 1ms / 1ns
 module t;
   bit clk = 0;
   bit data = 1;
@@ -21,12 +21,11 @@ module t;
   end
 
   initial begin
-    #4
+    #4 if (data != 1) $stop;
-    if(data != 1 ) $stop;
+    if (cb.data != 0) $stop;
-    if(cb.data != 0) $stop;
     #1;
     #1step;
-    if(cb.data != 1) $stop;
+    if (cb.data != 1) $stop;
     $write("*-* All Finished *-*\n");
     $finish;
   end

test_regress/t/t_config_work.v

@@ -6,7 +6,7 @@
 
 module t;
   // Test --work allows selecting two different libraries for these instances
-  m1 u_1();
+  m1 u_1 ();
-  m2 u_2();
+  m2 u_2 ();
   final $write("*-* All Finished *-*\n");
 endmodule

test_regress/t/t_config_work__liba.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module m1;
-  m3 u_13();
+  m3 u_13 ();
   initial $display("liba:m1 %%m=%m %%l=%l");
 endmodule
 

test_regress/t/t_config_work__libb.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module m2;
-  m3 u_23();
+  m3 u_23 ();
   initial $display("libb:m2 %%m=%m %%l=%l");
 endmodule
 

test_regress/t/t_constraint_global_arr_unsup.v

@@ -73,11 +73,13 @@ module t_constraint_global_arr_unsup;
           o.m_mid_arr[1].m_arr[2].m_y == 400) begin
         $display("*-* All Finished *-*");
         $finish;
-      end else begin
+      end
+      else begin
         $display("*-* FAILED *-*");
         $stop;
       end
-    end else begin
+    end
+    else begin
       $display("*-* FAILED: randomize() returned 0 *-*");
       $stop;
     end

test_regress/t/t_constraint_global_randMode.v

@@ -6,9 +6,7 @@
 
 class RandomValue;
   rand int value;
-  constraint small_int_c {
+  constraint small_int_c {value < 10;}
-    value < 10;
-  }
   task disable_val();
     value.rand_mode(0);
   endtask

test_regress/t/t_cover_sys_line_expr.out

@@ -5,12 +5,9 @@
         // any use, without warranty, 2024 by Wilson Snyder.
         // SPDX-License-Identifier: CC0-1.0
         
-        module t (/*AUTOARG*/
+        module t (
-          // Inputs
+            input clk
-          clk
+        );
-          );
-        
-          input clk;
         
           int cyc, bump, result;
           logic foo;
@@ -326,7 +323,7 @@
 -000000  point: comment=else hier=top.t
  000010     cyc <= cyc + 1;
 +000010  point: comment=block hier=top.t
-%000009     if (cyc==9) begin
+%000009     if (cyc == 9) begin
 -000001  point: comment=if hier=top.t
 -000009  point: comment=else hier=top.t
 %000001       $write("*-* All Finished *-*\n");
@@ -334,6 +331,6 @@
 %000001       $finish;
 -000001  point: comment=if hier=top.t
             end
-           end
+          end
         endmodule
         

test_regress/t/t_cover_sys_line_expr.v

@@ -4,12 +4,9 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-  // Inputs
+    input clk
-  clk
+);
-  );
-
-  input clk;
 
   int cyc, bump, result;
   logic foo;
@@ -73,9 +70,9 @@ module t (/*AUTOARG*/
     if (($sformatf("abc") != "abc") && foo) bump <= bump + 1;
     if (foo && foo) bump <= bump + 1;
     cyc <= cyc + 1;
-    if (cyc==9) begin
+    if (cyc == 9) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end
-   end
+  end
 endmodule

test_regress/t/t_covergroup_in_class_duplicate_bad.out

@@ -1,8 +1,8 @@
-%Error: t/t_covergroup_in_class_duplicate_bad.v:13:16: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
+%Error: t/t_covergroup_in_class_duplicate_bad.v:13:14: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
-   13 |     covergroup embeddedCg;
+   13 |   covergroup embeddedCg;
-      |                ^~~~~~~~~~
+      |              ^~~~~~~~~~
-        t/t_covergroup_in_class_duplicate_bad.v:9:16: ... Location of original declaration
+        t/t_covergroup_in_class_duplicate_bad.v:9:14: ... Location of original declaration
-    9 |     covergroup embeddedCg;
+    9 |   covergroup embeddedCg;
-      |                ^~~~~~~~~~
+      |              ^~~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_covergroup_in_class_duplicate_bad.v

@@ -6,11 +6,11 @@
 
 /* verilator lint_off COVERIGN */
 class myClass;
-    covergroup embeddedCg;
+  covergroup embeddedCg;
 
-    endgroup
+  endgroup
 
-    covergroup embeddedCg;
+  covergroup embeddedCg;
 
-    endgroup
+  endgroup
 endclass

test_regress/t/t_define_override.v

@@ -10,11 +10,10 @@
 
 `define STRINGIFY(x) `"x`"
 
-module test (
+module test ();
-);
+  initial begin
-    initial begin
+    $display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO));
-        $display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO));
+    $finish;
-        $finish;
+  end
-    end
 
 endmodule

test_regress/t/t_delay_1step.v

@@ -5,13 +5,12 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-  timeunit 10s;
+  timeunit 10s; timeprecision 1s;
-  timeprecision 1s;
 
   initial begin
     #1;
     if ($time != 1) $stop;
-    repeat(10) #1step;
+    repeat (10) #1step;
     if ($time != 2) $stop;
     #10;
     $write("*-* All Finished *-*\n");

test_regress/t/t_dfg_bin_to_one_hot.v

@@ -4,14 +4,14 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0)
+`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+    input clk
-   clk
+);
-   );
-   input clk;
 
    reg [31:0] cyc = 0;
    reg [6:0] cntA = 0;

test_regress/t/t_dfg_circular_merged_scc.v

@@ -4,24 +4,28 @@
 // any use, without warranty, 2025 by Geza Lore.
 // SPDX-License-Identifier: CC0-1.0
 
-module mul (input [8:0] A, input [16:0] B, output [25:0] Y);
+module mul (
+    input [8:0] A,
+    input [16:0] B,
+    output [25:0] Y
+);
   assign Y = $signed(A) * $signed(B);
 endmodule
 
 module A;
   wire [26:0] C;
   wire [26:0] D;
-  wire [8:0]  E;
+  wire [8:0] E;
 
   // This yields a circular DFG with a fairly special form that used to trip
   // decomposition.
   mul mul (
-    .A(9'd10),
+      .A(9'd10),
-    .B(17'h0cccd),
+      .B(17'h0cccd),
-    .Y({ C[26], C[9:0], D[15:1] })
+      .Y({C[26], C[9:0], D[15:1]})
   );
 
-  assign E = { C[8:0] };
+  assign E = {C[8:0]};
   assign C[25:10] = {16{C[26]}};
 
 endmodule

test_regress/t/t_dfg_oob_sel_rvalue.v

@@ -5,16 +5,16 @@
 // SPDX-License-Identifier: CC0-1.0
 
 
-module t(
+module t (
-   input  logic [0:0][2:0] i,
+    input logic [0:0][2:0] i,
-   output logic            o
+    output logic o
 );
 
   always_comb begin
     o = 1'b0;
     // verilator unroll_full
-    for (int n = 0 ; n < 3; ++n) begin
+    for (int n = 0; n < 3; ++n) begin
-      o = o | i[n] == 3'd0; // Intentionally out of bounds
+      o = o | i[n] == 3'd0;  // Intentionally out of bounds
     end
   end
 

test_regress/t/t_dfg_regularize_clk.v

@@ -4,9 +4,10 @@
 // without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkd(gotv,
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-               expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module sub (
     input clk,

test_regress/t/t_dfg_result_var_ext_write.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module top;
 

test_regress/t/t_dfg_true_cycle_bad.out

@@ -4,6 +4,6 @@
                     ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
                     ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                     t/t_dfg_true_cycle_bad.v:10:23:      Example path: o
-                    t/t_dfg_true_cycle_bad.v:12:22:      Example path: ASSIGNW
+                    t/t_dfg_true_cycle_bad.v:12:20:      Example path: ASSIGNW
                     t/t_dfg_true_cycle_bad.v:10:23:      Example path: o
 %Error: Exiting due to

test_regress/t/t_dfg_true_cycle_bad.v

@@ -6,11 +6,11 @@
 
 `default_nettype none
 
-module t(
+module t (
     output wire [9:0] o
 );
-    assign o[1:0] = o[9:8];
+  assign o[1:0] = o[9:8];
-    assign o[3:2] = o[1:0];
+  assign o[3:2] = o[1:0];
-    assign o[7:4] = 4'(o[3:2]);
+  assign o[7:4] = 4'(o[3:2]);
-    assign o[9:8] = o[5:4];
+  assign o[9:8] = o[5:4];
 endmodule

test_regress/t/t_disable_bad.out

@@ -1,8 +1,8 @@
-%Error: t/t_disable_bad.v:9:15: Can't find definition of block/task: 'abcd'
+%Error: t/t_disable_bad.v:9:13: Can't find definition of block/task: 'abcd'
-    9 |       disable abcd;
+    9 |     disable abcd;
-      |               ^~~~
+      |             ^~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: Internal Error: t/t_disable_bad.v:9:7: ../V3LinkJump.cpp:#: Unlinked disable statement
+%Error: Internal Error: t/t_disable_bad.v:9:5: ../V3LinkJump.cpp:#: Unlinked disable statement
-    9 |       disable abcd;
+    9 |     disable abcd;
-      |       ^~~~~~~
+      |     ^~~~~~~
                         ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_disable_bad.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-   initial begin
+  initial begin
-      disable abcd;
+    disable abcd;
-   end
+  end
-endmodule: t
+endmodule : t

test_regress/t/t_disable_inside.v

@@ -10,7 +10,7 @@ module t;
     fork : fork_blk
       begin
         #1;
-        disable fork_blk; // Disables both forked processes
+        disable fork_blk;  // Disables both forked processes
         $stop;
       end
       begin
@@ -32,7 +32,7 @@ module t;
     fork
       begin : fork_branch
         #1;
-        disable fork_branch; // Disables only this branch of the fork
+        disable fork_branch;  // Disables only this branch of the fork
         $stop;
       end
       begin

test_regress/t/t_dpi_inline_new.v

@@ -9,8 +9,10 @@
 package pyhdl_if;
 
   typedef chandle PyObject;
-  import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(input PyObject p0,
+  import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(
-                                    input longint unsigned p1);
+    input PyObject p0,
+    input longint unsigned p1
+  );
 
   function PyObject PyTuple_GetItem(input PyObject p0, input longint unsigned p1);
     return _pyhdl_if_PyTuple_GetItem(p0, p1);
@@ -32,11 +34,9 @@ package pyhdl_if;
 
 endpackage
 
-module t (/*AUTOARG*/
+module t (
-  // Inputs
+    input clk
-  clk
+);
-  );
-  input clk;
 
   import pyhdl_if::*;
 

test_regress/t/t_event_control_expr_unsup.out

@@ -1,5 +1,5 @@
-%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:21: Unsupported: Impure function calls in sensitivity lists
+%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:20: Unsupported: Impure function calls in sensitivity lists
-   15 |    always @(posedge foo());
+   15 |   always @(posedge foo());
-      |                     ^~~
+      |                    ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_event_control_expr_unsup.v

@@ -5,13 +5,13 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-   int x;
+  int x;
 
-   function bit foo;
+  function bit foo;
-      x += 1;
+    x += 1;
-      return bit'(x % 2);
+    return bit'(x % 2);
-   endfunction
+  endfunction
 
-   always @(posedge foo());
+  always @(posedge foo());
 
 endmodule

test_regress/t/t_expr_shortcircuit.v

@@ -4,12 +4,9 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+    input clk
-   clk
+);
-   );
-
-  input clk;
 
   int cyc = 0;
 
@@ -20,8 +17,7 @@ module t (/*AUTOARG*/
   endfunction
 
   always_ff @(posedge clk) begin
-    if (cyc[0] == 1'b0 || is_odd(cyc))
+    if (cyc[0] == 1'b0 || is_odd(cyc)) cyc <= cyc + 1;
-      cyc <= cyc + 1;
     if (cyc == 10) begin
       $write("*-* All Finished *-*\n");
       $finish;

test_regress/t/t_flag_unroll_limit_const.out

@@ -1,9 +1,9 @@
-%Error: t/t_flag_unroll_limit_const.v:17:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f'
+%Error: t/t_flag_unroll_limit_const.v:17:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f'
                                            : ... note: In instance 't'
         t/t_flag_unroll_limit_const.v:9:3: ... Location of non-constant LOOP: Loop simulation took too long; probably this is an infinite loop, otherwise set '--unroll-limit' above 4
-        t/t_flag_unroll_limit_const.v:17:16: ... Called from 'f()' with parameters:
+        t/t_flag_unroll_limit_const.v:17:19: ... Called from 'f()' with parameters:
            x = ?32?h5
-   17 |   output logic[f(5):0] o5    
+   17 |     output logic [f(5):0] o5   
-      |                ^
+      |                   ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_flag_unroll_limit_const.v

@@ -12,9 +12,9 @@ function automatic int f(int x);
   return n;
 endfunction
 
-module t(
+module t (
-  output logic[f(4):0] o4,  // Should simulate
+    output logic [f(4):0] o4,  // Should simulate
-  output logic[f(5):0] o5   // Should NOT simulate
+    output logic [f(5):0] o5  // Should NOT simulate
 );
 
 endmodule

test_regress/t/t_force.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_chained.out

@@ -1,4 +1,4 @@
-%Error: t/t_force_chained.v:27:  got='h0 exp='h00000001
+%Error: t/t_force_chained.v:30:  got='h0 exp='h00000001
-%Error: t/t_force_chained.v:33:  got='h0 exp='h00000002
+%Error: t/t_force_chained.v:36:  got='h0 exp='h00000002
-%Error: t/t_force_chained.v:40:  got='h0 exp='h00000003
+%Error: t/t_force_chained.v:43:  got='h0 exp='h00000003
-%Error: t/t_force_chained.v:46:  got='h0 exp='h00000003
+%Error: t/t_force_chained.v:49:  got='h0 exp='h00000003

test_regress/t/t_force_chained.v

@@ -4,9 +4,12 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop  // TODO
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
-module t;
+  module t;
   reg [1:0] a;
   wire [1:0] b = 1;
   bit [1:0] c;

test_regress/t/t_force_complex_sel_unsup.out

@@ -1,10 +1,10 @@
-%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:37:22: Unsupported: Force / release statement with complex select expression
+%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:41:22: Unsupported: Force / release statement with complex select expression
                                                        : ... note: In instance 't'
-   37 |       force logic_arr[($c(1))] = 0;
+   41 |       force logic_arr[($c(1))] = 0;
       |                      ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:44:24: Unsupported: Force / release statement with complex select expression
+%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:51:24: Unsupported: Force / release statement with complex select expression
                                                        : ... note: In instance 't'
-   44 |       release logic_arr[($c(1))];
+   51 |       release logic_arr[($c(1))];
       |                        ^
 %Error: Exiting due to

test_regress/t/t_force_complex_sel_unsup.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 `ifdef VERILATOR
 // The '$c(1)' is there to prevent inlining of the signal by V3Gate
@@ -31,23 +33,31 @@ module t (  /*AUTOARG*/
     cyc <= cyc + 1;
     if (cyc == 0) begin
       logic_arr[`IMPURE_ONE] <= 1;
-    end else if (cyc == 1) begin
+    end
+    else if (cyc == 1) begin
       `checkh(logic_arr[`IMPURE_ONE], 1);
-    end else if (cyc == 2) begin
+    end
+    else if (cyc == 2) begin
       force logic_arr[`IMPURE_ONE] = 0;
-    end else if (cyc == 3) begin
+    end
+    else if (cyc == 3) begin
       `checkh(logic_arr[`IMPURE_ONE], 0);
       logic_arr[`IMPURE_ONE] <= 1;
-    end else if (cyc == 4) begin
+    end
+    else if (cyc == 4) begin
       `checkh(logic_arr[`IMPURE_ONE], 0);
-    end else if (cyc == 5) begin
+    end
+    else if (cyc == 5) begin
       release logic_arr[`IMPURE_ONE];
-    end else if (cyc == 6) begin
+    end
+    else if (cyc == 6) begin
       `checkh(logic_arr[`IMPURE_ONE], 0);
       logic_arr[`IMPURE_ONE] <= 1;
-    end else if (cyc == 7) begin
+    end
+    else if (cyc == 7) begin
       `checkh(logic_arr[`IMPURE_ONE], 1);
-    end else if (cyc == 8) begin
+    end
+    else if (cyc == 8) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end

test_regress/t/t_force_func.out

@@ -1,4 +1,4 @@
-%Error: t/t_force_func.v:26:  got='h0 exp='h00000001
+%Error: t/t_force_func.v:29:  got='h0 exp='h00000001
-%Error: t/t_force_func.v:34:  got='h0 exp='h00000002
+%Error: t/t_force_func.v:37:  got='h0 exp='h00000002
-%Error: t/t_force_func.v:39:  got='h0 exp='h00000003
+%Error: t/t_force_func.v:42:  got='h0 exp='h00000003
-%Error: t/t_force_func.v:43:  got='h0 exp='h00000003
+%Error: t/t_force_func.v:46:  got='h0 exp='h00000003

test_regress/t/t_force_func.v

@@ -4,9 +4,12 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop  // TODO
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
-function bit [1:0] get_arg (bit [1:0] x);
+  function bit [1:0] get_arg (bit [1:0] x);
    return x;
 endfunction
 

test_regress/t/t_force_immediate_release.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t;
 

test_regress/t/t_force_initial.v

@@ -4,9 +4,12 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
-module t;
+  module t;
   reg [1:0] a = 0;
   reg [1:0] b = 2;
 

test_regress/t/t_force_mid.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Outputs

test_regress/t/t_force_multi.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_port_inline.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module sub(
    input wire [7:0] i,

test_regress/t/t_force_readwrite.v

@@ -13,7 +13,7 @@ module t;
   logic a;
   logic b = 1;
   logic c;
-  Cls   cls = new;
+  Cls cls = new;
 
   initial begin
     force a = b;

test_regress/t/t_force_readwrite_unsup.v

@@ -18,7 +18,7 @@ endclass
 module t;
   logic a;
   logic b = 1;
-  Cls   cls = new;
+  Cls cls = new;
 
   initial begin
     force a = b;

test_regress/t/t_force_release.out

@@ -1,4 +1,4 @@
          0 d=0,e=0
         10 d=1,e=1
         20 d=1,e=0
-%Error: t/t_force_release.v:36:  got='h1 exp='h00000000
+%Error: t/t_force_release.v:39:  got='h1 exp='h00000000

test_regress/t/t_force_release.v

@@ -4,11 +4,14 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop  // TODO
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 // Example from IEEE 1800-2023 10.6.2
 
-module t;
+  module t;
   logic a, b, c, d;
   wire e;
   and and1 (e, a, b, c);