33 lines
654 B
Systemverilog
33 lines
654 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ms / 1ns
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module t;
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bit clk = 0;
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bit data = 1;
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bit cb_data;
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initial forever #5 clk = ~clk;
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assign cb_data = cb.data;
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clocking cb @(posedge clk);
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input #0 data;
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endclocking
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initial begin
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@(posedge clk) data = 0;
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end
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initial begin
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#4 if (data != 1) $stop;
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if (cb.data != 0) $stop;
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#1;
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#1step;
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if (cb.data != 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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