52 lines
1.1 KiB
Systemverilog
52 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2025 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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package pyhdl_if;
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typedef chandle PyObject;
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import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(
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input PyObject p0,
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input longint unsigned p1
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);
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function PyObject PyTuple_GetItem(input PyObject p0, input longint unsigned p1);
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return _pyhdl_if_PyTuple_GetItem(p0, p1);
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endfunction
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class py_object;
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function new(PyObject obj);
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endfunction
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endclass
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class py_tuple;
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function py_object get_item(int idx);
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py_object ret = new(PyTuple_GetItem(null, longint'(idx)));
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return ret;
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endfunction
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endclass
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endpackage
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module t (
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input clk
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);
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import pyhdl_if::*;
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initial begin
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py_tuple t0 = new;
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py_object o;
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o = t0.get_item(1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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