Tests: Reformat some recent tests to mostly verilog-format standard. No test functional change.

docs/gen/ex_ASSIGNEQEXPR_faulty.rst

@@ -1,9 +1,8 @@
 .. comment: generated by t_lint_assigneqexpr_bad
 .. code-block:: sv
    :linenos:
-   :emphasize-lines: 3
 
-     assign d_o =  // Note = not == below
+       output logic c_o,
-         (
+       output logic d_o
-         c_o = 1  // <--- Warning: ASSIGNEQEXPR
+   );
-         ) ? 1 : (
+     assign c_o = (a_i != 0) ? 1 : 0;

examples/json_py/sub.v

@@ -5,9 +5,9 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub #(
-  #(parameter type TYPE_t = logic)
+    parameter type TYPE_t = logic
-  (
+) (
     input TYPE_t in,
     output TYPE_t out
 );

examples/json_py/top.v

@@ -5,8 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module top
+module top (
-  (
     input clk,
     input fastclk,
     input reset_l,
@@ -19,15 +18,24 @@ module top
     input [69:0] in_wide
 );
 
-   sub #(.TYPE_t(logic [1:0])) sub_small
+  sub #(
-     (.in(in_small),
+      .TYPE_t(logic [1:0])
-      .out(out_small));
+  ) sub_small (
+      .in(in_small),
+      .out(out_small)
+  );
 
-   sub #(.TYPE_t(logic [39:0])) sub_quad
+  sub #(
-     (.in(in_quad),
+      .TYPE_t(logic [39:0])
-      .out(out_quad));
+  ) sub_quad (
+      .in(in_quad),
+      .out(out_quad)
+  );
 
-   sub #(.TYPE_t(logic [69:0])) sub_wide
+  sub #(
-     (.in(in_wide),
+      .TYPE_t(logic [69:0])
-      .out(out_wide));
+  ) sub_wide (
+      .in(in_wide),
+      .out(out_wide)
+  );
 endmodule

examples/make_protect_lib/secret_impl.v

@@ -7,13 +7,13 @@
 // This module will be used as libsecret.a or libsecret.so without
 // exposing the source.
 
-module secret_impl
+module secret_impl (
-  (
     input [31:0] a,
     input [31:0] b,
     output logic [31:0] x,
     input clk,
-   input          reset_l);
+    input reset_l
+);
 
   logic [31:0] accum_q;
   logic [31:0] secret_value;
@@ -27,10 +27,8 @@ module secret_impl
     end
     else begin
       accum_q <= accum_q + a;
-      if (accum_q > 10)
+      if (accum_q > 10) x <= b;
-        x <= b;
+      else x <= a + b + secret_value;
-      else
-        x <= a + b + secret_value;
     end
   end
 

examples/make_protect_lib/top.v

@@ -6,7 +6,9 @@
 
 // See also https://verilator.org/guide/latest/examples.html"
 
-module top (input clk);
+module top (
+    input clk
+);
 
   int cyc;
   logic reset_l;
@@ -14,7 +16,13 @@ module top (input clk);
   logic [31:0] b;
   logic [31:0] x;
 
-  verilated_secret secret (.a, .b, .x, .clk, .reset_l);
+  verilated_secret secret (
+      .a,
+      .b,
+      .x,
+      .clk,
+      .reset_l
+  );
 
   always @(posedge clk) begin
     $display("[%0t] cyc=%0d a=%0d b=%0d x=%0d", $time, cyc, a, b, x);

examples/make_tracing_c/sub.v

@@ -5,8 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub (
-  (
     input clk,
     input reset_l
 );

examples/make_tracing_c/top.v

@@ -8,8 +8,7 @@
 // This is intended to be a complex example of several features, please also
 // see the simpler examples/make_hello_c.
 
-module top
+module top (
-  (
     // Declare some signals so we can see how I/O works
     input clk,
     input reset_l,

examples/make_tracing_sc/sub.v

@@ -5,8 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 // ======================================================================
 
-module sub
+module sub (
-  (
     input clk,
     input fastclk,
     input reset_l

examples/make_tracing_sc/top.v

@@ -8,8 +8,7 @@
 // This is intended to be a complex example of several features, please also
 // see the simpler examples/make_hello_c.
 
-module top
+module top (
-  (
     // Declare some signals so we can see how I/O works
     input clk,
     input fastclk,

test_regress/t/t_alias_force.v

@@ -22,11 +22,13 @@ module t (  /*AUTOARG*/
       force a = 16'h1234;
       if (a != 16'h1234 || a != b) $stop;
       release a;
-    end else if (cyc == 2) begin
+    end
+    else if (cyc == 2) begin
       force b = 16'h5678;
       if (a != 16'h5678 || a != b) $stop;
       release b;
-    end else if (cyc == 3) begin
+    end
+    else if (cyc == 3) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end

test_regress/t/t_alw_reorder_inlined_func.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+// verilog_format: on
 
 module t;
 
@@ -26,7 +28,8 @@ module t;
       idx = ~idx;
       tmp = array[~idx];
       return tmp;
-    end else begin
+    end
+    else begin
       return 0;
     end
   endfunction

test_regress/t/t_alw_sen_compare.v

@@ -11,7 +11,10 @@ module top;
   );
 endmodule
 
-module sub(a, b);
+module sub (
+    a,
+    b
+);
   input [127:0] a;
   input [127:0] b;
   always @(a or b) begin

test_regress/t/t_array_index_side.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
 
 class Cls;
    int m_index;

test_regress/t/t_array_method_map.out

@@ -1,11 +1,11 @@
-%Error-UNSUPPORTED: t/t_array_method_map.v:17:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
+%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5)
                                                 : ... note: In instance 't'
-   17 |       res = a.map(el) with (el == 200);
+   19 |       res = a.map(el) with (el == 200);
       |               ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: t/t_array_method_map.v:17:15: Unknown built-in array method 'map'
+%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map'
                                     : ... note: In instance 't'
-   17 |       res = a.map(el) with (el == 200);
+   19 |       res = a.map(el) with (el == 200);
       |               ^~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_array_method_map.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 

test_regress/t/t_assert_elab_p.v

@@ -25,7 +25,8 @@ module t #(
       .ID_T(ID_T),
       .STAGE_IDS(STAGE_IDS)
   ) pipe (
-      .*);
+      .*
+  );
 
   initial $finish;
 

test_regress/t/t_assert_future.v

@@ -10,11 +10,8 @@
 // verilog_format: on
 
 module t (
-    /*AUTOARG*/
+    input clk
-  // Inputs
-  clk
 );
-  input clk;
 
   global clocking @(posedge clk);
   endclocking

test_regress/t/t_assert_future_bad.out

@@ -1,22 +1,22 @@
-%Error: t/t_assert_future_bad.v:18:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:16:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   18 |   else $display("Future=%0d", $future_gclk(a));
+   16 |   else $display("Future=%0d", $future_gclk(a));
       |                               ^~~~~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_assert_future_bad.v:21:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:19:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   21 |   else $display("Future=%0d", $rising_gclk(a));
+   19 |   else $display("Future=%0d", $rising_gclk(a));
       |                               ^~~~~~~~~~~~
-%Error: t/t_assert_future_bad.v:24:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:22:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   24 |   else $display("Future=%0d", $falling_gclk(a));
+   22 |   else $display("Future=%0d", $falling_gclk(a));
       |                               ^~~~~~~~~~~~~
-%Error: t/t_assert_future_bad.v:27:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:25:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   27 |   else $display("Future=%0d", $steady_gclk(a));
+   25 |   else $display("Future=%0d", $steady_gclk(a));
       |                               ^~~~~~~~~~~~
-%Error: t/t_assert_future_bad.v:30:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
+%Error: t/t_assert_future_bad.v:28:31: Future sampled value function called outside property or sequence expression (IEEE 16.9.4)
                                      : ... note: In instance 't'
-   30 |   else $display("Future=%0d", $changing_gclk(a));
+   28 |   else $display("Future=%0d", $changing_gclk(a));
       |                               ^~~~~~~~~~~~~~
 %Error: Exiting due to

test_regress/t/t_assert_future_bad.v

@@ -4,12 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (  /*AUTOARG*/
+module t (
-  // Inputs
+    input a,
-  a, clk
+    input clk
 );
-  input a;
-  input clk;
 
   global clocking @(posedge clk);
   endclocking

test_regress/t/t_assert_future_unsup.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_assert_future_unsup.v:21:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func'
+%Error-UNSUPPORTED: t/t_assert_future_unsup.v:19:54: Unsupported/illegal: Future value function used with expression with operator FUNCREF 'func'
                                                    : ... note: In instance 't'
-   21 |   assert property (@(posedge clk) $future_gclk(a) == func(a));
+   19 |   assert property (@(posedge clk) $future_gclk(a) == func(a));
       |                                                      ^~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_assert_future_unsup.v

@@ -4,12 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (  /*AUTOARG*/
+module t (
-  // Inputs
+    input a,
-  a, clk
+    input clk
 );
-  input a;
-  input clk;
 
   function logic func(input logic i);
     return i;

test_regress/t/t_assert_implication_coverage.v

@@ -4,13 +4,12 @@
 // without warranty, 2025 by Wilson Snyder
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-  // Inputs
+    input clk
-  clk
 );
 
-  input clk;
+  integer cyc;
-  integer cyc; initial cyc=1;
+  initial cyc = 1;
 
   Test test (
     /*AUTOINST*/
@@ -35,7 +34,9 @@ module t (/*AUTOARG*/
 endmodule
 
 // Interface for data validation with coverage
-interface data_valid_if (input logic clk);
+interface data_valid_if (
+    input logic clk
+);
   logic enable_invalid_data_checks;
   logic valid;
   logic [7:0] data;
@@ -49,8 +50,7 @@ interface data_valid_if (input logic clk);
 
 endinterface
 
-module Test
+module Test (
-  (
     input clk,
     input integer cyc
 );

test_regress/t/t_assert_pre.v

@@ -4,15 +4,14 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkh(gotv,
+`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
-               expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
 
-module t (  /*AUTOARG*/
+module t (
-    // Inputs
+    input clk
-    clk
 );
-  input clk;
 
   bit toggle = 0;
   int inc = 0;
@@ -49,7 +48,8 @@ module t (  /*AUTOARG*/
 `endif
     if (cyc % 3 == 0) begin
       toggle <= 1;
-    end else begin
+    end
+    else begin
       toggle <= 0;
     end
 

test_regress/t/t_assign_automatic_bad.out

@@ -1,34 +1,34 @@
-%Error: t/t_assign_automatic_bad.v:35:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5'
+%Error: t/t_assign_automatic_bad.v:36:10: Dynamically-sized variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'bad_dyn5'
                                         : ... note: In instance 't'
-   35 |   assign bad_dyn5[0] = empty_dyn;   
+   36 |   assign bad_dyn5[0] = empty_dyn;   
       |          ^~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_assign_automatic_bad.v:37:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1'
+%Error: t/t_assign_automatic_bad.v:38:12: Automatic lifetime variable not allowed in continuous assignment (IEEE 1800-2023 6.21): 'm_bad1'
                                         : ... note: In instance 't'
-   37 |   assign c.m_bad1 = 2;   
+   38 |   assign c.m_bad1 = 2;   
       |            ^~~~~~
-%Error: t/t_assign_automatic_bad.v:47:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6'
+%Error: t/t_assign_automatic_bad.v:48:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_dyn6'
                                        : ... note: In instance 't'
-   47 |     bad_dyn6[0] <= 2;   
+   48 |     bad_dyn6[0] <= 2;   
       |     ^~~~~~~~
-%Error: t/t_assign_automatic_bad.v:49:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue'
+%Error: t/t_assign_automatic_bad.v:50:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_queue'
                                        : ... note: In instance 't'
-   49 |     bad_queue[0] <= 2;  
+   50 |     bad_queue[0] <= 2;   
       |     ^~~~~~~~~
-%Error: t/t_assign_automatic_bad.v:51:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc'
+%Error: t/t_assign_automatic_bad.v:52:5: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'bad_assoc'
                                        : ... note: In instance 't'
-   51 |     bad_assoc[0] <= 2;  
+   52 |     bad_assoc[0] <= 2;   
       |     ^~~~~~~~~
-%Error: t/t_assign_automatic_bad.v:54:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2'
+%Error: t/t_assign_automatic_bad.v:55:7: Automatic lifetime variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 'm_bad2'
                                        : ... note: In instance 't'
-   54 |     c.m_bad2 <= 2;   
+   55 |     c.m_bad2 <= 2;   
       |       ^~~~~~
-%Error: t/t_assign_automatic_bad.v:56:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
+%Error: t/t_assign_automatic_bad.v:57:10: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
                                         : ... note: In instance 't'
-   56 |     Cls::s_dyn[0] <= 2;   
+   57 |     Cls::s_dyn[0] <= 2;   
       |          ^~~~~
-%Error: t/t_assign_automatic_bad.v:58:26: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
+%Error: t/t_assign_automatic_bad.v:63:7: Dynamically-sized variable not allowed in nonblocking assignment (IEEE 1800-2023 6.21): 's_dyn'
                                        : ... note: In instance 't'
-   58 |     clist[bad_dyn6[0]++].s_dyn[0] <= '1;  
+   63 |     ].s_dyn[0] <= '1;   
       |       ^~~~~
 %Error: Exiting due to

test_regress/t/t_assign_automatic_bad.v

@@ -18,8 +18,9 @@ class Cls;
   int m_bad2;
 endclass
 
-module t(clk);
+module t (
-  input clk;
+    input clk
+);
 
   Cls c;
 
@@ -54,8 +55,12 @@ module t(clk);
     c.m_bad2 <= 2;  // <--- Error: nonblocking class automatic
     Cls::s_dyn <= 2;  // OK: nonblocking class static dynarray assignment, not to its element
     Cls::s_dyn[0] <= 2;  // Error: nonblocking class static dynarray element
-    clist[bad_dyn6[0]++].s_dyn <= '1; // OK: direct nonblocking assignment to dynamically-sized array
+    clist[
-    clist[bad_dyn6[0]++].s_dyn[0] <= '1; // Error: nonblocking assigment to dynamically-sized array element
+    bad_dyn6[0]++
+    ].s_dyn <= '1;  // OK: direct nonblocking assignment to dynamically-sized array
+    clist[
+    bad_dyn6[0]++
+    ].s_dyn[0] <= '1;  // Error: nonblocking assigment to dynamically-sized array element
     mt(ok_7);
     $stop;
   end

test_regress/t/t_assoc_enum.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 class X;
    typedef enum int {
@@ -31,14 +33,11 @@ class X;
 
 endclass
 
-module t;/*AUTOARG*/
+module t;
-
 
   initial begin
     X x = new;
     $finish;
   end
 
-
-
 endmodule

test_regress/t/t_assoc_method_map.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 
 module t;
 

test_regress/t/t_assoc_wildcard_map.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:17:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
+%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5)
                                                   : ... note: In instance 't'
-   17 |       res = a.map(el) with (el == 2);
+   19 |       res = a.map(el) with (el == 2);
       |               ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_assoc_wildcard_map.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2023 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 

test_regress/t/t_bitsel_concat.v

@@ -9,7 +9,10 @@
 // warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 // Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects
 

test_regress/t/t_bitsel_lvalue.v

@@ -4,8 +4,7 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t
+module t (
-  (
     input wire [31:0] foo,
     output reg [144:0] bar,
     output reg [144:0] bar2,

test_regress/t/t_c_width_bad.out

@@ -1,4 +1,4 @@
-%Error-UNSUPPORTED: t/t_c_width_bad.v:9:22: Unsupported: $c can't generate wider than 64 bits
+%Error-UNSUPPORTED: t/t_c_width_bad.v:9:21: Unsupported: $c can't generate wider than 64 bits
                                           : ... note: In instance 't'
     9 |   bit [99:0] wide = $c100("0");
       |                     ^~~~~

test_regress/t/t_cast_stream.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 typedef enum {
    UVM_TLM_READ_COMMAND,

test_regress/t/t_class_defaultparam_import.v

@@ -5,8 +5,11 @@
 // SPDX-License-Identifier: CC0-1.0
 
 package foo;
-   class bar#(type T=int);
+  class bar #(
+      type T = int
+  );
   endclass
-endpackage;
+endpackage
+;
 
 import foo::bar;

test_regress/t/t_class_extern_typeref.v

@@ -4,7 +4,9 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-class uvm_process_guard#(type T=int);
+class uvm_process_guard #(
+    type T = int
+);
   T m_context;
   extern function T get_context();
   extern function new(T ctxt);

test_regress/t/t_class_hier_construction.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Petr Nohavica
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 interface class IBottomMid;
   pure virtual function void moo(int i);

test_regress/t/t_class_modscope.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module m ();
   class c;

test_regress/t/t_class_param_extends_static_member_function_access.v

@@ -4,13 +4,17 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-class Class1 #(type T);
+class Class1 #(
+    type T
+);
   static function int get_p();
     return 7;
   endfunction
 endclass
 
-class Class2 #(type T) extends Class1 #(T);
+class Class2 #(
+    type T
+) extends Class1 #(T);
   static function int get_p2;
     return T::get_p();
   endfunction

test_regress/t/t_class_param_typedef3.v

@@ -4,17 +4,19 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-class func_c #(parameter p_width=4);
+class func_c #(
-   static function logic[p_width-1:0] func(
+    parameter p_width = 4
-      input logic[p_width-1:0] inb
 );
+  static function logic [p_width-1:0] func(input logic [p_width-1:0] inb);
     func = inb;
   endfunction
 endclass
 
-module modA #(parameter p_width = 7)(
+module modA #(
-   input logic [p_width-1:0] sig_a
+    parameter p_width = 7
-   ,output logic [p_width-1:0] sig_b
+) (
+    input logic [p_width-1:0] sig_a,
+    output logic [p_width-1:0] sig_b
 );
   assign sig_b = func_c#(p_width)::func(sig_a);
 endmodule
@@ -25,9 +27,11 @@ module the_top();
   logic [Size-1:0] sig_a;
   logic [Size-1:0] sig_b;
 
-   modA #(.p_width(Size)) modA(
+  modA #(
-      .sig_a(sig_a)
+      .p_width(Size)
-      ,.sig_b(sig_b)
+  ) modA (
+      .sig_a(sig_a),
+      .sig_b(sig_b)
   );
 
   //assign sig_b = func_c#(p_width)::func(inb_i);

test_regress/t/t_class_param_typedef4.v

@@ -4,17 +4,19 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-class func_c #(parameter p_width=4);
+class func_c #(
-  static function logic[p_width-1:0] func(
+    parameter p_width = 4
-    input logic[p_width-1:0] inb
 );
+  static function logic [p_width-1:0] func(input logic [p_width-1:0] inb);
     func = inb;
   endfunction
 endclass
 
-module modA #(parameter p_width = 7)(
+module modA #(
-  input logic [p_width-1:0] sig_a
+    parameter p_width = 7
-  ,output logic [p_width-1:0] sig_b
+) (
+    input logic [p_width-1:0] sig_a,
+    output logic [p_width-1:0] sig_b
 );
   assign sig_b = func_c#(p_width)::func(sig_a);
 endmodule
@@ -26,9 +28,11 @@ module the_top();
   logic [Size-1:0] sig_b;
   logic [Size-1:0] sig_c;
 
-  modA #(.p_width(Size)) modA(
+  modA #(
-    .sig_a(sig_a)
+      .p_width(Size)
-    ,.sig_b(sig_b)
+  ) modA (
+      .sig_a(sig_a),
+      .sig_b(sig_b)
   );
 
   initial begin

test_regress/t/t_class_param_typedef5.v

@@ -4,18 +4,18 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-class func_c #(parameter p_width=4);
+class func_c #(
-  typedef struct packed {
+    parameter p_width = 4
-    logic[p_width-1:0] data;
-  } my_type_t;
-  static function my_type_t func(
-    input logic[p_width-1:0] inb
 );
+  typedef struct packed {logic [p_width-1:0] data;} my_type_t;
+  static function my_type_t func(input logic [p_width-1:0] inb);
     func.data = inb;
   endfunction
 endclass
 
-module modA #(parameter p_width = 7)(
+module modA #(
+    parameter p_width = 7
+) (
     input func_c#(p_width)::my_type_t sig_a,
     output func_c#(p_width)::my_type_t sig_b
 );
@@ -27,7 +27,9 @@ module the_top();
 
   func_c #(Size)::my_type_t sig_a, sig_b, sig_c;
 
-  modA #(.p_width(Size)) modA(
+  modA #(
+      .p_width(Size)
+  ) modA (
       .sig_a(sig_a),
       .sig_b(sig_b)
   );

test_regress/t/t_class_param_typedef6.v

@@ -4,22 +4,16 @@
 // without warranty.
 // SPDX-License-Identifier: CC0-1.0
 
-
+// verilog_format: off
 `define stop $stop
-`define checkd(gotv,expv) \
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-  do if ((gotv) !== (expv)) begin \
+// verilog_format: on
-    $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", \
-            `__FILE__,`__LINE__, (gotv), (expv)); \
-    `stop; \
-  end while(0);
 
 class pipeline_class #(
     parameter type XWORD = logic
 );
 
-  typedef struct packed {
+  typedef struct packed {XWORD pc;} if_id_t;
-    XWORD pc;
-  } if_id_t;
 
 endclass
 

test_regress/t/t_class_param_upcast.v

@@ -4,7 +4,9 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-class factory #(type T);
+class factory #(
+    type T
+);
   static function T create;
     T obj = new;
     return obj;
@@ -24,10 +26,9 @@ endclass
 module t;
   initial begin
     foo f;
-    if (bit'($random))
+    if (bit'($random)) f = bar::create;
-      f = bar::create;
+    else f = factory#(foo)::create();
-    else
-      f = factory#(foo)::create();
     $finish;
   end
-endmodule;
+endmodule
+;

test_regress/t/t_class_scope_import_bad.out

@@ -1,4 +1,4 @@
-%Error: t/t_class_scope_import_bad.v:11:11: Import statement directly within a class scope is illegal
+%Error: t/t_class_scope_import_bad.v:11:10: Import statement directly within a class scope is illegal
    11 |   import pkg::*;
       |          ^~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

test_regress/t/t_class_super_new_noextend_bad.out

@@ -1,4 +1,4 @@
-%Error: t/t_class_super_new_noextend_bad.v:10:12: 'super' used on non-extended class (IEEE 1800-2023 8.15)
+%Error: t/t_class_super_new_noextend_bad.v:10:10: 'super' used on non-extended class (IEEE 1800-2023 8.15)
    10 |     super.new();   
       |          ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

test_regress/t/t_class_to_basic_assignment_bad.out

@@ -1,4 +1,4 @@
-%Error: t/t_class_to_basic_assignment_bad.v:26:29: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
+%Error: t/t_class_to_basic_assignment_bad.v:26:27: Assign RHS 'class{}Foo' cannot be assigned to non-class 'int'
    26 |       new_node.phase_done = get();
       |                           ^
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

test_regress/t/t_clocking_input_0_delay.v

@@ -21,8 +21,7 @@ module t;
   end
 
   initial begin
-    #4
+    #4 if (data != 1) $stop;
-    if (data != 1) $stop;
     if (cb.data != 0) $stop;
     #1;
     #1step;

test_regress/t/t_clocking_input_default.v

@@ -21,8 +21,7 @@ module t;
   end
 
   initial begin
-    #4
+    #4 if (data != 1) $stop;
-    if(data != 1 ) $stop;
     if (cb.data != 0) $stop;
     #1;
     #1step;

test_regress/t/t_constraint_global_arr_unsup.v

@@ -73,11 +73,13 @@ module t_constraint_global_arr_unsup;
           o.m_mid_arr[1].m_arr[2].m_y == 400) begin
         $display("*-* All Finished *-*");
         $finish;
-      end else begin
+      end
+      else begin
         $display("*-* FAILED *-*");
         $stop;
       end
-    end else begin
+    end
+    else begin
       $display("*-* FAILED: randomize() returned 0 *-*");
       $stop;
     end

test_regress/t/t_constraint_global_randMode.v

@@ -6,9 +6,7 @@
 
 class RandomValue;
   rand int value;
-  constraint small_int_c {
+  constraint small_int_c {value < 10;}
-    value < 10;
-  }
   task disable_val();
     value.rand_mode(0);
   endtask

test_regress/t/t_cover_sys_line_expr.out

@@ -5,13 +5,10 @@
         // any use, without warranty, 2024 by Wilson Snyder.
         // SPDX-License-Identifier: CC0-1.0
         
-        module t (/*AUTOARG*/
+        module t (
-          // Inputs
+            input clk
-          clk
         );
         
-          input clk;
-        
           int cyc, bump, result;
           logic foo;
 %000001   initial begin

test_regress/t/t_cover_sys_line_expr.v

@@ -4,13 +4,10 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-  // Inputs
+    input clk
-  clk
 );
 
-  input clk;
-
   int cyc, bump, result;
   logic foo;
   initial begin

test_regress/t/t_covergroup_in_class_duplicate_bad.out

@@ -1,7 +1,7 @@
-%Error: t/t_covergroup_in_class_duplicate_bad.v:13:16: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
+%Error: t/t_covergroup_in_class_duplicate_bad.v:13:14: Duplicate declaration of CLASS '__vlAnonCG_embeddedCg': '__vlAnonCG_embeddedCg'
    13 |   covergroup embeddedCg;
       |              ^~~~~~~~~~
-        t/t_covergroup_in_class_duplicate_bad.v:9:16: ... Location of original declaration
+        t/t_covergroup_in_class_duplicate_bad.v:9:14: ... Location of original declaration
     9 |   covergroup embeddedCg;
       |              ^~~~~~~~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.

test_regress/t/t_define_override.v

@@ -10,8 +10,7 @@
 
 `define STRINGIFY(x) `"x`"
 
-module test (
+module test ();
-);
   initial begin
     $display("TEST_MACRO %s", `STRINGIFY(`TEST_MACRO));
     $finish;

test_regress/t/t_delay_1step.v

@@ -5,8 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-  timeunit 10s;
+  timeunit 10s; timeprecision 1s;
-  timeprecision 1s;
 
   initial begin
     #1;

test_regress/t/t_dfg_bin_to_one_hot.v

@@ -4,14 +4,14 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0)
+`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+    input clk
-   clk
 );
-   input clk;
 
    reg [31:0] cyc = 0;
    reg [6:0] cntA = 0;

test_regress/t/t_dfg_circular_merged_scc.v

@@ -4,7 +4,11 @@
 // any use, without warranty, 2025 by Geza Lore.
 // SPDX-License-Identifier: CC0-1.0
 
-module mul (input [8:0] A, input [16:0] B, output [25:0] Y);
+module mul (
+    input [8:0] A,
+    input [16:0] B,
+    output [25:0] Y
+);
   assign Y = $signed(A) * $signed(B);
 endmodule
 

test_regress/t/t_dfg_regularize_clk.v

@@ -4,9 +4,10 @@
 // without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define checkd(gotv,
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
-               expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module sub (
     input clk,

test_regress/t/t_dfg_result_var_ext_write.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
-`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: $time=%0t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module top;
 

test_regress/t/t_dfg_true_cycle_bad.out

@@ -4,6 +4,6 @@
                     ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
                     ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                     t/t_dfg_true_cycle_bad.v:10:23:      Example path: o
-                    t/t_dfg_true_cycle_bad.v:12:22:      Example path: ASSIGNW
+                    t/t_dfg_true_cycle_bad.v:12:20:      Example path: ASSIGNW
                     t/t_dfg_true_cycle_bad.v:10:23:      Example path: o
 %Error: Exiting due to

test_regress/t/t_disable_bad.out

@@ -1,8 +1,8 @@
-%Error: t/t_disable_bad.v:9:15: Can't find definition of block/task: 'abcd'
+%Error: t/t_disable_bad.v:9:13: Can't find definition of block/task: 'abcd'
     9 |     disable abcd;
       |             ^~~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: Internal Error: t/t_disable_bad.v:9:7: ../V3LinkJump.cpp:#: Unlinked disable statement
+%Error: Internal Error: t/t_disable_bad.v:9:5: ../V3LinkJump.cpp:#: Unlinked disable statement
     9 |     disable abcd;
       |     ^~~~~~~
                         ... This fatal error may be caused by the earlier error(s); resolve those first.

test_regress/t/t_dpi_inline_new.v

@@ -9,8 +9,10 @@
 package pyhdl_if;
 
   typedef chandle PyObject;
-  import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(input PyObject p0,
+  import "DPI-C" context function PyObject _pyhdl_if_PyTuple_GetItem(
-                                    input longint unsigned p1);
+    input PyObject p0,
+    input longint unsigned p1
+  );
 
   function PyObject PyTuple_GetItem(input PyObject p0, input longint unsigned p1);
     return _pyhdl_if_PyTuple_GetItem(p0, p1);
@@ -32,11 +34,9 @@ package pyhdl_if;
 
 endpackage
 
-module t (/*AUTOARG*/
+module t (
-  // Inputs
+    input clk
-  clk
 );
-  input clk;
 
   import pyhdl_if::*;
 

test_regress/t/t_event_control_expr_unsup.out

@@ -1,4 +1,4 @@
-%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:21: Unsupported: Impure function calls in sensitivity lists
+%Error-UNSUPPORTED: t/t_event_control_expr_unsup.v:15:20: Unsupported: Impure function calls in sensitivity lists
    15 |   always @(posedge foo());
       |                    ^~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest

test_regress/t/t_expr_shortcircuit.v

@@ -4,13 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t (/*AUTOARG*/
+module t (
-   // Inputs
+    input clk
-   clk
 );
 
-  input clk;
-
   int cyc = 0;
 
   function automatic logic is_odd(int value);
@@ -20,8 +17,7 @@ module t (/*AUTOARG*/
   endfunction
 
   always_ff @(posedge clk) begin
-    if (cyc[0] == 1'b0 || is_odd(cyc))
+    if (cyc[0] == 1'b0 || is_odd(cyc)) cyc <= cyc + 1;
-      cyc <= cyc + 1;
     if (cyc == 10) begin
       $write("*-* All Finished *-*\n");
       $finish;

test_regress/t/t_flag_unroll_limit_const.out

@@ -1,7 +1,7 @@
-%Error: t/t_flag_unroll_limit_const.v:17:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f'
+%Error: t/t_flag_unroll_limit_const.v:17:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f'
                                            : ... note: In instance 't'
         t/t_flag_unroll_limit_const.v:9:3: ... Location of non-constant LOOP: Loop simulation took too long; probably this is an infinite loop, otherwise set '--unroll-limit' above 4
-        t/t_flag_unroll_limit_const.v:17:16: ... Called from 'f()' with parameters:
+        t/t_flag_unroll_limit_const.v:17:19: ... Called from 'f()' with parameters:
            x = ?32?h5
    17 |     output logic [f(5):0] o5   
       |                   ^

test_regress/t/t_force.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_chained.out

@@ -1,4 +1,4 @@
-%Error: t/t_force_chained.v:27:  got='h0 exp='h00000001
+%Error: t/t_force_chained.v:30:  got='h0 exp='h00000001
-%Error: t/t_force_chained.v:33:  got='h0 exp='h00000002
+%Error: t/t_force_chained.v:36:  got='h0 exp='h00000002
-%Error: t/t_force_chained.v:40:  got='h0 exp='h00000003
+%Error: t/t_force_chained.v:43:  got='h0 exp='h00000003
-%Error: t/t_force_chained.v:46:  got='h0 exp='h00000003
+%Error: t/t_force_chained.v:49:  got='h0 exp='h00000003

test_regress/t/t_force_chained.v

@@ -4,7 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop  // TODO
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
   module t;
   reg [1:0] a;

test_regress/t/t_force_complex_sel_unsup.out

@@ -1,10 +1,10 @@
-%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:37:22: Unsupported: Force / release statement with complex select expression
+%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:41:22: Unsupported: Force / release statement with complex select expression
                                                        : ... note: In instance 't'
-   37 |       force logic_arr[($c(1))] = 0;
+   41 |       force logic_arr[($c(1))] = 0;
       |                      ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:44:24: Unsupported: Force / release statement with complex select expression
+%Error-UNSUPPORTED: t/t_force_complex_sel_unsup.v:51:24: Unsupported: Force / release statement with complex select expression
                                                        : ... note: In instance 't'
-   44 |       release logic_arr[($c(1))];
+   51 |       release logic_arr[($c(1))];
       |                        ^
 %Error: Exiting due to

test_regress/t/t_force_complex_sel_unsup.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 `ifdef VERILATOR
 // The '$c(1)' is there to prevent inlining of the signal by V3Gate
@@ -31,23 +33,31 @@ module t (  /*AUTOARG*/
     cyc <= cyc + 1;
     if (cyc == 0) begin
       logic_arr[`IMPURE_ONE] <= 1;
-    end else if (cyc == 1) begin
+    end
+    else if (cyc == 1) begin
       `checkh(logic_arr[`IMPURE_ONE], 1);
-    end else if (cyc == 2) begin
+    end
+    else if (cyc == 2) begin
       force logic_arr[`IMPURE_ONE] = 0;
-    end else if (cyc == 3) begin
+    end
+    else if (cyc == 3) begin
       `checkh(logic_arr[`IMPURE_ONE], 0);
       logic_arr[`IMPURE_ONE] <= 1;
-    end else if (cyc == 4) begin
+    end
+    else if (cyc == 4) begin
       `checkh(logic_arr[`IMPURE_ONE], 0);
-    end else if (cyc == 5) begin
+    end
+    else if (cyc == 5) begin
       release logic_arr[`IMPURE_ONE];
-    end else if (cyc == 6) begin
+    end
+    else if (cyc == 6) begin
       `checkh(logic_arr[`IMPURE_ONE], 0);
       logic_arr[`IMPURE_ONE] <= 1;
-    end else if (cyc == 7) begin
+    end
+    else if (cyc == 7) begin
       `checkh(logic_arr[`IMPURE_ONE], 1);
-    end else if (cyc == 8) begin
+    end
+    else if (cyc == 8) begin
       $write("*-* All Finished *-*\n");
       $finish;
     end

test_regress/t/t_force_func.out

@@ -1,4 +1,4 @@
-%Error: t/t_force_func.v:26:  got='h0 exp='h00000001
+%Error: t/t_force_func.v:29:  got='h0 exp='h00000001
-%Error: t/t_force_func.v:34:  got='h0 exp='h00000002
+%Error: t/t_force_func.v:37:  got='h0 exp='h00000002
-%Error: t/t_force_func.v:39:  got='h0 exp='h00000003
+%Error: t/t_force_func.v:42:  got='h0 exp='h00000003
-%Error: t/t_force_func.v:43:  got='h0 exp='h00000003
+%Error: t/t_force_func.v:46:  got='h0 exp='h00000003

test_regress/t/t_force_func.v

@@ -4,7 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop  // TODO
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
   function bit [1:0] get_arg (bit [1:0] x);
    return x;

test_regress/t/t_force_immediate_release.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t;
 

test_regress/t/t_force_initial.v

@@ -4,7 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
   module t;
   reg [1:0] a = 0;

test_regress/t/t_force_mid.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Outputs

test_regress/t/t_force_multi.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_port_inline.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2024 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module sub(
    input wire [7:0] i,

test_regress/t/t_force_release.out

@@ -1,4 +1,4 @@
          0 d=0,e=0
         10 d=1,e=1
         20 d=1,e=0
-%Error: t/t_force_release.v:36:  got='h1 exp='h00000000
+%Error: t/t_force_release.v:39:  got='h1 exp='h00000000

test_regress/t/t_force_release.v

@@ -4,7 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
+// verilog_format: off
+`define stop  // TODO
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 // Example from IEEE 1800-2023 10.6.2
 

test_regress/t/t_force_release_net.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2022 by Geza Lore.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t (/*AUTOARG*/
    // Inputs

test_regress/t/t_force_release_var.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Geza Lore.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t (/*AUTOARG*/
    // Inputs

test_regress/t/t_force_rhs_ref.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t;
   reg [1:0] a;

test_regress/t/t_force_rhs_ref_multi_lhs.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t;
   bit [1:0] a;

test_regress/t/t_force_rhs_ref_multiple.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t;
   logic [7:0] a = 1;

test_regress/t/t_force_struct_partial.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 typedef struct packed {
     logic sig1;

test_regress/t/t_force_subnet.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_subvar.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_tri.out

@@ -1,6 +1,6 @@
-%Error-UNSUPPORTED: t/t_force_tri.v:27:10: Unsupported tristate construct: ASSIGNFORCE
+%Error-UNSUPPORTED: t/t_force_tri.v:29:10: Unsupported tristate construct: ASSIGNFORCE
                                          : ... note: In instance 't'
-   27 |          force bus = 4'bzz10;
+   29 |          force bus = 4'bzz10;
       |          ^~~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Exiting due to

test_regress/t/t_force_tri.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+// verilog_format: on
 
 module t(/*AUTOARG*/
    // Inputs

test_regress/t/t_force_unpacked.v

@@ -4,15 +4,15 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
-module t (  /*AUTOARG*/
+module t (
-    // Inputs
+    input clk
-    clk
 );
-  input clk;
 
   integer cyc = 0;
 

test_regress/t/t_force_unpacked_unsup.v

@@ -4,15 +4,15 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
 `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
-module t (  /*AUTOARG*/
+module t (
-    // Inputs
+    input clk
-    clk
 );
-  input clk;
 
   integer cyc = 0;
 

test_regress/t/t_foreach_noivar.v

@@ -4,8 +4,10 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module t;
 

test_regress/t/t_foreach_noivar_bad.out

@@ -1,11 +1,11 @@
-%Warning-NOEFFECT: t/t_foreach_noivar.v:17:5: foreach with no loop variable has no effect
+%Warning-NOEFFECT: t/t_foreach_noivar.v:19:5: foreach with no loop variable has no effect
                                             : ... note: In instance 't'
-   17 |     foreach (array[]) begin   
+   19 |     foreach (array[]) begin   
       |     ^~~~~~~
                    ... For warning description see https://verilator.org/warn/NOEFFECT?v=latest
                    ... Use "/* verilator lint_off NOEFFECT */" and lint_on around source to disable this message.
-%Warning-NOEFFECT: t/t_foreach_noivar.v:23:5: foreach with no loop variable has no effect
+%Warning-NOEFFECT: t/t_foreach_noivar.v:25:5: foreach with no loop variable has no effect
                                             : ... note: In instance 't'
-   23 |     foreach (array[,,]) begin   
+   25 |     foreach (array[,,]) begin   
       |     ^~~~~~~
 %Error: Exiting due to

test_regress/t/t_fork_delay_finish.v

@@ -7,9 +7,11 @@
 module t;
   bit flag;
   initial begin
-    fork begin
+    fork
+      begin
         $stop;
-    end join_none
+      end
+    join_none
     $finish;
   end
 endmodule

test_regress/t/t_func_automatic_clear.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Augustin Fabre.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 // Bug5747: Make sure that a variable with automatic storage is freshly
 // allocated when entering the function.

test_regress/t/t_func_purification.v

@@ -14,7 +14,8 @@ module t;
     if (x) begin
       if (x) begin
         return 1;
-      end else begin
+      end
+      else begin
         $c("");
       end
       return 0;

test_regress/t/t_func_virt_new.v

@@ -4,13 +4,16 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-class cl #(type T= int);
+class cl #(
+    type T = int
+);
   function void f();
     T obj = new;
   endfunction
 endclass
 virtual class vcl;
-endclass;
+endclass
+;
 module t;
   cl #(vcl) c = new;
   initial begin

test_regress/t/t_func_virt_new_bad.out

@@ -1,6 +1,6 @@
-%Error: t/t_func_virt_new_bad.v:9:13: Illegal to call 'new' using an abstract virtual class 'vcl' (IEEE 1800-2023 8.21)
+%Error: t/t_func_virt_new_bad.v:11:13: Illegal to call 'new' using an abstract virtual class 'vcl' (IEEE 1800-2023 8.21)
                                      : ... note: In instance 't'
-    9 |     T obj = new;
+   11 |     T obj = new;
       |             ^~~
         ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
 %Error: Exiting due to

test_regress/t/t_func_virt_new_bad.v

@@ -4,13 +4,16 @@
 // any use, without warranty, 2025 by Antmicro.
 // SPDX-License-Identifier: CC0-1.0
 
-class cl #(type T= int);
+class cl #(
+    type T = int
+);
   function void f();
     T obj = new;
   endfunction
 endclass
 virtual class vcl;
-endclass;
+endclass
+;
 module t;
   cl #(vcl) c = new;
   initial begin

test_regress/t/t_gen_class.v

@@ -4,9 +4,11 @@
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
 `define stop $stop
 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 module Child;
    int ch_value;