67 lines
1.8 KiB
Systemverilog
67 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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integer cyc = 0;
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logic logic_arr[2][-2:2][-3:-5];
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int int_arr[-1:2][1][3];
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// Test loop
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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logic_arr[0][2][-4] <= 1;
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int_arr[0][0][2] <= 1;
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end
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else if (cyc == 1) begin
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`checkh(logic_arr[0][2][-4], 1);
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`checkh(int_arr[0][0][2], 1);
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end
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else if (cyc == 2) begin
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force logic_arr[0][2][-4] = 0;
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force int_arr[0][0][2] = 0;
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end
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else if (cyc == 3) begin
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`checkh(logic_arr[0][2][-4], 0);
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logic_arr[0][2][-4] <= 1;
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`checkh(int_arr[0][0][2], 0);
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int_arr[0][0][2] <= 1;
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end
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else if (cyc == 4) begin
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`checkh(logic_arr[0][2][-4], 0);
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`checkh(int_arr[0][0][2], 0);
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end
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else if (cyc == 5) begin
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release logic_arr[0][2][-4];
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release int_arr[0][0][2];
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end
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else if (cyc == 6) begin
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`checkh(logic_arr[0][2][-4], 0);
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logic_arr[0][2][-4] <= 1;
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`checkh(int_arr[0][0][2], 0);
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int_arr[0][0][2] <= 1;
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end
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else if (cyc == 7) begin
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`checkh(logic_arr[0][2][-4], 1);
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`checkh(int_arr[0][0][2], 1);
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end
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else if (cyc == 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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