verilator/bin/verilator

552 lines
24 KiB
Plaintext
Raw Normal View History

#!/usr/bin/env perl
######################################################################
#
2024-01-01 09:19:59 +01:00
# Copyright 2003-2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
#
######################################################################
require 5.006_001;
use warnings;
use Getopt::Long;
use FindBin qw($RealBin $RealScript);
2014-11-28 13:56:21 +01:00
use IO::File;
use Pod::Usage;
use Cwd qw(realpath);
use strict;
use vars qw($Debug @Opt_Verilator_Sw);
#######################################################################
#######################################################################
# main
autoflush STDOUT 1;
autoflush STDERR 1;
$Debug = 0;
my $opt_gdb;
2019-07-26 03:34:09 +02:00
my $opt_rr;
2009-10-05 00:04:37 +02:00
my $opt_gdbbt;
my $opt_quiet_exit;
my $opt_unlimited_stack = 1;
2024-01-29 13:50:05 +01:00
my $opt_valgrind;
# No arguments can't do anything useful. Give help
if ($#ARGV < 0) {
pod2usage(-exitstatus => 2, -verbose => 0);
}
# Insert debugging options up front
push @ARGV, (split ' ', $ENV{VERILATOR_TEST_FLAGS} || "");
# We sneak a look at the flags so we can do some pre-environment checks
# All flags will hit verilator...
2010-01-19 02:37:20 +01:00
foreach my $sw (@ARGV) {
push @Opt_Verilator_Sw, $sw;
}
Getopt::Long::config("no_auto_abbrev", "pass_through");
2019-05-14 12:56:20 +02:00
if (! GetOptions(
# Major operating modes
"help" => \&usage,
"debug" => \&debug,
# "version!" => \&version, # Also passthru'ed
# Switches
"gdb!" => \$opt_gdb,
"gdbbt!" => \$opt_gdbbt,
"quiet-exit!" => \$opt_quiet_exit,
"rr!" => \$opt_rr,
"unlimited-stack!" => \$opt_unlimited_stack,
2024-01-29 13:50:05 +01:00
"valgrind!" => \$opt_valgrind,
# Additional parameters
"<>" => sub {}, # Ignored
)) {
pod2usage(-exitstatus => 2, -verbose => 0);
}
my $verilator_root = realpath("$RealBin/..");
if (defined $ENV{VERILATOR_ROOT}) {
if ((!-d $ENV{VERILATOR_ROOT}) || $verilator_root ne realpath($ENV{VERILATOR_ROOT})) {
warn "%Error: verilator: VERILATOR_ROOT is set to inconsistent path. Suggest leaving it unset.\n";
warn "%Error: VERILATOR_ROOT=$ENV{VERILATOR_ROOT}\n";
exit 1;
}
} else {
print "export VERILATOR_ROOT='$verilator_root'\n" if $Debug;
$ENV{VERILATOR_ROOT} = $verilator_root;
}
if ($opt_gdbbt && !gdb_works()) {
warn "-Info: --gdbbt ignored: gdb doesn't seem to be working\n" if $Debug;
$opt_gdbbt = 0;
}
# Determine runtime flags and run
# Opt_Verilator_Sw is what we want verilator to see on its argc/argv.
# Starting with that, escape all special chars for the shell;
# The shell will undo the escapes and the verilator binary should
# then see exactly the contents of @Opt_Verilator_Sw.
my @quoted_sw = map { sh_escape($_) } @Opt_Verilator_Sw;
2012-03-10 00:37:38 +01:00
if ($opt_gdb) {
# Generic GDB interactive
run (ulimit_stack_unlimited()
. aslr_off()
. ($ENV{VERILATOR_GDB} || "gdb")
. " " . verilator_bin()
2018-05-01 02:00:38 +02:00
# Note, uncomment to set breakpoints before running:
# ." -ex 'break main'"
# Note, we must use double-quotes ("run <switches>")
# and not single ('run <switches>') below. Bash swallows
# escapes as you would expect in a double-quoted string.
# That's not true for a single-quoted string, where \'
# actually terminates the string -- not what we want!
. " -ex \"run " . join(' ', @quoted_sw) . "\""
. " -ex 'set width 0'"
. " -ex 'bt'");
2019-07-26 03:34:09 +02:00
} elsif ($opt_rr) {
# Record with rr
run (ulimit_stack_unlimited()
. aslr_off()
. "rr record " . verilator_bin()
. " " . join(' ', @quoted_sw));
2012-03-10 00:37:38 +01:00
} elsif ($opt_gdbbt && $Debug) {
2009-10-05 00:04:37 +02:00
# Run under GDB to get gdbbt
run (ulimit_stack_unlimited()
. aslr_off()
. "gdb"
. " " . verilator_bin()
. " --batch --quiet --return-child-result"
. " -ex \"run " . join(' ', @quoted_sw)."\""
. " -ex 'set width 0'"
. " -ex 'bt' -ex 'quit'");
2024-01-29 13:50:05 +01:00
} elsif ($opt_valgrind) {
# Run under valgrind
my $valgrind_bin = ($ENV{VERILATOR_VALGRIND} || "valgrind --error-exitcode=1 --max-stackframe=2815880"
# Magic number sugested by valgrind, may need to be increased in future
# if you get warnings. See: https://valgrind.org/docs/manual/manual-core.html#opt.max-stackframe
);
run (ulimit_stack_unlimited()
. aslr_off()
. $valgrind_bin
. " " . verilator_bin()
. " " . join(' ', @quoted_sw));
} elsif ($Debug) {
# Debug
run(ulimit_stack_unlimited()
. aslr_off()
. verilator_bin()
. " " . join(' ', @quoted_sw));
2009-10-05 00:04:37 +02:00
} else {
# Normal, non gdb
run(ulimit_stack_unlimited() . verilator_bin() . " " . join(' ', @quoted_sw));
2009-10-05 00:04:37 +02:00
}
#----------------------------------------------------------------------
sub usage {
pod2usage(-verbose => 2, -exitval => 0, -output => \*STDOUT);
}
sub debug {
shift;
my $level = shift;
$Debug = $level || 3;
}
#######################################################################
#######################################################################
# Builds
sub verilator_bin {
my $basename = ($ENV{VERILATOR_BIN}
2016-10-01 00:14:42 +02:00
|| ($Debug ? "verilator_bin_dbg" : "verilator_bin"));
if (-x "$RealBin/$basename" || -x "$RealBin/$basename.exe") {
return "$RealBin/$basename";
} else {
return $basename; # Find in PATH
}
}
#######################################################################
#######################################################################
# Utilities
sub gdb_works {
$! = undef; # Cleanup -x
system("gdb /bin/echo"
. " --batch-silent --quiet --return-child-result"
. " -ex 'run -n'" # `echo -n`
. " -ex 'set width 0'"
. " -ex 'bt'"
. " -ex 'quit'");
my $status = $?;
return $status == 0;
}
sub aslr_off {
my $ok = `setarch --addr-no-randomize echo ok 2>/dev/null` || "";
if ($ok =~ /ok/) {
return "setarch --addr-no-randomize ";
} else {
return "";
}
}
sub ulimit_stack_unlimited {
return "" if !$opt_unlimited_stack;
system("ulimit -s unlimited 2>/dev/null");
my $status = $?;
if ($status == 0) {
return "ulimit -s unlimited 2>/dev/null; exec ";
} else {
return "";
}
}
sub run {
# Run command, check errors
my $command = shift;
$! = undef; # Cleanup -x
print "\t$command\n" if $Debug >= 3;
system($command);
my $status = $?;
if ($status) {
2016-10-01 00:14:42 +02:00
if ($! =~ /no such file or directory/i) {
warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
}
if ($Debug) { # For easy rerunning
warn "%Error: export VERILATOR_ROOT=" . ($ENV{VERILATOR_ROOT} || "") . "\n";
2016-10-01 00:14:42 +02:00
warn "%Error: $command\n";
}
if ($status & 127) {
2019-05-14 12:56:20 +02:00
if (($status & 127) == 4 # SIGILL
|| ($status & 127) == 8 # SIGFPA
|| ($status & 127) == 11) { # SIGSEGV
2020-04-29 03:15:27 +02:00
warn "%Error: Verilator internal fault, sorry. "
. "Suggest trying --debug --gdbbt\n" if !$Debug;
2016-10-01 00:14:42 +02:00
} elsif (($status & 127) == 6) { # SIGABRT
2020-04-29 03:15:27 +02:00
warn "%Error: Verilator aborted. "
. "Suggest trying --debug --gdbbt\n" if !$Debug;
2016-10-01 00:14:42 +02:00
} else {
2020-04-29 03:15:27 +02:00
warn "%Error: Verilator threw signal $status. "
. "Suggest trying --debug --gdbbt\n" if !$Debug;
2016-10-01 00:14:42 +02:00
}
}
if (!$opt_quiet_exit && ($status != 256 || $Debug)) { # i.e. not normal exit(1)
warn "%Error: Command Failed $command\n";
}
exit $! if $!; # errno
exit $? >> 8 if $? >> 8; # child exit status
exit 255; # last resort
}
}
sub sh_escape {
my ($arg) = @_;
# This is similar to quotemeta() but less aggressive.
# There's no need to escape hyphens, periods, or forward slashes
# for the shell as these have no special meaning to the shell.
$arg =~ s/([^0-9a-zA-Z_\-\+\=\.\/])/\\$1/g;
return $arg;
}
#######################################################################
#######################################################################
package main;
__END__
=pod
=head1 NAME
2019-10-27 15:29:19 +01:00
Verilator - Translate and simulate SystemVerilog code using C++/SystemC
2020-06-29 00:37:42 +02:00
=head1 SYNOPSIS
verilator --help
verilator --version
verilator --binary -j 0 [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
2016-11-27 22:37:51 +01:00
verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
verilator --lint-only -Wall [source_files.v]...
2020-06-29 00:37:42 +02:00
=head1 DESCRIPTION
2020-06-29 00:37:42 +02:00
The "Verilator" package converts all synthesizable, and many behavioral,
Verilog and SystemVerilog designs into a C++ or SystemC model that after
compiling can be executed. Verilator is not a traditional simulator, but a
compiler.
For documentation see L<https://verilator.org/verilator_doc.html>.
2010-02-07 01:56:14 +01:00
=head1 ARGUMENT SUMMARY
2020-06-29 00:37:42 +02:00
This is a short summary of the arguments to the "verilator" executable.
2021-04-13 15:25:11 +02:00
See L<https://verilator.org/guide/latest/exe_verilator.html> for the
detailed descriptions of these arguments.
2021-04-03 19:11:26 +02:00
=for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst"
2022-12-11 02:09:47 +01:00
<file.v> Verilog package, module, and top module filenames
2021-04-03 19:11:26 +02:00
<file.c/cc/cpp> Optional C++ files to compile in
<file.a/o/so> Optional C++ files to link in
+1364-1995ext+<ext> Use Verilog 1995 with file extension <ext>
+1364-2001ext+<ext> Use Verilog 2001 with file extension <ext>
+1364-2005ext+<ext> Use Verilog 2005 with file extension <ext>
+1800-2005ext+<ext> Use SystemVerilog 2005 with file extension <ext>
+1800-2009ext+<ext> Use SystemVerilog 2009 with file extension <ext>
+1800-2012ext+<ext> Use SystemVerilog 2012 with file extension <ext>
+1800-2017ext+<ext> Use SystemVerilog 2017 with file extension <ext>
--assert Enable all assertions
2024-02-23 15:05:53 +01:00
--assert-case Enable unique/unique0/priority case related checks
2008-07-16 20:06:08 +02:00
--autoflush Flush streams after all $displays
--bbox-sys Blackbox unknown $system calls
--bbox-unsup Blackbox unsupported language features
--binary Build model binary
--build Build model executable/library after Verilation
2022-09-18 16:32:43 +02:00
--build-dep-bin <filename> Override build dependency Verilator binary
--build-jobs <jobs> Parallelism for --build
--cc Create C++ output
-CFLAGS <flags> C++ compiler arguments for makefile
--clk <signal-name> Mark specified signal as clock
--no-clk <signal-name> Prevent marking specified signal as clock
--compiler <compiler-name> Tune for specified C++ compiler
2012-06-01 00:56:31 +02:00
--converge-limit <loops> Tune convergence settle time
--coverage Enable all coverage
--coverage-line Enable line coverage
2021-03-30 00:54:51 +02:00
--coverage-max-width <width> Maximum array depth for coverage
2008-12-12 21:34:02 +01:00
--coverage-toggle Enable toggle coverage
2012-03-09 00:36:51 +01:00
--coverage-underscore Enable coverage of _signals
--coverage-user Enable SVL user coverage
2010-02-02 03:12:00 +01:00
-D<var>[=<value>] Set preprocessor define
--debug Enable debugging
--debug-check Enable debugging assertions
--no-debug-leak Disable leaking memory in --debug mode
2009-01-21 22:56:50 +01:00
--debugi <level> Enable debugging at a specified level
--debugi-<srcfile> <level> Enable debugging a source file at a level
--decorations <level> Set output comment and spacing level
--no-decoration Disable comments and lower spacing level
--default-language <lang> Default language to parse
+define+<var>=<value> Set preprocessor define
2019-08-28 03:36:59 +02:00
--dpi-hdr-only Only produce the DPI header file
2018-10-26 01:45:06 +02:00
--dump-defines Show preprocessor defines with -E
Introduce DFG based combinational logic optimizer (#3527) Added a new data-flow graph (DFG) based combinational logic optimizer. The capabilities of this covers a combination of V3Const and V3Gate, but is also more capable of transforming combinational logic into simplified forms and more. This entail adding a new internal representation, `DfgGraph`, and appropriate `astToDfg` and `dfgToAst` conversion functions. The graph represents some of the combinational equations (~continuous assignments) in a module, and for the duration of the DFG passes, it takes over the role of AstModule. A bulk of the Dfg vertices represent expressions. These vertex classes, and the corresponding conversions to/from AST are mostly auto-generated by astgen, together with a DfgVVisitor that can be used for dynamic dispatch based on vertex (operation) types. The resulting combinational logic graph (a `DfgGraph`) is then optimized in various ways. Currently we perform common sub-expression elimination, variable inlining, and some specific peephole optimizations, but there is scope for more optimizations in the future using the same representation. The optimizer is run directly before and after inlining. The pre inline pass can operate on smaller graphs and hence converges faster, but still has a chance of substantially reducing the size of the logic on some designs, making inlining both faster and less memory intensive. The post inline pass can then optimize across the inlined module boundaries. No optimization is performed across a module boundary. For debugging purposes, each peephole optimization can be disabled individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one of the optimizations listed in V3DfgPeephole.h, for example -fno-dfg-peephole-remove-not-not. The peephole patterns currently implemented were mostly picked based on the design that inspired this work, and on that design the optimizations yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As you can imagine not having to haul around redundant combinational networks in the rest of the compilation pipeline also helps with memory consumption, and up to 30% peak memory usage of Verilator was observed on the same design. Gains on other arbitrary designs are smaller (and can be improved by analyzing those designs). For example OpenTitan gains between 1-15% speedup depending on build type.
2022-09-23 17:46:22 +02:00
--dump-dfg Enable dumping DfgGraphs to .dot files
--dump-graph Enable dumping V3Graphs to .dot files
--dump-tree Enable dumping Ast .tree files
--dump-tree-addrids Use short identifiers instead of addresses
--dump-tree-dot Enable dumping Ast .tree.dot debug files
--dump-<srcfile> Enable dumping everything in source file
Introduce DFG based combinational logic optimizer (#3527) Added a new data-flow graph (DFG) based combinational logic optimizer. The capabilities of this covers a combination of V3Const and V3Gate, but is also more capable of transforming combinational logic into simplified forms and more. This entail adding a new internal representation, `DfgGraph`, and appropriate `astToDfg` and `dfgToAst` conversion functions. The graph represents some of the combinational equations (~continuous assignments) in a module, and for the duration of the DFG passes, it takes over the role of AstModule. A bulk of the Dfg vertices represent expressions. These vertex classes, and the corresponding conversions to/from AST are mostly auto-generated by astgen, together with a DfgVVisitor that can be used for dynamic dispatch based on vertex (operation) types. The resulting combinational logic graph (a `DfgGraph`) is then optimized in various ways. Currently we perform common sub-expression elimination, variable inlining, and some specific peephole optimizations, but there is scope for more optimizations in the future using the same representation. The optimizer is run directly before and after inlining. The pre inline pass can operate on smaller graphs and hence converges faster, but still has a chance of substantially reducing the size of the logic on some designs, making inlining both faster and less memory intensive. The post inline pass can then optimize across the inlined module boundaries. No optimization is performed across a module boundary. For debugging purposes, each peephole optimization can be disabled individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one of the optimizations listed in V3DfgPeephole.h, for example -fno-dfg-peephole-remove-not-not. The peephole patterns currently implemented were mostly picked based on the design that inspired this work, and on that design the optimizations yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As you can imagine not having to haul around redundant combinational networks in the rest of the compilation pipeline also helps with memory consumption, and up to 30% peak memory usage of Verilator was observed on the same design. Gains on other arbitrary designs are smaller (and can be improved by analyzing those designs). For example OpenTitan gains between 1-15% speedup depending on build type.
2022-09-23 17:46:22 +02:00
--dumpi-dfg <level> Enable dumping DfgGraphs to .dot files at level
--dumpi-graph <level> Enable dumping V3Graphs to .dot files at level
--dumpi-tree <level> Enable dumping Ast .tree files at level
--dumpi-<srcfile> <level> Enable dumping everything in source file at level
-E Preprocess, but do not compile
--error-limit <value> Abort after this number of errors
--exe Link to create executable
2021-06-06 16:27:01 +02:00
--expand-limit <value> Set expand optimization limit
2021-04-03 19:11:26 +02:00
-F <file> Parse arguments from a file, relatively
-f <file> Parse arguments from a file
-FI <file> Force include of a file
--flatten Force inlining of all modules, tasks and functions
--future0 <option> Ignore an option for compatibility
--future1 <option> Ignore an option with argument for compatibility
2022-06-04 14:37:42 +02:00
-fno-<optimization> Disable internal optimization stage
2020-06-29 00:37:42 +02:00
-G<name>=<value> Overwrite top-level parameter
--gate-stmts <value> Tune gate optimizer depth
2012-03-10 00:37:38 +01:00
--gdb Run Verilator under GDB interactively
2011-02-18 13:11:03 +01:00
--gdbbt Run Verilator under GDB for backtrace
2019-10-10 00:53:30 +02:00
--generate-key Create random key for --protect-key
2017-09-24 00:03:39 +02:00
--getenv <var> Get environment variable with defaults
--get-supported <feature> Get if feature is supported
--help Display this help
--hierarchical Enable hierarchical Verilation
2010-02-02 03:12:00 +01:00
-I<dir> Directory to search for includes
--if-depth <value> Tune IFDEPTH warning
2010-02-02 03:12:00 +01:00
+incdir+<dir> Directory to search for includes
--inline-mult <value> Tune module inlining
--instr-count-dpi <value> Assumed dynamic instruction count of DPI imports
-j <jobs> Parallelism for --build-jobs/--verilate-jobs
--l2-name <value> Verilog scope name of the top module
--language <lang> Default language standard to parse
-LDFLAGS <flags> Linker pre-object arguments for makefile
--lib-create <name> Create a DPI library
2010-02-02 03:12:00 +01:00
+libext+<ext>+[ext]... Extensions for finding modules
--lint-only Lint, but do not make output
--make <build-tool> Generate scripts for specified build tool
2021-04-03 19:11:26 +02:00
-MAKEFLAGS <flags> Arguments to pass to make during --build
2022-09-16 02:26:08 +02:00
--main Generate C++ main() file
--main-top-name Specify top name passed to Verilated model in generated C++ main
--max-num-width <value> Maximum number width (default: 64K)
--Mdir <directory> Name of output object directory
--MMD Create .d dependency files
--mod-prefix <topname> Name to prepend to lower classes
--MP Create phony dependency targets
2010-02-02 03:12:00 +01:00
+notimingchecks Ignored
-O0 Disable optimizations
2022-12-11 02:09:47 +01:00
-O3 High-performance optimizations
2010-02-02 03:12:00 +01:00
-O<optimization-letter> Selectable optimizations
-o <executable> Name of final executable
2019-12-01 18:43:41 +01:00
--output-split <statements> Split .cpp files into pieces
2020-06-20 01:22:39 +02:00
--output-split-cfuncs <statements> Split model functions
--output-split-ctrace <statements> Split tracing functions
-P Disable line numbers and blanks with -E
2022-12-11 02:09:47 +01:00
--pins-bv <bits> Specify types for top-level ports
--pins-sc-biguint Specify types for top-level ports
--pins-sc-uint Specify types for top-level ports
--pins-uint8 Specify types for top-level ports
--no-pins64 Don't use uint64_t's for 33-64 bit sigs
--pipe-filter <command> Filter all input through a script
2018-10-26 03:17:25 +02:00
--pp-comments Show preprocessor comments with -E
2022-12-11 02:09:47 +01:00
--prefix <topname> Name of top-level class
--private Debugging; see docs
--prof-c Compile C++ code with profiling
--prof-cfuncs Name functions for profiling
--prof-exec Enable generating execution profile for gantt chart
--prof-pgo Enable generating profiling data for PGO
--protect-ids Hash identifier names for obscurity
--protect-key <key> Key for symbol protection
--protect-lib <name> Create a DPI protected library
--public Mark signals as public; see docs
--public-depth <level> Mark public to specified module depth
2023-03-09 01:38:26 +01:00
--public-params Mark all parameters as public_flat
--public-flat-rw Mark all variables, etc as public_flat_rw
-pvalue+<name>=<value> Overwrite toplevel parameter
--quiet-exit Don't print the command on failure
2017-02-10 00:33:18 +01:00
--relative-includes Resolve includes relative to current file
--reloop-limit Minimum iterations for forming loops
--report-unoptflat Extra diagnostics for UNOPTFLAT
2019-07-26 03:34:09 +02:00
--rr Run Verilator and record with rr
--runtime-debug Enable model runtime debugging
2016-10-01 00:14:42 +02:00
--savable Enable model save-restore
--sc Create SystemC output
--no-skip-identical Disable skipping identical output
--stats Create statistics file
2014-12-20 14:28:31 +01:00
--stats-vars Provide statistics on variables
--no-std Prevent parsing standard library
--no-stop-fail Do not call $stop when assertion fails
2022-12-21 01:22:42 +01:00
--structs-packed Convert all unpacked structures to packed structures
2010-02-02 03:12:00 +01:00
-sv Enable SystemVerilog parsing
2024-03-15 15:32:31 +01:00
+systemverilogext+<ext> Synonym for +1800-2017ext+<ext>
--threads <threads> Enable multithreading
--threads-dpi <mode> Enable multithreaded DPI
--threads-max-mtasks <mtasks> Tune maximum mtask partitioning
Timing support (#3363) Adds timing support to Verilator. It makes it possible to use delays, event controls within processes (not just at the start), wait statements, and forks. Building a design with those constructs requires a compiler that supports C++20 coroutines (GCC 10, Clang 5). The basic idea is to have processes and tasks with delays/event controls implemented as C++20 coroutines. This allows us to suspend and resume them at any time. There are five main runtime classes responsible for managing suspended coroutines: * `VlCoroutineHandle`, a wrapper over C++20's `std::coroutine_handle` with move semantics and automatic cleanup. * `VlDelayScheduler`, for coroutines suspended by delays. It resumes them at a proper simulation time. * `VlTriggerScheduler`, for coroutines suspended by event controls. It resumes them if its corresponding trigger was set. * `VlForkSync`, used for syncing `fork..join` and `fork..join_any` blocks. * `VlCoroutine`, the return type of all verilated coroutines. It allows for suspending a stack of coroutines (normally, C++ coroutines are stackless). There is a new visitor in `V3Timing.cpp` which: * scales delays according to the timescale, * simplifies intra-assignment timing controls and net delays into regular timing controls and assignments, * simplifies wait statements into loops with event controls, * marks processes and tasks with timing controls in them as suspendable, * creates delay, trigger scheduler, and fork sync variables, * transforms timing controls and fork joins into C++ awaits There are new functions in `V3SchedTiming.cpp` (used by `V3Sched.cpp`) that integrate static scheduling with timing. This involves providing external domains for variables, so that the necessary combinational logic gets triggered after coroutine resumption, as well as statements that need to be injected into the design eval function to perform this resumption at the correct time. There is also a function that transforms forked processes into separate functions. See the comments in `verilated_timing.h`, `verilated_timing.cpp`, `V3Timing.cpp`, and `V3SchedTiming.cpp`, as well as the internals documentation for more details. Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-08-22 14:26:32 +02:00
--timing Enable timing support
--no-timing Disable timing support
--timescale <timescale> Sets default timescale
--timescale-override <timescale> Overrides all timescales
--top <topname> Alias of --top-module
2022-12-11 02:09:47 +01:00
--top-module <topname> Name of top-level input module
--trace Enable waveform creation
2019-10-27 14:27:18 +01:00
--trace-coverage Enable tracing of coverage
--trace-depth <levels> Depth of tracing
--trace-fst Enable FST waveform creation
2011-09-15 03:11:14 +02:00
--trace-max-array <depth> Maximum bit width for tracing
--trace-max-width <width> Maximum array depth for tracing
2019-10-27 14:27:18 +01:00
--trace-params Enable tracing of parameters
--trace-structs Enable tracing structure names
--trace-threads <threads> Enable FST waveform creation on separate threads
2023-08-19 10:51:29 +02:00
--no-trace-top Do not emit traces for signals in the top module generated by verilator
--trace-underscore Enable tracing of _signals
2010-02-02 03:12:00 +01:00
-U<var> Undefine preprocessor define
--no-unlimited-stack Don't disable stack size limit
--unroll-count <loops> Tune maximum loop iterations
--unroll-stmts <stmts> Tune maximum loop body size
2011-01-02 01:43:22 +01:00
--unused-regexp <regexp> Tune UNUSED lint signals
2010-02-02 03:12:00 +01:00
-V Verbose version and config
-v <filename> Verilog library
2024-01-29 13:50:05 +01:00
--valgrind Run Verilator under valgrind
--verilate-jobs Job threads for Verilation stage
2022-12-23 17:32:38 +01:00
--no-verilate Skip Verilation and just compile previously Verilated code
+verilog1995ext+<ext> Synonym for +1364-1995ext+<ext>
+verilog2001ext+<ext> Synonym for +1364-2001ext+<ext>
2018-05-19 20:50:28 +02:00
--version Displays program version and exits
--vpi Enable VPI compiles
--waiver-output <filename> Create a waiver file based on the linter warnings
-Wall Enable all style warnings
-Werror-<message> Convert warnings to errors
2010-02-02 03:12:00 +01:00
-Wfuture-<message> Disable unknown message warnings
-Wno-<message> Disable warning
-Wno-context Disable source context on warnings
2019-11-16 17:59:21 +01:00
-Wno-fatal Disable fatal exit on warnings
2010-02-02 03:12:00 +01:00
-Wno-lint Disable all lint warnings
-Wno-style Disable all style warnings
2019-11-16 17:59:21 +01:00
-Wpedantic Warn on compliance-test issues
-Wwarn-<message> Enable specified warning message
-Wwarn-lint Enable lint warning message
-Wwarn-style Enable style warning message
2017-10-02 03:31:40 +02:00
--x-assign <mode> Assign non-initial Xs to this value
--x-initial <mode> Assign initial Xs to this value
--x-initial-edge Enable initial X->0 and X->1 edge triggers
--no-json-edit-nums Don't dump editNum in .tree.json files
--no-json-ids Don't use short identifiers instead of adresses/paths in .tree.json
--json-only Create JSON parser output (.tree.json and .meta.json)
--json-only-output .tree.json output filename
--json-only-meta-output .tree.meta.json output filename
2018-10-28 13:16:19 +01:00
--xml-only Create XML parser output
2019-11-01 02:17:05 +01:00
--xml-output XML output filename
2010-02-02 03:12:00 +01:00
-y <dir> Directory to search for modules
2020-06-29 00:37:42 +02:00
This is a short summary of the simulation runtime arguments, i.e. for the
final Verilated simulation runtime models. See
2021-04-13 15:25:11 +02:00
L<https://verilator.org/guide/latest/exe_verilator.html> for the detailed
description of these arguments.
2018-05-20 14:40:35 +02:00
2021-04-03 19:11:26 +02:00
=for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst"
2018-05-20 14:40:35 +02:00
+verilator+debug Enable debugging
2018-05-20 15:16:37 +02:00
+verilator+debugi+<value> Enable debugging at a level
+verilator+coverage+file+<filename> Set coverage output filename
2021-04-03 19:11:26 +02:00
+verilator+error+limit+<value> Set error limit
2018-05-20 14:40:35 +02:00
+verilator+help Display help
2021-04-03 19:11:26 +02:00
+verilator+noassert Disable assert checking
+verilator+prof+exec+file+<filename> Set execution profile filename
+verilator+prof+exec+start+<value> Set execution profile starting point
+verilator+prof+exec+window+<value> Set execution profile duration
+verilator+prof+vlt+file+<filename> Set PGO profile filename
2021-02-15 14:40:49 +01:00
+verilator+rand+reset+<value> Set random reset technique
+verilator+seed+<value> Set random seed
2018-05-20 14:40:35 +02:00
+verilator+V Verbose version and config
+verilator+version Show version and exit
2010-02-07 01:56:14 +01:00
=head1 DISTRIBUTION
2019-11-08 04:33:59 +01:00
The latest version is available from L<https://verilator.org>.
2024-01-01 09:19:59 +01:00
Copyright 2003-2024 by Wilson Snyder. This program is free software; you can
redistribute it and/or modify the Verilator internals under the terms of
either the GNU Lesser General Public License Version 3 or the Perl Artistic
License Version 2.0.
2020-02-13 04:46:59 +01:00
All Verilog and C++/SystemC code quoted within this documentation file are
released as Creative Commons Public Domain (CC0). Many example files and
test files are likewise released under CC0 into effectively the Public
Domain as described in the files themselves.
2020-06-29 00:37:42 +02:00
=head1 SEE ALSO
L<verilator_coverage>, L<verilator_gantt>, L<verilator_profcfunc>, L<make>,
2012-11-04 01:11:53 +01:00
L<verilator --help> which is the source for this document,
and L<https://verilator.org/verilator_doc.html> for detailed documentation.
=cut
######################################################################
2020-06-28 03:44:32 +02:00
# Local Variables:
# fill-column: 75
# End: