With --Wall, add IFDEPTH warning on deep if statements.
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16
Changes
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@ -7,24 +7,26 @@ indicates the contributor was also the author of the fix; Thanks!
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** Add limited support for VPI access to public signals, see docs.
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** Add -Wall, -Wwarn-style, -Wno-style to enable code style warnings
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that have been added to this release, and disabled by default.
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*** Add -F option to read relative option files, bug297. [Neil Hamilton]
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*** Support ++,--,+= etc as standalone statements. [Alex Solomatnikov]
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*** Suppress WIDTH warnings when adding/subtracting 1'b1.
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**** When running with VERILATOR_ROOT, optionally find binaries under bin.
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**** Suppress WIDTH warnings when adding/subtracting 1'b1.
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** Add -Wall, -Wwarn-style, -Wno-style to enable code style warnings
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that have been added to this release, and disabled by default:
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*** With --Wall, add DECLFILENAME warning on modules not matching filename.
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*** With --Wall, add DEFPARAM warning on deprecated defparam statements.
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*** With --Wall, add IFDEPTH warning on deep if statements.
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*** With --Wall, add INCABSPATH warning on `include with absolute paths.
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**** When running with VERILATOR_ROOT, optionally find binaries under bin.
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**** The VARHIDDEN warning is now disabled by default, use -Wall to enable.
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*** The VARHIDDEN warning is now disabled by default, use -Wall to enable.
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* Verilator 3.805 2010/11/02
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@ -255,6 +255,7 @@ descriptions in the next sections for more information.
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--gdbbt Run Verilator under GDB for backtrace
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--help Display this help
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-I<dir> Directory to search for includes
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--if-depth <value> Tune IFDEPTH warning
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+incdir+<dir> Directory to search for includes
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--inhibit-sim Create function to turn off sim
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--inline-mult <value> Tune module inlining
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@ -558,6 +559,11 @@ include directories or libraries. Same as +incdir and -y; +incdir and -y
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are fairly standard across Verilog tools while -I is an alias for GCC
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compatibility.
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=item --if-depth I<value>
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Rarely needed. Set the depth at which the IFDEPTH warning will fire,
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defaults to 0 which disables this warning.
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=item +incdir+I<dir>
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Add the directory to the list of directories that should be searched for
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@ -2420,6 +2426,16 @@ additional ones.)
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Ignoring this warning may make Verilator simulations differ from other
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simulators.
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=item IFDEPTH
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Warns that if/if else statements have exceeded the depth specified with
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--if-depth, as they are likely to result in slow priority encoders. Unique
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and priority if statements are ignored. Solutions include changing the
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code to a case statement, or a SystemVerilog 'unique if' or 'priority if'.
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Disabled by default as this is a code style warning, it will simulate
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correctly.
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=item IMPERFECTSCH
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Warns that the scheduling of the model is not absolutely perfect, and some
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@ -53,6 +53,7 @@ private:
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string m_namedScope; // Name of begin blocks above us
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string m_unnamedScope; // Name of begin blocks, including unnamed blocks
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int m_repeatNum; // Repeat counter
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int m_ifDepth; // Current if depth
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// METHODS
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static int debug() {
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@ -152,6 +153,21 @@ private:
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// any BEGINs, but V3Coverage adds them all under the module itself.
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nodep->iterateChildren(*this);
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}
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// VISITORS - LINT CHECK
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virtual void visit(AstIf* nodep, AstNUser*) { // Note not AstNodeIf; other types don't get covered
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// Check IFDEPTH warning - could be in other transform files if desire
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int prevIfDepth = m_ifDepth;
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if (m_ifDepth == -1 || v3Global.opt.ifDepth()<1) { // Turned off
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} else if (nodep->uniquePragma() || nodep->unique0Pragma() || nodep->priorityPragma()) {
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m_ifDepth = -1;
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} else if (++m_ifDepth > v3Global.opt.ifDepth()) {
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nodep->v3warn(IFDEPTH,"Deep 'if' statement; suggest unique/priority to avoid slow logic");
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nodep->fileline()->warnOn(V3ErrorCode::IFDEPTH, false); // Warn only once
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m_ifDepth = -1;
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}
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nodep->iterateChildren(*this);
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m_ifDepth = prevIfDepth;
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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nodep->iterateChildren(*this);
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}
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@ -161,6 +177,7 @@ public:
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m_modp = NULL;
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m_ftaskp = NULL;
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m_repeatNum = 0;
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m_ifDepth = 0;
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nodep->accept(*this);
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}
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virtual ~BeginVisitor() {}
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@ -63,9 +63,8 @@ public:
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COMBDLY, // Combinatorial delayed assignment
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DEFPARAM, // Style: Defparam
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DECLFILENAME, // Declaration doesn't match filename
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STMTDLY, // Delayed statement
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SYMRSVDWORD, // Symbol is Reserved Word
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GENCLK, // Generated Clock
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IFDEPTH, // If statements too deep
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IMPERFECTSCH, // Imperfect schedule (disabled by default)
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IMPLICIT, // Implicit wire
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IMPURE, // Impure function not being inlined
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@ -74,6 +73,8 @@ public:
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MODDUP, // Duplicate module
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MULTIDRIVEN, // Driven from multiple blocks
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REDEFMACRO, // Redefining existing define macro
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STMTDLY, // Delayed statement
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SYMRSVDWORD, // Symbol is Reserved Word
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UNDRIVEN, // No drivers
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UNOPT, // Unoptimizable block
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UNOPTFLAT, // Unoptimizable block after flattening
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@ -104,10 +105,11 @@ public:
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"BLKANDNBLK",
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"CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CDCRSTLOGIC", "CMPCONST",
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"COMBDLY", "DEFPARAM", "DECLFILENAME",
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"STMTDLY", "SYMRSVDWORD", "GENCLK", "IMPERFECTSCH", "IMPLICIT", "IMPURE",
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"INCABSPATH",
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"GENCLK",
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"IFDEPTH", "IMPERFECTSCH", "IMPLICIT", "IMPURE", "INCABSPATH",
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"LITENDIAN", "MODDUP",
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"MULTIDRIVEN", "REDEFMACRO",
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"STMTDLY", "SYMRSVDWORD",
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"UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNSIGNED", "UNUSED",
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"VARHIDDEN", "WIDTH", "WIDTHCONCAT",
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" MAX"
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@ -705,6 +705,10 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
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else if ( !strncmp (sw, "-I", 2)) {
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addIncDir (parseFileArg(optdir, string (sw+strlen("-I"))));
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}
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else if ( !strcmp (sw, "-if-depth") && (i+1)<argc ) {
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shift;
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m_ifDepth = atoi(argv[i]);
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}
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else if ( !strcmp (sw, "-inline-mult") && (i+1)<argc ) {
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shift;
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m_inlineMult = atoi(argv[i]);
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@ -1061,6 +1065,7 @@ V3Options::V3Options() {
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m_underlineZero = false;
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m_errorLimit = 50;
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m_ifDepth = 0;
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m_inlineMult = 2000;
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m_outputSplit = 0;
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m_outputSplitCFuncs = 0;
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@ -127,6 +127,7 @@ class V3Options {
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bool m_underlineZero;// main switch: --underline-zero; undocumented old Verilator 2
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int m_errorLimit; // main switch: --error-limit
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int m_ifDepth; // main switch: --if-depth
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int m_inlineMult; // main switch: --inline-mult
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int m_outputSplit; // main switch: --output-split
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int m_outputSplitCFuncs;// main switch: --output-split-cfuncs
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@ -245,6 +246,7 @@ class V3Options {
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bool inhibitSim() const { return m_inhibitSim; }
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int errorLimit() const { return m_errorLimit; }
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int ifDepth() const { return m_ifDepth; }
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int inlineMult() const { return m_inlineMult; }
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int outputSplit() const { return m_outputSplit; }
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int outputSplitCFuncs() const { return m_outputSplitCFuncs; }
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@ -0,0 +1,24 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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v_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"],
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fails=>1,
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verilator_make_gcc => 0,
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make_top_shell => 0,
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make_main => 0,
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expect=>
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'%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:\d+: Deep \'if\' statement; suggest unique/priority to avoid slow logic
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%Warning-IFDEPTH: Use .* to disable this message.
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%Error: Exiting due to.*',
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) if $Self->{v3};
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ok(1);
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1;
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@ -0,0 +1,40 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t;
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integer v = 19;
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initial begin
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if (v==1) begin end
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else if (v==2) begin end
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else if (v==3) begin end
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else if (v==4) begin end
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else if (v==5) begin end
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else if (v==6) begin end
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else if (v==7) begin end
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else if (v==8) begin end
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else if (v==9) begin end
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else if (v==10) begin end
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else if (v==11) begin end // Warn about this one
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else if (v==12) begin end
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end
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initial begin
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unique0 if (v==1) begin end
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else if (v==2) begin end
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else if (v==3) begin end
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else if (v==4) begin end
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else if (v==5) begin end
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else if (v==6) begin end
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else if (v==7) begin end
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else if (v==8) begin end
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else if (v==9) begin end
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else if (v==10) begin end
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else if (v==11) begin end // Warn about this one
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else if (v==12) begin end
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end
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endmodule
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