Untabify
This commit is contained in:
Wilson Snyder
parent
1e4c3751e1
commit
bd28945374
270
bin/verilator
270
bin/verilator
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@ -19,8 +19,8 @@ require 5.006_001;
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use warnings;
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BEGIN {
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if ($ENV{DIRPROJECT} && $ENV{DIRPROJECT_PERL_BOOT}) {
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# Magic to allow author testing of perl packages in local directory
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require $ENV{DIRPROJECT}."/".$ENV{DIRPROJECT_PERL_BOOT};
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# Magic to allow author testing of perl packages in local directory
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require $ENV{DIRPROJECT}."/".$ENV{DIRPROJECT_PERL_BOOT};
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}
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}
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@ -71,16 +71,16 @@ foreach my $sw (@ARGV) {
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Getopt::Long::config ("no_auto_abbrev","pass_through");
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if (! GetOptions (
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# Major operating modes
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"help" => \&usage,
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"debug:s" => \&debug,
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# "version!" => \&version, # Also passthru'ed
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# Switches
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"gdb!" => \$opt_gdb,
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"gdbbt!" => \$opt_gdbbt,
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# Additional parameters
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"<>" => sub {}, # Ignored
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)) {
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# Major operating modes
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"help" => \&usage,
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"debug:s" => \&debug,
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# "version!" => \&version, # Also passthru'ed
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# Switches
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"gdb!" => \$opt_gdb,
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"gdbbt!" => \$opt_gdbbt,
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# Additional parameters
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"<>" => sub {}, # Ignored
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)) {
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pod2usage(-exitstatus=>2, -verbose=>0);
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}
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@ -92,22 +92,22 @@ if ($opt_gdbbt && !gdb_works()) {
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if ($opt_gdb) {
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# Generic GDB interactive
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run (("gdb"||$ENV{VERILATOR_GDB})
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." ".verilator_bin()
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." -ex 'run ".join(' ',@Opt_Verilator_Sw)."'"
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." -ex 'set width 0'"
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." -ex 'bt'");
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." ".verilator_bin()
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." -ex 'run ".join(' ',@Opt_Verilator_Sw)."'"
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." -ex 'set width 0'"
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." -ex 'bt'");
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} elsif ($opt_gdbbt && $Debug) {
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# Run under GDB to get gdbbt
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run ("gdb"
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." ".verilator_bin()
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." --batch --quiet --return-child-result"
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." -ex 'run ".join(' ',@Opt_Verilator_Sw)."'"
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." -ex 'set width 0'"
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." -ex 'bt'");
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." ".verilator_bin()
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." --batch --quiet --return-child-result"
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." -ex 'run ".join(' ',@Opt_Verilator_Sw)."'"
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." -ex 'set width 0'"
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." -ex 'bt'");
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} else {
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# Normal, non gdb
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run (verilator_bin()
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." ".join(' ',@Opt_Verilator_Sw));
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." ".join(' ',@Opt_Verilator_Sw));
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}
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#----------------------------------------------------------------------
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@ -130,23 +130,23 @@ sub verilator_bin {
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my $bin = "";
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# Use VERILATOR_ROOT if defined, else assume verilator_bin is in the search path
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my $basename = ($ENV{VERILATOR_BIN}
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|| ($Debug ? "verilator_bin_dbg" : "verilator_bin"));
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|| ($Debug ? "verilator_bin_dbg" : "verilator_bin"));
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if (defined($ENV{VERILATOR_ROOT})) {
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my $dir = $ENV{VERILATOR_ROOT};
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if (-x "$dir/bin/$basename") { # From a "make install" into VERILATOR_ROOT
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$bin = "$dir/bin/$basename";
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} else {
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$bin = "$dir/$basename"; # From pointing to kit directory
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}
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my $dir = $ENV{VERILATOR_ROOT};
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if (-x "$dir/bin/$basename") { # From a "make install" into VERILATOR_ROOT
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$bin = "$dir/bin/$basename";
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} else {
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$bin = "$dir/$basename"; # From pointing to kit directory
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}
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} else {
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if (-x "$RealBin/$basename") {
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$bin = "$RealBin/$basename"; # From path/to/verilator with verilator_bin installed
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} else {
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$bin = $basename; # Find in PATH
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}
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# Note we don't look under bin/$basename which would be right if running
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# in the kit dir. Running that would likely break, since
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# VERILATOR_ROOT wouldn't be set and Verilator won't find internal files.
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if (-x "$RealBin/$basename") {
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$bin = "$RealBin/$basename"; # From path/to/verilator with verilator_bin installed
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} else {
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$bin = $basename; # Find in PATH
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}
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# Note we don't look under bin/$basename which would be right if running
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# in the kit dir. Running that would likely break, since
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# VERILATOR_ROOT wouldn't be set and Verilator won't find internal files.
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}
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return $bin;
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}
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@ -158,10 +158,10 @@ sub verilator_bin {
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sub gdb_works {
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$! = undef; # Cleanup -x
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system("gdb /bin/echo"
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." --batch-silent --quiet --return-child-result"
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." -ex 'run -n'" # `echo -n`
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." -ex 'set width 0'"
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." -ex 'bt'");
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." --batch-silent --quiet --return-child-result"
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." -ex 'run -n'" # `echo -n`
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." -ex 'set width 0'"
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." -ex 'bt'");
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my $status = $?;
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return $status==0;
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}
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@ -174,23 +174,23 @@ sub run {
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system($command);
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my $status = $?;
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if ($status) {
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if ($! =~ /no such file or directory/i) {
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warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
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}
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if ($Debug) { # For easy rerunning
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warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
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warn "%Error: $command\n";
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}
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if ($status & 127) {
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if (($status & 127) == 8 || ($status & 127) == 11) { # SIGFPA or SIGSEGV
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warn "%Error: Verilator internal fault, sorry. Consider trying --debug --gdbbt\n" if !$Debug;
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} elsif (($status & 127) == 6) { # SIGABRT
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warn "%Error: Verilator aborted. Consider trying --debug --gdbbt\n" if !$Debug;
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} else {
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warn "%Error: Verilator threw signal $status. Consider trying --debug --gdbbt\n" if !$Debug;
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}
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}
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die "%Error: Command Failed $command\n";
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if ($! =~ /no such file or directory/i) {
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warn "%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in environment\n";
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}
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if ($Debug) { # For easy rerunning
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warn "%Error: export VERILATOR_ROOT=".($ENV{VERILATOR_ROOT}||"")."\n";
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warn "%Error: $command\n";
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}
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if ($status & 127) {
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if (($status & 127) == 8 || ($status & 127) == 11) { # SIGFPA or SIGSEGV
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warn "%Error: Verilator internal fault, sorry. Consider trying --debug --gdbbt\n" if !$Debug;
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} elsif (($status & 127) == 6) { # SIGABRT
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warn "%Error: Verilator aborted. Consider trying --debug --gdbbt\n" if !$Debug;
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} else {
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warn "%Error: Verilator threw signal $status. Consider trying --debug --gdbbt\n" if !$Debug;
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}
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}
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die "%Error: Command Failed $command\n";
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}
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}
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@ -324,7 +324,7 @@ descriptions in the next sections for more information.
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--public Debugging; see docs
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-pvalue+<name>=<value> Overwrite toplevel parameter
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--report-unoptflat Extra diagnostics for UNOPTFLAT
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--savable Enable model save-restore
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--savable Enable model save-restore
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--sc Create SystemC output
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--stats Create statistics file
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--stats-vars Provide statistics on variables
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@ -1336,7 +1336,7 @@ We'll compile this example into C++.
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#include "Vour.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env) {
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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Vour* top = new Vour;
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while (!Verilated::gotFinish()) { top->eval(); }
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delete top;
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@ -1400,7 +1400,7 @@ This is an example similar to the above, but using SystemC.
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cat <<EOF >sc_main.cpp
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#include "Vour.h"
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int sc_main(int argc, char **argv) {
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Verilated::commandArgs(argc, argv);
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Verilated::commandArgs(argc, argv);
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sc_clock clk ("clk",10, 0.5, 3, true);
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Vour* top;
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top = new Vour("top"); // SP_CELL (top, Vour);
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@ -1529,42 +1529,42 @@ All output files are placed in the output directory name specified with the
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Verilator creates the following files in the output directory:
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{prefix}.mk // Make include file for compiling
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{prefix}_classes.mk // Make include file with class names
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{prefix}.mk // Make include file for compiling
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{prefix}_classes.mk // Make include file with class names
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For -cc and -sc mode, it also creates:
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{prefix}.cpp // Top level C++ file
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{prefix}.h // Top level header
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{prefix}{each_verilog_module}.cpp // Lower level internal C++ files
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{prefix}{each_verilog_module}.h // Lower level internal header files
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{prefix}.cpp // Top level C++ file
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{prefix}.h // Top level header
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{prefix}{each_verilog_module}.cpp // Lower level internal C++ files
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{prefix}{each_verilog_module}.h // Lower level internal header files
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In certain optimization modes, it also creates:
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{prefix}__Dpi.h // DPI import and export declarations
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{prefix}__Inlines.h // Inline support functions
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{prefix}__Slow.cpp // Constructors and infrequent routines
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{prefix}__Syms.cpp // Global symbol table C++
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{prefix}__Syms.h // Global symbol table header
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{prefix}__Trace.cpp // Wave file generation code (--trace)
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{prefix}__cdc.txt // Clock Domain Crossing checks (--cdc)
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{prefix}__stats.txt // Statistics (--stats)
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{prefix}__Dpi.h // DPI import and export declarations
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{prefix}__Inlines.h // Inline support functions
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{prefix}__Slow.cpp // Constructors and infrequent routines
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{prefix}__Syms.cpp // Global symbol table C++
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{prefix}__Syms.h // Global symbol table header
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{prefix}__Trace.cpp // Wave file generation code (--trace)
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{prefix}__cdc.txt // Clock Domain Crossing checks (--cdc)
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{prefix}__stats.txt // Statistics (--stats)
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It also creates internal files that can be mostly ignored:
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{each_verilog_module}.vpp // Post-processed verilog (--debug)
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{prefix}.flags_vbin // Verilator dependencies
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{prefix}.flags_vpp // Pre-processor dependencies
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{prefix}__verFiles.dat // Timestamps for skip-identical
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{prefix}{misc}.d // Make dependencies (-MMD)
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{prefix}{misc}.dot // Debugging graph files (--debug)
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{prefix}{misc}.tree // Debugging files (--debug)
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{each_verilog_module}.vpp // Post-processed verilog (--debug)
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{prefix}.flags_vbin // Verilator dependencies
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{prefix}.flags_vpp // Pre-processor dependencies
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{prefix}__verFiles.dat // Timestamps for skip-identical
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{prefix}{misc}.d // Make dependencies (-MMD)
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{prefix}{misc}.dot // Debugging graph files (--debug)
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{prefix}{misc}.tree // Debugging files (--debug)
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After running Make, the C++ compiler should produce the following:
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{prefix} // Final executable (w/--exe argument)
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{prefix}__ALL.a // Library of all Verilated objects
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{prefix}{misc}.o // Intermediate objects
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{prefix} // Final executable (w/--exe argument)
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{prefix}__ALL.a // Library of all Verilated objects
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{prefix}{misc}.o // Intermediate objects
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=head1 ENVIRONMENT
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@ -1659,46 +1659,46 @@ simulation executable.
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The user must write the top level of the simulation. Here's a simple
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example:
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#include <verilated.h> // Defines common routines
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#include "Vtop.h" // From Verilating "top.v"
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#include <verilated.h> // Defines common routines
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#include "Vtop.h" // From Verilating "top.v"
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Vtop *top; // Instantiation of module
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Vtop *top; // Instantiation of module
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vluint64_t main_time = 0; // Current simulation time
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// This is a 64-bit integer to reduce wrap over issues and
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// allow modulus. You can also use a double, if you wish.
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vluint64_t main_time = 0; // Current simulation time
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// This is a 64-bit integer to reduce wrap over issues and
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// allow modulus. You can also use a double, if you wish.
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double sc_time_stamp () { // Called by $time in Verilog
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return main_time; // converts to double, to match
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// what SystemC does
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}
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double sc_time_stamp () { // Called by $time in Verilog
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return main_time; // converts to double, to match
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// what SystemC does
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}
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv); // Remember args
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int main(int argc, char** argv) {
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Verilated::commandArgs(argc, argv); // Remember args
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top = new Vtop; // Create instance
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top = new Vtop; // Create instance
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top->reset_l = 0; // Set some inputs
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top->reset_l = 0; // Set some inputs
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while (!Verilated::gotFinish()) {
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if (main_time > 10) {
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top->reset_l = 1; // Deassert reset
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}
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if ((main_time % 10) == 1) {
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top->clk = 1; // Toggle clock
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}
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if ((main_time % 10) == 6) {
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top->clk = 0;
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}
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top->eval(); // Evaluate model
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cout << top->out << endl; // Read a output
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main_time++; // Time passes...
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}
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while (!Verilated::gotFinish()) {
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if (main_time > 10) {
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top->reset_l = 1; // Deassert reset
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}
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if ((main_time % 10) == 1) {
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top->clk = 1; // Toggle clock
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}
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if ((main_time % 10) == 6) {
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top->clk = 0;
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}
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top->eval(); // Evaluate model
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cout << top->out << endl; // Read a output
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main_time++; // Time passes...
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}
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top->final(); // Done simulating
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// // (Though this example doesn't get here)
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delete top;
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}
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top->final(); // Done simulating
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// // (Though this example doesn't get here)
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delete top;
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}
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Note signals are read and written as member variables of the lower module.
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You call the eval() method to evaluate the model. When the simulation is
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@ -1928,8 +1928,8 @@ VerilatedVpi::callValueCbs().
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...
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while (time passes) {
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...
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topp->eval();
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VerilatedVpi::callValueCbs();
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topp->eval();
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VerilatedVpi::callValueCbs();
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}
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@ -1973,10 +1973,10 @@ underneath NC:
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cd obj_dir
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ncsc_run \
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sc_main.cpp \
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Vour__ALLcls.cpp \
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Vour__ALLsup.cpp \
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verilated.cpp
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sc_main.cpp \
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Vour__ALLcls.cpp \
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Vour__ALLsup.cpp \
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verilated.cpp
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For larger designs you'll want to automate this using makefiles, which pull
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the names of the .cpp files to compile in from the make variables generated
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@ -2493,7 +2493,7 @@ such as $stop, $finish and $display. That is, you cannot use hierarchical
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references, events or similar features of the Verilog language. It also
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simulates as Synopsys's Design Compiler would; namely a block of the form:
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always @ (x) y = x & z;
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always @ (x) y = x & z;
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This will recompute y when there is even a potential for change in x or a
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change in z, that is when the flops computing x or z evaluate (which is
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@ -2837,9 +2837,9 @@ Warnings may be disabled in three ways. First, when the warning is
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printed it will include a warning code. Simply surround the offending
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line with a warn_off/warn_on pair:
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// verilator lint_off UNSIGNED
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if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
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// verilator lint_on UNSIGNED
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// verilator lint_off UNSIGNED
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if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop;
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// verilator lint_on UNSIGNED
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Second, warnings may be disabled using a configuration file with a lint_off
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command. This is useful when a script is suppressing warnings and the
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@ -2937,10 +2937,10 @@ were used, the simulator would have to copy large arrays every cycle. (In
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smaller loops, loop unrolling allows the delayed assignment to work, though
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it's a bit slower than a non-delayed assignment.) Here's an example
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always @ (posedge clk)
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always @ (posedge clk)
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if (~reset_l) begin
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for (i=0; i<`ARRAY_SIZE; i++) begin
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array[i] = 0; // Non-delayed for verilator
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array[i] = 0; // Non-delayed for verilator
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end
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This message is only seen on large or complicated loops because Verilator
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@ -3398,9 +3398,9 @@ A recommended style for unused nets is to put at the bottom of a file code
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similar to the following:
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wire _unused_ok = &{1'b0,
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sig_not_used_a,
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sig_not_used_yet_b, // To be fixed
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1'b0};
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sig_not_used_a,
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sig_not_used_yet_b, // To be fixed
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1'b0};
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The reduction AND and constant zeros mean the net will always be zero, so
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won't use simulation time. The redundant leading and trailing zeros avoid
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@ -3437,11 +3437,11 @@ unwidthed. Verilator considers zero to be any width needed.
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Concatenate leading zeros when doing arithmetic. In the statement
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wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0];
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wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0];
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||||
The best fix, which clarifies intent and will also make all tools happy is:
|
||||
|
||||
wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0,carry[0]};
|
||||
wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0,carry[0]};
|
||||
|
||||
Ignoring this warning will only suppress the lint check, it will simulate
|
||||
correctly.
|
||||
|
|
@ -3639,7 +3639,7 @@ trace file if you want all data to land in the same output file.
|
|||
tfp->open ("obj_dir/t_trace_ena_cc/simx.vcd");
|
||||
...
|
||||
sc_start(1);
|
||||
...
|
||||
...
|
||||
tfp->close();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue