Commentary
This commit is contained in:
Wilson Snyder
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Changes
20
Changes
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@ -5,12 +5,16 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.800***
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Application visible changes:
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** SystemPerl is no longer required for tracing.
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Applications must use VerilatedVcdC class in place of SpTraceVcdC.
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** SystemVerilog 1800-2009 is now the default language.
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Thus "global" etc are now keywords. See the --language option.
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New features:
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** Support SystemVerilog types "byte", "chandle", "int", "longint",
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"shortint", "time", "var" and "void" in variables and functions.
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@ -35,7 +39,10 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Support 1800-2009 define defaults and `undefineall.
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*** Add VARHIDDEN warning when signal name hides module name.
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*** Add -CFLAGS, -LDFLAGS, <file>.a, <file>.o, and <file>.so options.
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*** Speed compiles by avoiding including the STL iostream header.
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Application programs may need to include it themselves to avoid errors.
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*** Add experimental clock domain crossing checks.
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@ -43,10 +50,7 @@ indicates the contributor was also the author of the fix; Thanks!
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*** Add experimental config files to filter warnings outside of the source.
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*** Add -CFLAGS, -LDFLAGS, <file>.a, <file>.o, and <file>.so options.
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*** Speed compiles by avoiding including the STL iostream header.
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Application programs may need to include it themselves to avoid errors.
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*** Add VARHIDDEN warning when signal name hides module name.
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**** Support optional cell parenthesis, bug179. [by Byron Bradley]
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@ -60,11 +64,11 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Add -Wno-MODDUP option to allow duplicate modules.
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**** Fix creating implicit variables for expressions, bug196. [Byron Bradley]
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Bug fixes:
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**** Fix duplicate implicit variables under generates, bug201. [Byron Bradley]
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**** Fix implicit variable issues, bug196, bug201. [Byron Bradley]
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**** Fix for variable typing, bug205. [by Byron Bradley]
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**** Fix 'for' variable typing, bug205. [by Byron Bradley]
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**** Fix tracing with --pins-bv 1, bug195. [Michael S]
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@ -159,7 +159,7 @@ Verilator - Convert Verilog code to C++/SystemC
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verilator --cc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
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verilator --sc [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
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verilator --sp [options] [top_level.v] [opt_c_files.cpp/c/cc/a/o/so]
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verilator --lint-only ...
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verilator --lint-only [top_level.v]...
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=head1 DESCRIPTION
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@ -184,6 +184,7 @@ The resulting executable will perform the actual simulation.
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To get started, jump down to "EXAMPLE C++ EXECUTION".
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=head1 ARGUMENT SUMMARY
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This is a short summary of the arguments to Verilator. See the detailed
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@ -267,6 +268,7 @@ descriptions in the next sections for more information.
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-x-assign <mode> Initially assign Xs to this value
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-y <dir> Directory to search for modules
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=head1 ARGUMENTS
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=over 4
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@ -838,6 +840,7 @@ compatibility.
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=back
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=head1 EXAMPLE C++ EXECUTION
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We'll compile this example into C++.
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@ -895,6 +898,7 @@ Really, you're better off writing a Makefile to do all this for you. Then,
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when your source changes it will automatically run all of these steps. See
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the test_c directory in the distribution for an example.
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=head1 EXAMPLE SYSTEMC EXECUTION
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This is an example similar to the above, but using SystemPerl.
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@ -965,6 +969,7 @@ Really, you're better off using a Makefile to do all this for you. Then,
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when your source changes it will automatically run all of these steps. See
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the test_sp directory in the distribution for an example.
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=head1 BENCHMARKING & OPTIMIZATION
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For best performance, run Verilator with the "-O3 -x-assign=fast
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@ -1019,6 +1024,7 @@ Verilog line numbers on which most of the time is being spent.
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When done, please let the author know the results. I like to keep tabs on
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how Verilator compares, and may be able to suggest additional improvements.
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=head1 FILES
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All output files are placed in the output directory name specified with the
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@ -1068,6 +1074,7 @@ After running Make, the C++ compiler should produce the following:
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{prefix}__ALL.a // Library of all Verilated objects
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{prefix}{misc}.o // Intermediate objects
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=head1 ENVIRONMENT
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=over 4
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@ -1139,6 +1146,7 @@ Verilator was compiled).
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=back
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=head1 CONNECTING TO C++
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Verilator creates a .h and .cpp file for the top level module and all
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@ -1194,6 +1202,7 @@ You call the eval() method to evaluate the model. When the simulation is
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complete call the final() method to wrap up any SystemVerilog final blocks,
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and complete any assertions.
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=head1 CONNECTING TO SYSTEMC
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Verilator will convert the top level module to a SC_MODULE. This module
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@ -1209,6 +1218,7 @@ Lower modules are not pure SystemC code. This is a feature, as using the
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SystemC pin interconnect scheme everywhere would reduce performance by an
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order of magnitude.
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=head1 DIRECT PROGRAMMING INTERFACE (DPI)
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Verilator supports SystemVerilog Direct Programming Interface import and
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@ -1302,6 +1312,7 @@ definitions.
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Instead of DPI exporting, there's also Verilator public functions, which
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are slightly faster, but less compatible.
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=head1 CROSS COMPILATION
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Verilator supports cross-compiling Verilated code. This is generally used
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@ -1351,6 +1362,7 @@ For larger designs you'll want to automate this using makefiles, which pull
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the names of the .cpp files to compile in from the make variables generated
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in obj_dir/Vour_classes.mk.
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=head1 CONFIGURATION FILES
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In addition to the command line, warnings and other features may be
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@ -1395,6 +1407,7 @@ if ommitted).
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=back
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=head1 LANGUAGE STANDARD SUPPORT
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=head2 Verilog 2001 (IEEE 1364-2001) Support
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@ -1415,11 +1428,12 @@ Verilator currently has some support for SystemVerilog synthesis
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constructs. As SystemVerilog features enter common usage they are added;
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please file a bug if a feature you need is missing.
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Verilator supports ==? and !=? operators, $bits, $countones, $error,
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$fatal, $info, $isunknown, $onehot, $onehot0, $unit, $warning, always_comb,
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always_ff, always_latch, bit, byte, chandle, do-while, export, final,
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import, int, logic, longint, package, program, shortint, time, var, void,
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priority case/if, and unique case/if.
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Verilator supports ==? and !=? operators, ++ and -- in some contexts,
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$bits, $countones, $error, $fatal, $info, $isunknown, $onehot, $onehot0,
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$unit, $warning, always_comb, always_ff, always_latch, bit, byte, chandle,
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do-while, enum, export, final, import, int, logic, longint, package,
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program, shortint, time, typedef, var, void, priority case/if, and unique
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case/if.
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It also supports .name and .* interconnection.
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@ -1432,6 +1446,10 @@ Verilator implements a full SystemVerilog 2009 preprocessor, including
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function call-like preprocessor defines, default define arguments,
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`__FILE__, `__LINE__ and `undefineall.
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Verilator currently has some support for SystemVerilog 2009 synthesis
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constructs. As SystemVerilog features enter common usage they are added;
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please file a bug if a feature you need is missing.
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=head2 Sugar/PSL Support
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Most future work is being directed towards improving SystemVerilog
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@ -1475,6 +1493,7 @@ Verilator likewise also asserts any "unique" or "priority" SystemVerilog
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keywords on case statements. However, "unique if" and "priority if" are
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currently simply ignored.
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=head1 LANGUAGE EXTENSIONS
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The following additional constructs are the extensions Verilator supports
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@ -1785,6 +1804,7 @@ Re-enable waveform tracing for all future signals that are declared.
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=back
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=head1 LANGUAGE LIMITATIONS
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There are some limitations and lack of features relative to a commercial
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@ -2079,6 +2099,7 @@ when displaying all times, model wide.
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=back
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=head1 ERRORS AND WARNINGS
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Warnings may be disabled in two ways. First, when the warning is
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@ -2525,6 +2546,7 @@ program above:
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=back
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=head1 FAQ/FREQUENTLY ASKED QUESTIONS
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=over 4
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@ -2848,6 +2870,7 @@ SystemC module *may* be faster.)
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=back
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=head1 BUGS
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First, check the the coding limitations section.
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@ -2875,6 +2898,7 @@ L<http://www.veripool.org/verilator>. The bug will become publicly
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visible; if this is unacceptable, mail the bug report to
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C<wsnyder@wsnyder.org>.
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=head1 HISTORY
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Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group
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as the need arises. Verilator is now about 3x faster than in 2002, and is
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faster than many popular commercial simulators.
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=head1 CONTRIBUTORS
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Many people have provided ideas and other assistance with Verilator.
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@ -2942,6 +2967,7 @@ Xiaoliang.
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Thanks all.
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=head1 DISTRIBUTION
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The latest version is available from L<http://www.veripool.org/>.
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@ -2963,7 +2989,7 @@ Major concepts by Paul Wasson and Duane Galbi.
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L<verilator_profcfunc>, L<systemperl>, L<vcoverage>, L<make>
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And verilator_internals.txt in the distribution.
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And internals.txt in the distribution.
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=cut
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15
readme.pod
15
readme.pod
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@ -45,10 +45,10 @@ Verilator is developed and has primary testing on:
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SuSE 11.1 AMD64 i686-linux-2.6.27, GCC 4.3.2
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Versions have also built on Redhat Linux, Windows under Cygwin, Macs, HPUX
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and Solaris. It should run with minor porting on any Linix-ish platform.
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Verilator also works on Windows under MinGW (gcc -mno-cygwin). Verilated
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output (not Verilator itself) compiles under MSVC++ 2008.
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Versions have also built on Redhat Linux, Macs OS-X, HPUX and Solaris. It
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should run with minor porting on any Linix-ish platform. Verilator also
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works on Windows under Cygwin, and Windows under MinGW (gcc -mno-cygwin).
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Verilated output (not Verilator itself) compiles under MSVC++ 2008.
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=head1 INSTALLATION
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@ -164,11 +164,11 @@ or reading verilator.txt in the same directory as this README.
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=head1 DIRECTORY STRUCTURE
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The directories in the kit de-taring are as follows:
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The directories in the kit after de-taring are as follows:
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bin/verilator => Compiler Wrapper invoked on user Verilog code
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bin/verilator => Compiler Wrapper invoked to Verilate code
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include/ => Files that should be in your -I compiler path
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include/verilated.cpp => Global routines to link into your simulator
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include/verilated*.cpp => Global routines to link into your simulator
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include/verilated.h => Global headers
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include/verilated.v => Stub defines for linting
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include/verilated.mk => Common makefile
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@ -184,4 +184,3 @@ The directories in the kit de-taring are as follows:
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=head1 LIMITATIONS
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See verilator.txt (or execute C<bin/verilator --help>) for limitations.
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