Commentary

bin/verilator

@@ -227,7 +227,7 @@ __END__
 
 =head1 NAME
 
-Verilator - Convert Verilog code to C++/SystemC
+Verilator - Translate and simulate SystemVerilog code using C++/SystemC
 
 =head1 SYNOPSIS
 
@@ -241,7 +241,7 @@ Verilator - Convert Verilog code to C++/SystemC
 
 Verilator converts synthesizable (generally not behavioral) Verilog code,
 plus some Synthesis, SystemVerilog and a small subset of Verilog AMS into
-C++ or SystemC code.  It is not a complete simulator, but a compiler.
+C++ or SystemC code.  It is not a traditional simulator, but a compiler.
 
 Verilator is invoked with parameters similar to GCC, Cadence
 Verilog-XL/NC-Verilog, or Synopsys's VCS.  It reads the specified Verilog
@@ -3897,7 +3897,7 @@ output from a sub-module.)  While legal in Verilog, implicit declarations
 only work for single bit wide signals (not buses), do not allow using a
 signal before it is implicitly declared by a cell, and can lead to dangling
 nets.  A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
-Emacs, available from L<http://www.veripool.org/>
+Emacs, available from L<https://www.veripool.org/verilog-mode>
 
 Ignoring this warning will only suppress the lint check, it will simulate
 correctly.

docs/internals.adoc

@@ -103,7 +103,7 @@ the pass.
 A number of passes use graph algorithms, and the class `V3Graph` is
 provided to represent those graphs. Graphs are directed, and algorithms are
 provided to manipulate the graphs and to output them in
-http://www.graphviz.org/[GraphViz] dot format. `V3Graph.h` provides
+http://www.graphviz.org[GraphViz] dot format. `V3Graph.h` provides
 documentation of this class.
 
 ==== `V3GraphVertex`
@@ -431,7 +431,7 @@ into `V3Const__gen.cpp`.
 Verilator uses the "Visitor" design pattern to implement its refinement and
 optimization passes. This allows separation of the pass algorithm from the
 AST on which it operates. Wikipedia provides an introduction to the concept
-at http://en.wikipedia.org/wiki/Visitor_pattern.
+at https://en.wikipedia.org/wiki/Visitor_pattern.
 
 As noted above, all visitors are derived classes of `AstNVisitor`. All
 derived classes of `AstNode` implement the `accept` method, which takes as
@@ -744,7 +744,7 @@ into the obj_dir, .tree and .dot files.
 === .dot Output
 
 Dot files are dumps of internal graphs in
-http://www.graphviz.org/[Graphviz] dot format.  When a dot file is dumped,
+http://www.graphviz.org[Graphviz] dot format.  When a dot file is dumped,
 Verilator will also print a line on stdout that can be used to format the
 output, for example:
 
@@ -753,9 +753,9 @@ output, for example:
 You can then print a.ps.  You may prefer gif format, which doesn't get
 scaled so can be more useful with large graphs.
 
-For dynamic graph viewing consider ZGRViewer
-http://zvtm.sourceforge.net/zgrviewer.html.  If you know of better
-viewers let us know; ZGRViewer isn't great for large graphs.
+For dynamic graph viewing consider
+http://zvtm.sourceforge.net/zgrviewer.html[ZGRViewer].  If you know of
+better viewers let us know; ZGRViewer isn't great for large graphs.
 
 === .tree Output
 

test_regress/t/t_debug_fatalsrc_bad.pl

@@ -14,7 +14,7 @@ compile(
     fails => $Self->{vlt_all},
     expect =>
 '%Error: Internal Error: .*: --debug-fatal-src
-.* See the manual and http://www.veripool.org/verilator for more assistance.
+.* See the manual and .*
 %Error: Command Failed.*',
     );
 

test_regress/t/t_debug_fatalsrc_bt_bad.pl

@@ -15,7 +15,7 @@ lint(
     fails => 1,
     expect =>
 '%Error: Internal Error: .*: --debug-fatal-src
-.*See the manual and http://www.veripool.org/verilator for more assistance.
+.*See the manual and .*
 .*in V3Options::.*
 .*%Error: Command Failed.*',
     );

test_regress/t/t_dpi_accessors.v

@@ -8,7 +8,7 @@
 // This test exercises the use of DPI to access signals and registers in a
 // module hierarchy in a uniform fashion. See the discussion at
 //
-// http://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables
+// https://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables
 //
 // We need to test read and write access to:
 // - scalars

test_regress/t/t_func_under2.v

@@ -34,7 +34,6 @@ module t (/*AUTOARG*/
         func1(1'b1, dbg_addr) : val = 1;
         // This fails:
         // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement
-        // %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
         func2(1'b1, dbg_addr) : val = 2;
         default : val = 0;
       endcase