Commit Graph

73 Commits

Author SHA1 Message Date
Zachary Snow 73f831122f trim empty blocks; remove extra space in implicitly typed decls 2019-04-19 02:55:40 -04:00
Zachary Snow 9fcc8e3478 enum generate localparam values are also explicitly sized to avoid implicit cast/warnings 2019-04-19 01:02:07 -04:00
Zachary Snow a5ebb1e822 minor output cleanup 2019-04-18 23:32:49 -04:00
Zachary Snow e4cd8f4c09 simplify handles division and unsized decimal constants 2019-04-09 13:07:43 -04:00
Zachary Snow 9b51d7566b more expression simplification 2019-04-08 21:57:50 -04:00
Zachary Snow 9a38225b1d several major fixes surrounding packed arrays
- entirely new PackedArray conversion (always flattens)
- typedef and struct correctly order packed ranges when combining types
- Stmt LHS traversal no longer traverses nested statements to avoid double conversion
- Logic conversion applies to `initial` blocks`
- new and modified tests to cover these cases
2019-04-08 21:28:33 -04:00
Zachary Snow fb3d68e339 propper support for indexed part select addressing 2019-04-05 13:53:52 -04:00
Zachary Snow 011d88b544 PackedArray conversion supports arbitrary endianness 2019-04-04 19:40:19 -04:00
Zachary Snow 383754fa7a final major round of splitting and cleanup in the SystemVerilog module 2019-04-03 20:24:09 -04:00
Zachary Snow 6d0f7dd0a7 significantly stronger support, and proper handling of assertions 2019-04-03 19:08:30 -04:00
Zachary Snow e79c95c5f0 some cleanup throughout the SystemVerilog module 2019-04-03 13:45:43 -04:00
Zachary Snow c53b39319d added support and conversion handling of the $bits system function
This also entailed further fleshing out the expression traversal helper
to cover expressions in generate blocks, which could, of course, use
$bits.
2019-04-02 00:16:09 -04:00
Zachary Snow dc759dbb68 support for parameters of all types; fix named argument display bug 2019-03-31 14:25:09 -04:00
Zachary Snow c4f5718f51 support for binary xnor 2019-03-30 01:33:49 -04:00
Zachary Snow 2314f97a96 support for call args with unnamed and named arguments 2019-03-30 01:27:48 -04:00
Zachary Snow a432d75939 additional SystemVerilog language support
- unique0 and priority
- uniqueness on if statements
- preliminary discard-only parsing of assertions
- parameters with alias typenames
2019-03-30 00:47:42 -04:00
Zachary Snow 713fb8a658 support for more complex for loop components 2019-03-27 01:53:26 -04:00
Zachary Snow 1c1740f1e3 support for constant size casts 2019-03-27 00:34:17 -04:00
Zachary Snow 0352414e0f surprisingly non-disgusting addition of attribute instances to module items and statements 2019-03-26 01:54:16 -04:00
Zachary Snow ec06b2b97a support for basic event triggers 2019-03-25 19:06:54 -04:00
Zachary Snow ed816ac5dc fix silly bugs from AST reorg 2019-03-25 14:40:57 -04:00
Zachary Snow 8907ac861d split out Decl, LHS, and Stmt into separate AST modules 2019-03-25 13:29:35 -04:00
Zachary Snow 77f0d23d4b starting work to clean up and segment AST 2019-03-22 19:39:28 -04:00