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trim empty blocks; remove extra space in implicitly typed decls

This commit is contained in:
Zachary Snow 2019-04-19 02:55:40 -04:00
parent 8298e83f1e
commit 73f831122f
2 changed files with 2 additions and 1 deletions
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1
src/Convert/Traverse.hs
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@ -201,6 +201,7 @@ traverseSinglyNestedStmtsM :: Monad m => MapperM m Stmt -> MapperM m Stmt
traverseSinglyNestedStmtsM fullMapper = cs
where
cs (StmtAttr a stmt) = fullMapper stmt >>= return . StmtAttr a
cs (Block Nothing [] []) = return Null
cs (Block name decls stmts) =
mapM fullMapper stmts >>= return . Block name decls
cs (Case u kw expr cases def) = do

2
src/Language/SystemVerilog/AST/Decl.hs
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@ -26,7 +26,7 @@ instance Show Decl where
showList l _ = unlines' $ map show l
show (Parameter t x e) = printf "parameter %s%s = %s;" (showPad t) x (show e)
show (Localparam t x e) = printf "localparam %s%s = %s;" (showPad t) x (show e)
show (Variable d t x a me) = printf "%s%s %s%s%s;" (showPad d) (show t) x (showRanges a) (showAssignment me)
show (Variable d t x a me) = printf "%s%s%s%s%s;" (showPad d) (showPad t) x (showRanges a) (showAssignment me)
data Direction
= Input