support for basic event triggers

src/Convert/Traverse.hs

@@ -156,6 +156,7 @@ traverseNestedStmtsM mapper = fullMapper
         cs (Timing event stmt) = fullMapper stmt >>= return . Timing event
         cs (Return expr) = return $ Return expr
         cs (Subroutine f exprs) = return $ Subroutine f exprs
+        cs (Trigger x) = return $ Trigger x
         cs (Null) = return Null
 
 traverseStmtLHSsM :: Monad m => MapperM m LHS -> MapperM m Stmt
@@ -292,6 +293,7 @@ traverseExprsM mapper = moduleItemMapper
         mapM maybeExprMapper exprs >>= return . Subroutine f
     flatStmtMapper (Return expr) =
         exprMapper expr >>= return . Return
+    flatStmtMapper (Trigger x) = return $ Trigger x
     flatStmtMapper (Null) = return Null
 
     portBindingMapper (p, me) =

src/Language/SystemVerilog/AST/Stmt.hs

@@ -36,6 +36,7 @@ data Stmt
     | Timing  Timing Stmt
     | Return  Expr
     | Subroutine Identifier [Maybe Expr]
+    | Trigger Identifier
     | Null
     deriving Eq
 
@@ -67,6 +68,7 @@ instance Show Stmt where
     show (If a b c   ) = printf "if (%s) %s\nelse %s" (show a) (show b) (show c)
     show (Return e   ) = printf "return %s;" (show e)
     show (Timing t s ) = printf "%s %s" (show t) (show s)
+    show (Trigger x  ) = printf "-> %s;" x
     show (Null       ) = ";"
 
 data CaseKW

src/Language/SystemVerilog/Parser/Parse.y

@@ -541,6 +541,7 @@ StmtNonAsgn :: { Stmt }
   | "repeat" "(" Expr ")" Stmt                 { RepeatL $3 $5 }
   | "do"      Stmt "while" "(" Expr ")" ";"    { DoWhile $5 $2 }
   | "forever" Stmt                             { Forever $2 }
+  | "->" Identifier ";"                        { Trigger $2 }
 
 DeclsAndStmts :: { ([Decl], [Stmt]) }
   : DeclOrStmt DeclsAndStmts { combineDeclsAndStmts $1 $2 }