prjxray/fuzzers
litghost cc9e00da8f
Merge pull request #1174 from antmicro/zynq_ps7_clocks
Zynq PS7 clocks
2019-12-12 13:05:29 -08:00
..
000-init-db Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7 2019-12-12 17:20:53 +01:00
001-part-yaml Modified fuzzer 001 to include required features for Zynq parts. 2019-12-10 14:38:24 +01:00
005-tilegrid Add HCLK_[LR]_BOT_UTURN aliases. 2019-10-23 15:30:27 -07:00
007-timing fuzzers: 007: run make format 2019-07-23 14:50:10 +02:00
010-clb-lutinit
011-clb-ffconfig MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
012-clb-n5ffmux
013-clb-ncy0 MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
014-clb-ffsrcemux
015-clb-nffmux MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
016-clb-noutmux MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
017-clb-precyinit
018-clb-ram MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
019-clb-ndi1mux MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
025-bram-config
026-bram-data
027-bram36-config
028-fifo-config
029-bram-fifo-config
030-iob MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
031-cmt-mmcm
032-cmt-pll Added forcing of manual routing through "BB" pips to toggle more bits. 2019-11-15 12:14:06 +01:00
033-mon-xadc
034-cmt-pll-pips Fixed bit names formatting. 2019-11-14 16:09:44 +01:00
035-iob-ilogic Move ILOGIC and OLOGIC to IOI3 tiles for consistency. 2019-08-01 11:06:18 -07:00
035a-iob-idelay Add additional features for IDELAY. 2019-07-25 15:40:04 -07:00
036-iob-ologic run make format 2019-10-24 17:45:04 +02:00
037-iob-pips Filter ILOGIC1 version of IMUX22. 2019-08-09 15:57:52 -07:00
038-cfg Add background to script's purpose 2019-09-10 09:01:03 +02:00
039-hclk-config Skip weird tiles on Kintex7 fuzzing. 2019-08-08 12:14:35 -07:00
040-clk-hrow-config
041-clk-hrow-pips Ran make format 2019-12-12 09:31:59 +01:00
042-clk-bufg-config
043-clk-rebuf-pips
044-clk-bufg-pips 044-clk-bufg-pips: Exclude CK_BUFG_(BOT|TOP)_R_CK_MUXED from todo list 2019-06-25 18:52:00 +02:00
045-hclk-cmt-pips Split CCIO ACTIVE into two features. 2019-08-05 17:34:54 -07:00
046-clk-bufg-muxed-pips fuzzers: Add 046-clk-bufg-mixed-pips fuzzer 2019-06-25 18:52:00 +02:00
047-hclk-ioi-pips hclk-ioi: re-add IDELAYCTRL to exclude-RE 2019-10-31 12:04:43 +01:00
047a-hclk-idelayctrl-pips hlck-ioi: fix empty list bug in generate.tcl 2019-11-04 11:02:52 +01:00
048-int-piplist
049-int-imux-gfan
050-pip-seed 050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits 2019-06-17 14:55:18 +02:00
051-pip-imuxlout-bypalts
052-pip-clkin
053-pip-ctrlin
054-pip-fan-alt
055-pip-gnd
056-pip-rem
057-pip-bi
058-pip-hclk
059-pip-byp-bounce MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
060-bram-cascades
071-ppips Added dumping of PPIPs for Zynq PS7 tiles and interconnects. 2019-12-12 09:57:41 +01:00
072-ordered_wires
073-get_counts
074-dump_all MAKE - Format Trailing Whitespace 2019-10-26 10:04:52 +01:00
075-pins Modified fuzzer 075 to dump IO bank number for each pin. 2019-12-11 17:10:41 +01:00
100-dsp-mskpat FUZZER - DSP - Fixes Following Review 2019-11-02 11:43:12 +00:00
piplist
.gitignore
Makefile hclk-ioi: make 047a dependent on 47 to avoid race condition on piplist 2019-10-31 17:00:33 +01:00
clb.mk
clb_ext.mk Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 2019-07-10 15:06:58 +02:00
fuzzer.mk
int_create_empty_db.sh
int_generate.py Fix problem with falsely ignored PIPs 2019-06-27 08:01:01 +02:00
int_loop.mk
int_loop.sh
int_loop_check.py int_loop_check.py: Fix output formatting 2019-07-15 10:08:45 +02:00
int_maketodo.py Avoid failing on empty pip lists (which may occur). 2019-08-08 12:23:30 -07:00
pip_list.mk
pip_loop.mk
reseg.sh
run_fuzzer.py