ccb43370fa
005-tilegrid/util.py: format fix
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
f79aa011c1
005-tilegrid/generate_full.py: simplified assertion
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
9e6c62cb4c
005-tilegrid: created a util script
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There is some shared code between add_tdb.py and generate_full.py. To
solve this I have added a util script containing shared code.
Moreover, in the case a block has to be overwritten, the add_tile_bits
function now checks if the two version of the block contain the same
information. If this does not happend the script fails.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
67dad57a8e
005-tilegrid: format fix
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
5f59221f0b
005-tilegrid/generate_full: propagating INT
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I have added a way to propagate INT_L base addresses which do not have
an adjacent block
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-14 12:58:24 +01:00
0906e734b9
Fix PR #507 : Merged last run in the pool
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Signed-off-by: Mehdi Khairy <mehdi.khairy@more-magic.org>
2019-01-12 12:27:35 +01:00
0168578b5a
Merge remote-tracking branch 'upstream/master'
2019-01-12 03:30:23 +01:00
e359ab6f39
Fixing Fuzzer 072: supporting all pips count
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Signed-off-by: Mehdi Khairy <mehdi.khairy@more-magic.org>
2019-01-12 03:02:42 +01:00
d007828d5c
Merge pull request #506 from mithro/remove-asserts
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Remove asserts checking only artix7 / kintex7.
2019-01-12 01:42:39 +01:00
f10f9141fb
Merge pull request #489 from natsfr/master
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Fixing Bug #171 and #465
2019-01-11 15:24:40 -08:00
8d87f2ff95
Remove asserts checking only artix7 / kintex7.
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Lets see how they explode on Zynq.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
2019-01-11 15:12:23 -08:00
84645e8793
PR #489 Fix 072 Fuzzer by splitting jobs
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Signed-off-by: Mehdi Khairy <mehdi.khairy@more-magic.org>
2019-01-11 23:23:17 +01:00
d735f0e2b2
Merge pull request #505 from antmicro/052-fix
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fuzzers: 52: retry routing if it fails
2019-01-11 19:43:33 +01:00
4c4e17f380
Merge pull request #502 from mcmasterg/pip-quick
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pip (especially imuxlout) quick
2019-01-11 19:18:22 +01:00
9845739386
fuzzers: 52: retry routing if it fails
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Sometimes randomly selected scr and dst tiles lead
to unroutable situation. This can be mitigated by
repeating the failed attempt with a new src and dst
tiles.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-11 19:13:05 +01:00
d8a5160fa0
clb-ndi1mux: README update
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 18:56:40 +01:00
5f8c46a795
clb: clean up README files
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 18:52:42 +01:00
f4f2a79cf9
ffconfig readme: cleanup
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 16:06:49 +01:00
09971f8bd4
ffconfig readme: import wiki
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 16:06:23 +01:00
591c3be2ac
pip-imuxlout: QUICK tcl
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 11:42:57 +01:00
f4edf4a198
piplist.tcl: break into functions
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 11:37:54 +01:00
c9ced5ea47
fuzzers: int: create empty DB if it doesn't exist
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-11 10:46:54 +01:00
3585d98b99
int_loop: QUICK reduce TODO N
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-11 10:45:59 +01:00
144a0edc8c
Bug #456 : fix regression in CLB bit CARRY4.ACY0
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-01-11 08:13:54 +01:00
19a93121a6
Bug #171 : Fixing build directory for Fuzzers 074
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Signed-off-by: Mehdi Khairy <mehdi.khairy@more-magic.org>
2019-01-10 23:57:35 +01:00
9fdd4fab86
timfuz: update readme
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-10 16:01:04 +01:00
dff1402dfa
Merge pull request #474 from antmicro/05x-fuzzers-rework
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05x fuzzers rework
2019-01-10 15:03:00 +01:00
6c6e90db84
fuzzers: 05x: do not use symbolic link to int_generate.py
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-10 14:36:36 +01:00
42529b7287
fuzzers: 51: calculate 50 DB entries in each step
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-10 12:46:41 +01:00
65f5ddb030
005-tilegrid/add_tdb.py: use floor divide
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 12:04:34 +01:00
b4ca31cd1e
005-tilegrid/add_tdb.py: added frame check
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This solves issue #481 . add_tdb.py now checks if all the bits in a same
tag have the same base address and, if that is the case, the first of
them is selected
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 11:43:53 +01:00
08aaa19551
Merge pull request #462 from antmicro/ps7
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PS7 INT on Zynq
2019-01-10 10:47:42 +01:00
3738801ca3
005-tilegrid: removing unneeded comments
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 10:22:36 +01:00
39693b7958
ps7_int: rename fuzzer ps7 --> ps7_int
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 10:02:08 +01:00
bd32e51a38
005-tilegrid/add_tdb.py: change ps7 --> ps7_int
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 10:01:32 +01:00
f8b5de960c
ps7_int/Makefile: change ps7 --> ps7_int
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-10 10:00:49 +01:00
e9a2489c36
Merge pull request #478 from litghost/add_ppips_for_bram
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Add ppips for bram
2019-01-10 09:32:02 +01:00
81fbb37153
bram config: DOX_REG, clean up
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-10 08:44:51 +01:00
150795d6d3
Add BRAM_INT_INTERFACE_* too.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-09 18:04:20 -08:00
55201c4d1e
Add ppip output for BRAM tiles.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-09 17:10:01 -08:00
bba4f339cc
tilegrid: fix multi regression
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-09 23:29:21 +01:00
a4b0c6f1de
fuzzers: refactor fuzzer 51
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The fuzzer is now todo files based. It is also using generic
generate.py script.
For now the fuzzer instantiates picorv and randluts besides
the logic under test. This is required for to deliver negative
examples to segmaker. Because of the size of the design this
fuzzer is taking really long to complete. We need to find a
smallest possible design that will be enough to generate the DB.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-09 23:16:22 +01:00
49d8a6c22c
fuzzers: 56: use generic generate.py
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-09 23:16:22 +01:00
bc48baa30d
fuzzers: add generic generate.py
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-09 23:16:19 +01:00
eb11da50e0
fuzzers: int_loop: do not mask errors
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-01-09 22:12:47 +01:00
7f6e6f1c8c
005-tilegrid/add_tdb.py: Changed frame and word params
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-09 19:07:40 +01:00
3ec9dd58af
Merge branch 'master' into ps7
2019-01-09 18:52:28 +01:00
892b4fb5f7
fuzzaddr: optional dframe, dbit
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Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2019-01-09 18:45:37 +01:00
8bdf04a29d
005-tilegrid/add_tdb.py: Added ps7 tdb
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There is an hack to be fixed that selects only the first bit of the
tdb lines. It has to be corrected
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-09 18:14:23 +01:00
6691d2dcc8
ps7/top.py: updated top generator
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The top.py generates a param.csv file related to a specific tile. The
segdata_tilegrid.tdb related to ps7 now contains two different
addresses bound to a specific tile.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2019-01-09 16:31:28 +01:00
Alessandro Comodi
Mehdi Khairy
John McMaster
litghost
Tim 'mithro' Ansell
Karol Gugala
John McMaster
Tomasz Michalak