mirror of https://github.com/openXC7/prjxray.git
fuzzers: refactor fuzzer 51
The fuzzer is now todo files based. It is also using generic generate.py script. For now the fuzzer instantiates picorv and randluts besides the logic under test. This is required for to deliver negative examples to segmaker. Because of the size of the design this fuzzer is taking really long to complete. We need to find a smallest possible design that will be enough to generate the DB. Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala
parent
e6eb0db9f9
commit
a4b0c6f1de
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@ -1,68 +0,0 @@
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#!/usr/bin/env python3
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import re, os
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from prjxray.segmaker import Segmaker
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segmk = Segmaker("design.bits")
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tiledata = dict()
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pipdata = dict()
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ignpip = set()
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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_, pip = pip.split(".")
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {"pips": set(), "srcs": set(), "dsts": set()}
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if pip in pipdata:
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assert pipdata[pip] == (src, dst)
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else:
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pipdata[pip] = (src, dst)
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tiledata[tile]["pips"].add(pip)
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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if pnum == 1 or pdir == 0 or \
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re.match(r"^(L[HV]B?|G?CLK)(_L)?(_B)?[0-9]", src) or \
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re.match(r"^(L[HV]B?|G?CLK)(_L)?(_B)?[0-9]", dst) or \
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re.match(r"^(CTRL|GFAN)(_L)?[0-9]", dst):
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ignpip.add(pip)
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for tile, pips_srcs_dsts in tiledata.items():
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pips = pips_srcs_dsts["pips"]
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srcs = pips_srcs_dsts["srcs"]
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dsts = pips_srcs_dsts["dsts"]
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for pip, src_dst in pipdata.items():
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src, dst = src_dst
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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def bitfilter(frame_idx, bit_idx):
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assert os.getenv("XRAY_DATABASE") in ["artix7", "kintex7"]
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if frame_idx in [30, 31]:
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return False
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return True
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segmk.compile(bitfilter=bitfilter)
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segmk.write(allow_empty=True)
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@ -0,0 +1 @@
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../int_generate.py
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@ -3,10 +3,13 @@ source "$::env(XRAY_DIR)/utils/utils.tcl"
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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read_verilog $::env(FUZDIR)/picorv32.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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@ -14,6 +17,8 @@ resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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@ -21,7 +26,6 @@ route_design
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# write_checkpoint -force design.dcp
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set fp [open "../../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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@ -29,8 +33,8 @@ for {gets $fp line} {$line != ""} {gets $fp line} {
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}
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close $fp
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set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
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set int_l_tiles [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [filter [pblock_tiles roi] {TYPE == INT_R}]]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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@ -51,18 +55,37 @@ for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set src_prefix [regsub {(.*/.).*} ${clb_src_pin} {\1}]
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set dst_prefix [regsub {(.*/.).*} ${clb_dst_pin} {\1}]
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if {$src_prefix == $dst_prefix} {
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set slice [get_sites -of_objects $clb_dst_pin]
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set lut [regsub {.*/} $src_prefix {}]6LUT
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set slice [get_sites -of_objects $clb_dst_pin]
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set src_slice [get_sites -of_objects $clb_src_pin]
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set lut [regsub {.*/} $src_prefix {}]6LUT
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set dff [regsub {.*/} $src_prefix {}]FF
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puts "=== $slice $lut ($clb_src_pin -> $clb_dst_pin)"
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
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set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
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set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
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# some source wires may be FF outputs, in such cases
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# we need to place and route an FF
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set src_type [regsub {.*/*(.$)} $clb_src_pin {\1}]
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if { $src_type == "Q" } {
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set mydff [create_cell -reference FDCE mydff_$idx]
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set_property -dict "LOC $src_slice BEL $dff" $mydff
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connect_net -net $mynet -objects "$mylut/I0 $mydff/Q"
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} else {
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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}
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set route_list "$tile/$src_wire $tile/$dst_wire"
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puts "route_via $mynet $route_list"
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set rc [route_via $mynet $route_list 0]
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if {$rc != 0} {
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puts "SUCCESS"
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} else {
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puts "Manual routing failed"
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# TODO: We should probably fail here
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}
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}
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proc write_txtdata {filename} {
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File diff suppressed because it is too large
Load Diff
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@ -1,3 +1,93 @@
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module top (input i, output o);
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assign o = i;
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`include "setseed.vh"
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module top(input clk, din, stb, output dout);
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reg [41:0] din_bits;
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wire [78:0] dout_bits;
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reg [41:0] din_shr;
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reg [78:0] dout_shr;
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always @(posedge clk) begin
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if (stb) begin
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din_bits <= din_shr;
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dout_shr <= dout_bits;
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end else begin
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din_shr <= {din_shr, din};
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dout_shr <= {dout_shr, din_shr[41]};
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end
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end
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assign dout = dout_shr[78];
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roi roi (
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.clk(clk),
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.din_bits(din_bits),
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.dout_bits(dout_bits)
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);
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endmodule
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module roi(input clk, input [41:0] din_bits, output [78:0] dout_bits);
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picorv32 picorv32 (
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.clk(clk),
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.resetn(din_bits[0]),
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.mem_valid(dout_bits[0]),
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.mem_instr(dout_bits[1]),
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.mem_ready(din_bits[1]),
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.mem_addr(dout_bits[33:2]),
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.mem_wdata(dout_bits[66:34]),
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.mem_wstrb(dout_bits[70:67]),
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.mem_rdata(din_bits[33:2])
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);
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randluts randluts (
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.din(din_bits[41:34]),
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.dout(dout_bits[78:71])
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);
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endmodule
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module randluts(input [7:0] din, output [7:0] dout);
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localparam integer N =
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`SEED % 3 == 2 ? 250 :
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`SEED % 3 == 1 ? 100 : 10;
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function [31:0] xorshift32(input [31:0] xorin);
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begin
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xorshift32 = xorin;
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xorshift32 = xorshift32 ^ (xorshift32 << 13);
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xorshift32 = xorshift32 ^ (xorshift32 >> 17);
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xorshift32 = xorshift32 ^ (xorshift32 << 5);
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end
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endfunction
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function [63:0] lutinit(input [7:0] a, b);
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begin
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lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
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lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
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end
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endfunction
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wire [(N+1)*8-1:0] nets;
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assign nets[7:0] = din;
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assign dout = nets[(N+1)*8-1:N*8];
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genvar i, j;
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generate
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for (i = 0; i < N; i = i+1) begin:is
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for (j = 0; j < 8; j = j+1) begin:js
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localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
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LUT6 #(
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.INIT(lutinit(i, j))
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) lut (
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.I0(nets[8*i+(k+0)%8]),
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.I1(nets[8*i+(k+1)%8]),
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.I2(nets[8*i+(k+2)%8]),
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.I3(nets[8*i+(k+3)%8]),
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.I4(nets[8*i+(k+4)%8]),
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.I5(nets[8*i+(k+5)%8]),
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.O(nets[8*i+8+j])
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);
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end
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end
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endgenerate
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endmodule
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