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Merge pull request #502 from mcmasterg/pip-quick 

pip (especially imuxlout) quick
This commit is contained in:
John McMaster 2019-01-11 19:18:22 +01:00 committed by GitHub
parent 996d3564e0 591c3be2ac
commit 4c4e17f380
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 62 additions and 40 deletions
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15
fuzzers/051-pip-imuxlout/generate.tcl
View File

@ -88,13 +88,13 @@ for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
}
}
proc write_txtdata {filename} {
proc write_txtdata {filename tiles} {
puts "Writing $filename."
set fp [open $filename w]
set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
if {$all_pips != {}} {
puts "Dumping pips."
foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
foreach tile $tiles {
foreach pip [filter $all_pips "TILE == $tile"] {
set src_wire [get_wires -uphill -of_objects $pip]
set dst_wire [get_wires -downhill -of_objects $pip]
@ -110,4 +110,13 @@ proc write_txtdata {filename} {
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt
# quick: only analyze manually routed tiles, skipping riscv and such
if {[info exists ::env(QUICK) ] && "$::env(QUICK)" == "Y"} {
set lim [expr [llength $todo_lines] - 1]
set tiles [concat [lrange $int_l_tiles 0 $lim] [lrange $int_r_tiles 0 $lim]]
} else {
set tiles [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]]
}
write_txtdata design.txt $tiles

5
fuzzers/int_loop.mk
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@ -1,6 +1,8 @@
TODO_N ?= 10
# Number of spcimens
ifeq ($(QUICK),Y)
N ?= 1
N = 1
TODO_N = 3
SEGMATCH_FLAGS=
else
# Should be at least the -m value
@ -11,7 +13,6 @@ endif
# Driven by int_loop.sh
ITER ?= 1
MAKETODO_FLAGS ?=
TODO_N ?= 10
PIP_TYPE?=pips_int
PIPLIST_TCL?=$(XRAY_DIR)/fuzzers/piplist.tcl

82
fuzzers/piplist.tcl
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@ -1,39 +1,51 @@
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog $::env(XRAY_DIR)/fuzzers/piplist.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force piplist.dcp
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc print_tile_pips {tile_type filename} {
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
puts "Dumping PIPs for tile $tile ($tile_type) to $filename"
set fp [open $filename w]
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
set src [get_wires -uphill -of_objects $pip]
set dst [get_wires -downhill -of_objects $pip]
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
}
}
close $fp
proc build_project {} {
create_project -force -part $::env(XRAY_PART) piplist piplist
read_verilog $::env(XRAY_DIR)/fuzzers/piplist.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force piplist.dcp
}
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt
puts "Done"
proc dump_pips {} {
proc print_tile_pips {tile_type filename} {
set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
puts "Dumping PIPs for tile $tile ($tile_type) to $filename"
set fp [open $filename w]
foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
set src [get_wires -uphill -of_objects $pip]
set dst [get_wires -downhill -of_objects $pip]
if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
}
}
close $fp
}
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt
puts "Done"
}
proc run {} {
build_project
dump_pips
}
run