Merge remote-tracking branch 'upstream/master'

.github/update-contributing.py

@@ -29,7 +29,7 @@ contrib.append(
 ----
 
 This file is generated from [README.md](README.md), please edit that file then
-run the `./.update-contributing.py`.
+run the `./.github/update-contributing.py`.
 
 """)
 

.travis.yml

@@ -1,42 +1,33 @@
-matrix:
+os: linux
+dist: trusty
+language: python
+python: 3.6
+addons:
+  apt:
+    sources:
+      - ubuntu-toolchain-r-test
+      - llvm-toolchain-trusty-5.0
+    packages:
+      - clang-format-5.0
+      - g++-6
+
+install:
+  - export CC=gcc-6
+  - export CXX=g++-6
+  - make env
+
+
+jobs:
   include:
-    # Job 1) Test C++ w/ GCC
-    - os: linux
-      dist: trusty
-      language: cpp
-      addons:
-        apt:
-          sources:
-            - ubuntu-toolchain-r-test
-          packages:
-            - g++-6
+    # State 1 - Tests
+    - stage: "Tests"
+      name: "C++ Tests"
+      script: make test-cpp
+
+    - name: "Python Tests"
+      script: make test-py
+
+    - name: "Format"
       script:
-        - export CC=gcc-6
-        - export CXX=g++-6
-        - mkdir -p build
-        - pushd build
-        - cmake -DPRJXRAY_BUILD_TESTING=ON ..
-        - make -j 4
-        - ctest
-    # Job 2) Lint checks on Python and C++
-    - os: linux
-      dist: trusty
-      language: python
-      python: 3.6
-      addons:
-        apt:
-          sources:
-            - ubuntu-toolchain-r-test
-            - llvm-toolchain-trusty-5.0
-          packages:
-            - clang-format-5.0
-            - g++-6
-      install:
-        - export CC=gcc-6
-        - export CXX=g++-6
-        - pip install -r requirements.txt
-      script:
-        - export CC=gcc-6
-        - export CXX=g++-6
         - make format
-        - test $(git status --porcelain | wc -l) -eq 0 || { git diff; false; } 
+        - test $(git status --porcelain | wc -l) -eq 0 || { git diff; false; }

CONTRIBUTING.md

@@ -92,5 +92,5 @@ In addition to the above contribution guidelines, see the guide to
 ----
 
 This file is generated from [README.md](README.md), please edit that file then
-run the `./.update-contributing.py`.
+run the `./.github/update-contributing.py`.
 

Dockerfile

@@ -4,8 +4,9 @@ FROM ${DEV_ENV_IMAGE} AS db_builder
 ARG NUM_PARALLEL_JOBS=1
 
 COPY . /source
-RUN cd /source && make -j${NUM_PARALLEL_JOBS} --output-sync=target --warn-undefined-variables database
-RUN find /source/database -mindepth 1 -maxdepth 1 -type d -exec /source/htmlgen/htmlgen.py --settings={}/settings.sh --output=/output/html \;
+RUN cd /source && make -j${NUM_PARALLEL_JOBS} --output-sync=target --warn-undefined-variables build && make env
+RUN bash -c ". /source/database/artix7/settings.sh; cd /source/fuzzers && make --output-sync=target --warn-undefined-variables"
+#RUN find /source/database -mindepth 1 -maxdepth 1 -type d -exec /source/htmlgen/htmlgen.py --settings={}/settings.sh --output=/output/html \;
 RUN mkdir -p /output/raw && find /source/database -mindepth 1 -maxdepth 1 -type d -exec cp -R {} /output/raw \;
 
 FROM amd64/nginx:alpine

Makefile

@@ -1,14 +1,13 @@
-CLANG_FORMAT ?= clang-format-5.0
-PYTHON_FORMAT ?= yapf
-TCL_FORMAT ?= utils//tcl-reformat.sh
-
-.PHONY: database format clean env
+ALL_EXCLUDE = third_party .git env build
 
+# Tools + Environment
 IN_ENV = if [ -e env/bin/activate ]; then . env/bin/activate; fi;
 env:
 	virtualenv --python=python3 --system-site-packages env
 	$(IN_ENV) pip install -r requirements.txt
+	$(IN_ENV) pip install -r docs/requirements.txt
 	ln -sf $(PWD)/prjxray env/lib/python3.*/site-packages/
+	ln -sf $(PWD)/third_party/fasm/fasm.py env/lib/python3.*/site-packages/
 	$(IN_ENV) python -c "import yaml" || (echo "Unable to find python-yaml" && exit 1)
 
 build:
@@ -16,16 +15,53 @@ build:
 	mkdir -p build
 	cd build; cmake ..; $(MAKE)
 
-database: build
-	$(MAKE) -C $@
+.PHONY: env build
 
-FORMAT_EXCLUDE = third_party .git env build
-FIND_EXCLUDE = $(foreach x,$(FORMAT_EXCLUDE),-and -not -path './$(x)/*')
-format:
-	find . -name \*.cc $(FIND_EXCLUDE) -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i
-	find . -name \*.h $(FIND_EXCLUDE) -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i
-	$(IN_ENV) find . -name \*.py $(FIND_EXCLUDE) -print0 | xargs -0 -P $$(nproc) yapf -p -i
-	find . -name \*.tcl $(FIND_EXCLUDE) -print0 | xargs -0 -P $$(nproc) -n 1 $(TCL_FORMAT)
+# Run tests of code.
+# ------------------------
+TEST_EXCLUDE = $(foreach x,$(ALL_EXCLUDE) fuzzers minitests experiments,--ignore $(x))
+
+test: test-py test-cpp
+	@true
+
+test-py:
+	$(IN_ENV) py.test $(TEST_EXCLUDE) --doctest-modules --junitxml=build/py_test_results.xml
+
+test-cpp:
+	mkdir -p build
+	cd build && cmake -DPRJXRAY_BUILD_TESTING=ON ..
+	cd build && $(MAKE) -s
+	cd build && ctest --no-compress-output -T Test -C RelWithDebInfo --output-on-failure
+
+.PHONY: test test-py test-cpp
+
+# Auto formatting of code.
+# ------------------------
+FORMAT_EXCLUDE = $(foreach x,$(ALL_EXCLUDE),-and -not -path './$(x)/*')
+
+CLANG_FORMAT ?= clang-format-5.0
+format-cpp:
+	find . -name \*.cc $(FORMAT_EXCLUDE) -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i
+	find . -name \*.h $(FORMAT_EXCLUDE) -print0 | xargs -0 -P $$(nproc) ${CLANG_FORMAT} -style=file -i
+
+format-docs:
+	./.github/update-contributing.py
+
+PYTHON_FORMAT ?= yapf
+format-py:
+	$(IN_ENV) find . -name \*.py $(FORMAT_EXCLUDE) -print0 | xargs -0 -P $$(nproc) yapf -p -i
+
+TCL_FORMAT ?= utils//tcl-reformat.sh
+format-tcl:
+	find . -name \*.tcl $(FORMAT_EXCLUDE) -print0 | xargs -0 -P $$(nproc) -n 1 $(TCL_FORMAT)
+
+format: format-cpp format-docs format-py format-tcl
+	@true
+
+.PHONY: format format-cpp format-py format-tcl
+
+# Project X-Ray database
+# ------------------------
 
 checkdb:
 	@for DB in database/*; do if [ -d $$DB ]; then \

cloudbuild.yaml

@@ -7,7 +7,7 @@ steps:
     - '--build-arg'
     - 'NUM_PARALLEL_JOBS=${_NUM_CPUS}'
     - '-t'
-    - '${_GCR_ZONE}/$PROJECT_ID/${_IMAGE_NAME}:${TAG_NAME}'
+    - '${_GCR_ZONE}/$PROJECT_ID/${_IMAGE_NAME}:${SHORT_SHA}'
     - '.'
 options:
   disk_size_gb: 1000
@@ -18,4 +18,4 @@ substitutions:
   _IMAGE_NAME: 'prjxray-db'
   _NUM_CPUS: '16'
 images:
-  - '${_GCR_ZONE}/$PROJECT_ID/${_IMAGE_NAME}:${TAG_NAME}'
+  - '${_GCR_ZONE}/$PROJECT_ID/${_IMAGE_NAME}:${SHORT_SHA}'

fuzzers/005-tilegrid/Makefile

@@ -1,5 +1,10 @@
 FUZDIR=$(shell pwd)
 BUILD_DIR=$(FUZDIR)/build
+TILEGRID_TDB_DEPENDENCIES=iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
+
+ifeq (${XRAY_DATABASE}, zynq7)
+TILEGRID_TDB_DEPENDENCIES += ps7_int/build/segbits_tilegrid.tdb
+endif
 
 database: build/tilegrid.json
 
@@ -22,7 +27,7 @@ build/bram/deltas:
 build/iob/deltas:
 	bash generate.sh build/iob iob
 
-build/tilegrid_tdb.json: add_tdb.py iob/build/segbits_tilegrid.tdb mmcm/build/segbits_tilegrid.tdb pll/build/segbits_tilegrid.tdb
+build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
 	python3 add_tdb.py --fn-in build/basicdb/tilegrid.json --fn-out build/tilegrid_tdb.json
 
 iob/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
@@ -34,6 +39,9 @@ mmcm/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 pll/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd pll && $(MAKE)
 
+ps7_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
+	cd ps7_int && $(MAKE)
+
 # FIXME: add monitor to ROI
 monitor/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
 	cd monitor && $(MAKE)
@@ -54,6 +62,7 @@ clean:
 	cd iob && $(MAKE) clean
 	cd mmcm && $(MAKE) clean
 	cd pll && $(MAKE) clean
+	cd ps7_int && $(MAKE) clean
 
 .PHONY: database pushdb clean run
 

fuzzers/005-tilegrid/add_tdb.py

@@ -52,16 +52,29 @@ def parse_addr(line):
     return frame, wordidx, bitidx
 
 
+def check_frames(frames):
+    baseaddr = set()
+    for frame in frames:
+        baseaddr.add(frame // 128)
+    assert len(baseaddr) == 1, "Multiple base addresses for the same tag"
+
+
 def load_db(fn):
     for l in open(fn, "r"):
         l = l.strip()
         # FIXME: add offset to name
         # IOB_X0Y101.DFRAME:27.DWORD:3.DBIT:3 00020027_003_03
         parts = l.split(' ')
-        assert len(parts) == 2, "Unresolved bit: %s" % l
-        tagstr, addrstr = parts
+        tagstr = parts[0]
+        addrlist = parts[1:]
+        frames = list()
+        for addrstr in addrlist:
+            frame, wordidx, bitidx = parse_addr(addrstr)
+            frames.append(frame)
+        check_frames(frames)
+        # Take the first address in the list
+        frame, wordidx, bitidx = parse_addr(addrlist[0])
 
-        frame, wordidx, bitidx = parse_addr(addrstr)
         bitidx_up = False
 
         tparts = tagstr.split('.')
@@ -107,6 +120,8 @@ def run(fn_in, fn_out, verbose=False):
     if os.path.exists("monitor/build/segbits_tilegrid.tdb"):
         # FIXME: height
         tdb_fns.append(("monitor/build/segbits_tilegrid.tdb", 30, 101))
+    if os.path.exists("ps7_int/build/segbits_tilegrid.tdb"):
+        tdb_fns.append(("ps7_int/build/segbits_tilegrid.tdb", 36, 2))
 
     for (tdb_fn, frames, words) in tdb_fns:
         for (tile, frame, wordidx) in load_db(tdb_fn):

fuzzers/005-tilegrid/fuzzaddr/generate.py

@@ -3,8 +3,24 @@
 from prjxray import bitsmaker
 
 
-def run(bits_fn, design_fn, fnout, oneval, dframe, dword, dbit, verbose=False):
-    metastr = "DFRAME:%02x.DWORD:%u.DBIT:%u" % (dframe, dword, dbit)
+def run(
+        bits_fn,
+        design_fn,
+        fnout,
+        oneval,
+        dframe,
+        dword,
+        dbit,
+        multi=False,
+        verbose=False):
+    # mimicing tag names, wasn't sure if it would break things otherwise
+    metastr = "DWORD:%u" % dword
+    if dbit is not None:
+        metastr += ".DBIT:%u" % dbit
+    if dframe is not None:
+        metastr += ".DFRAME:%02x" % dframe
+    if multi:
+        metastr += ".MULTI"
 
     tags = dict()
     f = open(design_fn, 'r')
@@ -28,11 +44,18 @@ def main():
     parser.add_argument("--verbose", action="store_true", help="")
     parser.add_argument("--design", default="design.csv", help="")
     parser.add_argument("--fnout", default="/dev/stdout", help="")
-    parser.add_argument("--oneval", required=True, help="")
+    parser.add_argument(
+        "--oneval",
+        required=True,
+        help="Parameter value that correspodns to a set bit")
+    #
+    parser.add_argument(
+        "--multi", action="store_true", help="Are multiple bits expected?")
     parser.add_argument(
         "--dframe",
         type=str,
-        required=True,
+        required=False,
+        default="",
         help="Reference frame delta (base 16)")
     parser.add_argument(
         "--dword",
@@ -42,7 +65,8 @@ def main():
     parser.add_argument(
         "--dbit",
         type=str,
-        required=True,
+        required=False,
+        default="",
         help="Reference bit delta (base 10)")
     args = parser.parse_args()
 
@@ -51,9 +75,10 @@ def main():
         args.design,
         args.fnout,
         args.oneval,
-        int(args.dframe, 16),
+        None if args.dframe == "" else int(args.dframe, 16),
         int(args.dword, 10),
-        int(args.dbit, 10),
+        None if args.dbit == "" else int(args.dbit, 10),
+        multi=args.multi,
         verbose=args.verbose)
 
 

fuzzers/005-tilegrid/ps7_int/Makefile

@@ -0,0 +1,3 @@
+N ?= 2
+GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 14 --dword 0 --dbit 17"
+include ../fuzzaddr/common.mk

fuzzers/005-tilegrid/ps7_int/generate.tcl

@@ -0,0 +1,32 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+    # Disable MMCM frequency etc sanity checks
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/005-tilegrid/ps7_int/top.py

@@ -0,0 +1,682 @@
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+
+
+def write_params(params):
+    pinstr = 'tile,val\n'
+    for tile, (val) in sorted(params.items()):
+        pinstr += '%s,%s\n' % (tile, val)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print(
+        '''
+module top(input clk, stb, di, output do);
+    localparam integer DIN_N = 8;
+    localparam integer DOUT_N = 8;
+
+    reg [DIN_N-1:0] din;
+    wire [DOUT_N-1:0] dout;
+
+    reg [DIN_N-1:0] din_shr;
+    reg [DOUT_N-1:0] dout_shr;
+
+    always @(posedge clk) begin
+        din_shr <= {din_shr, di};
+        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+        if (stb) begin
+            din <= din_shr;
+            dout_shr <= dout;
+        end
+    end
+
+    assign do = dout_shr[DOUT_N-1];
+    ''')
+
+    params = {}
+
+    # NOTE: The INT_L tile has been hardcoded and it works only for the part specified in the assertion
+    assert os.getenv('XRAY_PART') == "xc7z010clg400-1"
+    for isone in util.gen_fuzz_states(1):
+        params['INT_L_X0Y50'] = isone
+        print(
+            '''
+    (* KEEP, DONT_TOUCH *)
+
+    PS7 dut_%(dut)s(
+	.DMA0DATYPE			(),
+	.DMA0DAVALID			(),
+	.DMA0DRREADY			(),
+	.DMA0RSTN			(),
+	.DMA1DATYPE	              	(),
+	.DMA1DAVALID			(),
+	.DMA1DRREADY			(),
+	.DMA1RSTN			(),
+	.DMA2DATYPE			(),
+	.DMA2DAVALID			(),
+	.DMA2DRREADY			(),
+	.DMA2RSTN			(),
+	.DMA3DATYPE			(),
+	.DMA3DAVALID			(),
+	.DMA3DRREADY			(),
+	.DMA3RSTN			(),
+	.EMIOCAN0PHYTX			(),
+	.EMIOCAN1PHYTX			(),
+	.EMIOENET0GMIITXD		(),
+	.EMIOENET0GMIITXEN		(),
+	.EMIOENET0GMIITXER		(),
+	.EMIOENET0MDIOMDC		(),
+	.EMIOENET0MDIOO			(),
+	.EMIOENET0MDIOTN		(),
+	.EMIOENET0PTPDELAYREQRX		(),
+	.EMIOENET0PTPDELAYREQTX		(),
+	.EMIOENET0PTPPDELAYREQRX	(),
+	.EMIOENET0PTPPDELAYREQTX	(),
+	.EMIOENET0PTPPDELAYRESPRX	(),
+	.EMIOENET0PTPPDELAYRESPTX	(),
+	.EMIOENET0PTPSYNCFRAMERX	(),
+	.EMIOENET0PTPSYNCFRAMETX	(),
+	.EMIOENET0SOFRX			(),
+	.EMIOENET0SOFTX			(),
+	.EMIOENET1GMIITXD		(),
+	.EMIOENET1GMIITXEN		(),
+	.EMIOENET1GMIITXER		(),
+	.EMIOENET1MDIOMDC		(),
+	.EMIOENET1MDIOO			(),
+	.EMIOENET1MDIOTN		(),
+	.EMIOENET1PTPDELAYREQRX		(),
+	.EMIOENET1PTPDELAYREQTX		(),
+	.EMIOENET1PTPPDELAYREQRX	(),
+	.EMIOENET1PTPPDELAYREQTX	(),
+	.EMIOENET1PTPPDELAYRESPRX	(),
+	.EMIOENET1PTPPDELAYRESPTX	(),
+	.EMIOENET1PTPSYNCFRAMERX	(),
+	.EMIOENET1PTPSYNCFRAMETX	(),
+	.EMIOENET1SOFRX			(),
+	.EMIOENET1SOFTX			(),
+	.EMIOGPIOO			(),
+	.EMIOGPIOTN			(),
+	.EMIOI2C0SCLO			(),
+	.EMIOI2C0SCLTN			(),
+	.EMIOI2C0SDAO			(),
+	.EMIOI2C0SDATN			(),
+	.EMIOI2C1SCLO			(),
+	.EMIOI2C1SCLTN			(),
+	.EMIOI2C1SDAO			(),
+	.EMIOI2C1SDATN			(),
+	.EMIOPJTAGTDO			(),
+	.EMIOPJTAGTDTN			(),
+	.EMIOSDIO0BUSPOW		(),
+	.EMIOSDIO0BUSVOLT		(),
+	.EMIOSDIO0CLK			(),
+	.EMIOSDIO0CMDO			(),
+	.EMIOSDIO0CMDTN			(),
+	.EMIOSDIO0DATAO			(),
+	.EMIOSDIO0DATATN		(),
+	.EMIOSDIO0LED			(),
+	.EMIOSDIO1BUSPOW		(),
+	.EMIOSDIO1BUSVOLT		(),
+	.EMIOSDIO1CLK			(),
+	.EMIOSDIO1CMDO			(),
+	.EMIOSDIO1CMDTN			(),
+	.EMIOSDIO1DATAO			(),
+	.EMIOSDIO1DATATN		(),
+	.EMIOSDIO1LED			(),
+	.EMIOSPI0MO			(),
+	.EMIOSPI0MOTN			(),
+	.EMIOSPI0SCLKO			(),
+	.EMIOSPI0SCLKTN			(),
+	.EMIOSPI0SO			(),
+	.EMIOSPI0SSNTN			(),
+	.EMIOSPI0SSON			(),
+	.EMIOSPI0STN			(),
+	.EMIOSPI1MO			(),
+	.EMIOSPI1MOTN			(),
+	.EMIOSPI1SCLKO			(),
+	.EMIOSPI1SCLKTN			(),
+	.EMIOSPI1SO			(),
+	.EMIOSPI1SSNTN			(),
+	.EMIOSPI1SSON			(),
+	.EMIOSPI1STN			(),
+	.EMIOTRACECTL			(),
+	.EMIOTRACEDATA			(),
+	.EMIOTTC0WAVEO			(),
+	.EMIOTTC1WAVEO			(),
+	.EMIOUART0DTRN			(),
+	.EMIOUART0RTSN			(),
+	.EMIOUART0TX			(),
+	.EMIOUART1DTRN			(),
+	.EMIOUART1RTSN			(),
+	.EMIOUART1TX			(),
+	.EMIOUSB0PORTINDCTL		(),
+	.EMIOUSB0VBUSPWRSELECT		(),
+	.EMIOUSB1PORTINDCTL		(),
+	.EMIOUSB1VBUSPWRSELECT		(),
+	.EMIOWDTRSTO			(),
+	.EVENTEVENTO			(),
+	.EVENTSTANDBYWFE		(),
+	.EVENTSTANDBYWFI		(),
+	.FCLKCLK			(),
+	.FCLKRESETN			(),
+	.FTMTF2PTRIGACK			(),
+	.FTMTP2FDEBUG			(),
+	.FTMTP2FTRIG			(),
+	.IRQP2F				(),
+	.MAXIGP0ARADDR			(),
+	.MAXIGP0ARBURST			(),
+	.MAXIGP0ARCACHE			(),
+	.MAXIGP0ARESETN			(),
+	.MAXIGP0ARID			(),
+	.MAXIGP0ARLEN			(),
+	.MAXIGP0ARLOCK			(),
+	.MAXIGP0ARPROT			(),
+	.MAXIGP0ARQOS			(),
+	.MAXIGP0ARSIZE			(),
+	.MAXIGP0ARVALID			(),
+	.MAXIGP0AWADDR			(),
+	.MAXIGP0AWBURST			(),
+	.MAXIGP0AWCACHE			(),
+	.MAXIGP0AWID			(),
+	.MAXIGP0AWLEN			(),
+	.MAXIGP0AWLOCK			(),
+	.MAXIGP0AWPROT			(),
+	.MAXIGP0AWQOS			(),
+	.MAXIGP0AWSIZE			(),
+	.MAXIGP0AWVALID			(),
+	.MAXIGP0BREADY			(),
+	.MAXIGP0RREADY			(),
+	.MAXIGP0WDATA			(),
+	.MAXIGP0WID			(),
+	.MAXIGP0WLAST			(),
+	.MAXIGP0WSTRB			(),
+	.MAXIGP0WVALID			(),
+	.MAXIGP1ARADDR			(),
+	.MAXIGP1ARBURST			(),
+	.MAXIGP1ARCACHE			(),
+	.MAXIGP1ARESETN			(),
+	.MAXIGP1ARID			(),
+	.MAXIGP1ARLEN			(),
+	.MAXIGP1ARLOCK			(),
+	.MAXIGP1ARPROT			(),
+	.MAXIGP1ARQOS			(),
+	.MAXIGP1ARSIZE			(),
+	.MAXIGP1ARVALID			(),
+	.MAXIGP1AWADDR			(),
+	.MAXIGP1AWBURST			(),
+	.MAXIGP1AWCACHE			(),
+	.MAXIGP1AWID			(),
+	.MAXIGP1AWLEN			(),
+	.MAXIGP1AWLOCK			(),
+	.MAXIGP1AWPROT			(),
+	.MAXIGP1AWQOS			(),
+	.MAXIGP1AWSIZE			(),
+	.MAXIGP1AWVALID			(),
+	.MAXIGP1BREADY			(),
+	.MAXIGP1RREADY			(),
+	.MAXIGP1WDATA			(),
+	.MAXIGP1WID			(),
+	.MAXIGP1WLAST			(),
+	.MAXIGP1WSTRB			(),
+	.MAXIGP1WVALID			(),
+	.SAXIACPARESETN			(),
+	.SAXIACPARREADY			(),
+	.SAXIACPAWREADY			(),
+	.SAXIACPBID			(),
+	.SAXIACPBRESP			(),
+	.SAXIACPBVALID			(),
+	.SAXIACPRDATA			(),
+	.SAXIACPRID			(),
+	.SAXIACPRLAST			(),
+	.SAXIACPRRESP			(),
+	.SAXIACPRVALID			(),
+	.SAXIACPWREADY			(),
+	.SAXIGP0ARESETN			(),
+	.SAXIGP0ARREADY			(),
+	.SAXIGP0AWREADY			(),
+	.SAXIGP0BID			(),
+	.SAXIGP0BRESP			(),
+	.SAXIGP0BVALID			(),
+	.SAXIGP0RDATA			(),
+	.SAXIGP0RID			(),
+	.SAXIGP0RLAST			(),
+	.SAXIGP0RRESP			(),
+	.SAXIGP0RVALID			(),
+	.SAXIGP0WREADY			(),
+	.SAXIGP1ARESETN			(),
+	.SAXIGP1ARREADY			(),
+	.SAXIGP1AWREADY			(),
+	.SAXIGP1BID			(),
+	.SAXIGP1BRESP			(),
+	.SAXIGP1BVALID			(),
+	.SAXIGP1RDATA			(),
+	.SAXIGP1RID			(),
+	.SAXIGP1RLAST			(),
+	.SAXIGP1RRESP			(),
+	.SAXIGP1RVALID			(),
+	.SAXIGP1WREADY			(),
+	.SAXIHP0ARESETN			(),
+	.SAXIHP0ARREADY			(),
+	.SAXIHP0AWREADY			(),
+	.SAXIHP0BID			(),
+	.SAXIHP0BRESP			(),
+	.SAXIHP0BVALID			(),
+	.SAXIHP0RACOUNT			(),
+	.SAXIHP0RCOUNT			(),
+	.SAXIHP0RDATA			(),
+	.SAXIHP0RID			(),
+	.SAXIHP0RLAST			(),
+	.SAXIHP0RRESP			(),
+	.SAXIHP0RVALID			(),
+	.SAXIHP0WACOUNT			(),
+	.SAXIHP0WCOUNT			(),
+	.SAXIHP0WREADY			(),
+	.SAXIHP1ARESETN			(),
+	.SAXIHP1ARREADY			(),
+	.SAXIHP1AWREADY			(),
+	.SAXIHP1BID			(),
+	.SAXIHP1BRESP			(),
+	.SAXIHP1BVALID			(),
+	.SAXIHP1RACOUNT			(),
+	.SAXIHP1RCOUNT			(),
+	.SAXIHP1RDATA			(),
+	.SAXIHP1RID			(),
+	.SAXIHP1RLAST			(),
+	.SAXIHP1RRESP			(),
+	.SAXIHP1RVALID			(),
+	.SAXIHP1WACOUNT			(),
+	.SAXIHP1WCOUNT			(),
+	.SAXIHP1WREADY			(),
+	.SAXIHP2ARESETN			(),
+	.SAXIHP2ARREADY			(),
+	.SAXIHP2AWREADY			(),
+	.SAXIHP2BID			(),
+	.SAXIHP2BRESP			(),
+	.SAXIHP2BVALID			(),
+	.SAXIHP2RACOUNT			(),
+	.SAXIHP2RCOUNT			(),
+	.SAXIHP2RDATA			(),
+	.SAXIHP2RID			(),
+	.SAXIHP2RLAST			(),
+	.SAXIHP2RRESP			(),
+	.SAXIHP2RVALID			(),
+	.SAXIHP2WACOUNT			(),
+	.SAXIHP2WCOUNT			(),
+	.SAXIHP2WREADY			(),
+	.SAXIHP3ARESETN			(),
+	.SAXIHP3ARREADY			(),
+	.SAXIHP3AWREADY			(),
+	.SAXIHP3BID			(),
+	.SAXIHP3BRESP			(),
+	.SAXIHP3BVALID			(),
+	.SAXIHP3RACOUNT			(),
+	.SAXIHP3RCOUNT			(),
+	.SAXIHP3RDATA			(),
+	.SAXIHP3RID			(),
+	.SAXIHP3RLAST			(),
+	.SAXIHP3RRESP			(),
+	.SAXIHP3RVALID			(),
+	.SAXIHP3WACOUNT			(),
+	.SAXIHP3WCOUNT			(),
+	.SAXIHP3WREADY			(),
+	.DDRA				(),
+	.DDRBA				(),
+	.DDRCASB			(),
+	.DDRCKE				(),
+	.DDRCKN				(),
+	.DDRCKP				(),
+	.DDRCSB				(),
+	.DDRDM				(),
+	.DDRDQ				(),
+	.DDRDQSN			(),
+	.DDRDQSP			(),
+	.DDRDRSTB			(),
+	.DDRODT				(),
+	.DDRRASB			(),
+	.DDRVRN				(),
+	.DDRVRP				(),
+	.DDRWEB				(),
+	.MIO				(),
+	.PSCLK				(),
+	.PSPORB				(),
+	.PSSRSTB			(),
+	.DDRARB				(%(dout)u),
+	.DMA0ACLK			(),
+	.DMA0DAREADY			(),
+	.DMA0DRLAST			(),
+	.DMA0DRTYPE			(),
+	.DMA0DRVALID			(),
+	.DMA1ACLK			(),
+	.DMA1DAREADY			(),
+	.DMA1DRLAST			(),
+	.DMA1DRTYPE			(),
+	.DMA1DRVALID			(),
+	.DMA2ACLK			(),
+	.DMA2DAREADY			(),
+	.DMA2DRLAST			(),
+	.DMA2DRTYPE			(),
+	.DMA2DRVALID			(),
+	.DMA3ACLK			(),
+	.DMA3DAREADY			(),
+	.DMA3DRLAST			(),
+	.DMA3DRTYPE			(),
+	.DMA3DRVALID			(),
+	.EMIOCAN0PHYRX			(),
+	.EMIOCAN1PHYRX			(),
+	.EMIOENET0EXTINTIN		(),
+	.EMIOENET0GMIICOL		(),
+	.EMIOENET0GMIICRS		(),
+	.EMIOENET0GMIIRXCLK		(),
+	.EMIOENET0GMIIRXD		(),
+	.EMIOENET0GMIIRXDV		(),
+	.EMIOENET0GMIIRXER		(),
+	.EMIOENET0GMIITXCLK		(),
+	.EMIOENET0MDIOI			(),
+	.EMIOENET1EXTINTIN		(),
+	.EMIOENET1GMIICOL		(),
+	.EMIOENET1GMIICRS		(),
+	.EMIOENET1GMIIRXCLK		(),
+	.EMIOENET1GMIIRXD		(),
+	.EMIOENET1GMIIRXDV		(),
+	.EMIOENET1GMIIRXER		(),
+	.EMIOENET1GMIITXCLK		(),
+	.EMIOENET1MDIOI			(),
+	.EMIOGPIOI			(),
+	.EMIOI2C0SCLI			(),
+	.EMIOI2C0SDAI			(),
+	.EMIOI2C1SCLI			(),
+	.EMIOI2C1SDAI			(),
+	.EMIOPJTAGTCK			(),
+	.EMIOPJTAGTDI			(),
+	.EMIOPJTAGTMS			(),
+	.EMIOSDIO0CDN			(),
+	.EMIOSDIO0CLKFB			(),
+	.EMIOSDIO0CMDI			(),
+	.EMIOSDIO0DATAI			(),
+	.EMIOSDIO0WP			(),
+	.EMIOSDIO1CDN			(),
+	.EMIOSDIO1CLKFB			(),
+	.EMIOSDIO1CMDI			(),
+	.EMIOSDIO1DATAI			(),
+	.EMIOSDIO1WP			(),
+	.EMIOSPI0MI			(),
+	.EMIOSPI0SCLKI			(),
+	.EMIOSPI0SI			(),
+	.EMIOSPI0SSIN			(),
+	.EMIOSPI1MI			(),
+	.EMIOSPI1SCLKI			(),
+	.EMIOSPI1SI			(),
+	.EMIOSPI1SSIN			(),
+	.EMIOSRAMINTIN			(),
+	.EMIOTRACECLK			(),
+	.EMIOTTC0CLKI			(),
+	.EMIOTTC1CLKI			(),
+	.EMIOUART0CTSN			(),
+	.EMIOUART0DCDN			(),
+	.EMIOUART0DSRN			(),
+	.EMIOUART0RIN			(),
+	.EMIOUART0RX			(),
+	.EMIOUART1CTSN			(),
+	.EMIOUART1DCDN			(),
+	.EMIOUART1DSRN			(),
+	.EMIOUART1RIN			(),
+	.EMIOUART1RX			(),
+	.EMIOUSB0VBUSPWRFAULT		(),
+	.EMIOUSB1VBUSPWRFAULT		(),
+	.EMIOWDTCLKI			(),
+	.EVENTEVENTI			(),
+	.FCLKCLKTRIGN			(),
+	.FPGAIDLEN			(),
+	.FTMDTRACEINATID		(),
+	.FTMDTRACEINCLOCK		(),
+	.FTMDTRACEINDATA		(),
+	.FTMDTRACEINVALID		(),
+	.FTMTF2PDEBUG			(),
+	.FTMTF2PTRIG			(),
+	.FTMTP2FTRIGACK			(),
+	.IRQF2P				(),
+	.MAXIGP0ACLK			(),
+	.MAXIGP0ARREADY			(),
+	.MAXIGP0AWREADY			(),
+	.MAXIGP0BID			(),
+	.MAXIGP0BRESP			(),
+	.MAXIGP0BVALID			(),
+	.MAXIGP0RDATA			(),
+	.MAXIGP0RID			(),
+	.MAXIGP0RLAST			(),
+	.MAXIGP0RRESP			(),
+	.MAXIGP0RVALID			(),
+	.MAXIGP0WREADY			(),
+	.MAXIGP1ACLK			(),
+	.MAXIGP1ARREADY			(),
+	.MAXIGP1AWREADY			(),
+	.MAXIGP1BID			(),
+	.MAXIGP1BRESP			(),
+	.MAXIGP1BVALID			(),
+	.MAXIGP1RDATA			(),
+	.MAXIGP1RID			(),
+	.MAXIGP1RLAST			(),
+	.MAXIGP1RRESP			(),
+	.MAXIGP1RVALID			(),
+	.MAXIGP1WREADY			(),
+	.SAXIACPACLK			(),
+	.SAXIACPARADDR			(),
+	.SAXIACPARBURST			(),
+	.SAXIACPARCACHE			(),
+	.SAXIACPARID			(),
+	.SAXIACPARLEN			(),
+	.SAXIACPARLOCK			(),
+	.SAXIACPARPROT			(),
+	.SAXIACPARQOS			(),
+	.SAXIACPARSIZE			(),
+	.SAXIACPARUSER			(),
+	.SAXIACPARVALID			(),
+	.SAXIACPAWADDR			(),
+	.SAXIACPAWBURST			(),
+	.SAXIACPAWCACHE			(),
+	.SAXIACPAWID			(),
+	.SAXIACPAWLEN			(),
+	.SAXIACPAWLOCK			(),
+	.SAXIACPAWPROT			(),
+	.SAXIACPAWQOS			(),
+	.SAXIACPAWSIZE			(),
+	.SAXIACPAWUSER			(),
+	.SAXIACPAWVALID			(),
+	.SAXIACPBREADY			(),
+	.SAXIACPRREADY			(),
+	.SAXIACPWDATA			(),
+	.SAXIACPWID			(),
+	.SAXIACPWLAST			(),
+	.SAXIACPWSTRB			(),
+	.SAXIACPWVALID			(),
+	.SAXIGP0ACLK			(),
+	.SAXIGP0ARADDR			(),
+	.SAXIGP0ARBURST			(),
+	.SAXIGP0ARCACHE			(),
+	.SAXIGP0ARID			(),
+	.SAXIGP0ARLEN			(),
+	.SAXIGP0ARLOCK			(),
+	.SAXIGP0ARPROT			(),
+	.SAXIGP0ARQOS			(),
+	.SAXIGP0ARSIZE			(),
+	.SAXIGP0ARVALID			(),
+	.SAXIGP0AWADDR			(),
+	.SAXIGP0AWBURST			(),
+	.SAXIGP0AWCACHE			(),
+	.SAXIGP0AWID			(),
+	.SAXIGP0AWLEN			(),
+	.SAXIGP0AWLOCK			(),
+	.SAXIGP0AWPROT			(),
+	.SAXIGP0AWQOS			(),
+	.SAXIGP0AWSIZE			(),
+	.SAXIGP0AWVALID			(),
+	.SAXIGP0BREADY			(),
+	.SAXIGP0RREADY			(),
+	.SAXIGP0WDATA			(),
+	.SAXIGP0WID			(),
+	.SAXIGP0WLAST			(),
+	.SAXIGP0WSTRB			(),
+	.SAXIGP0WVALID			(),
+	.SAXIGP1ACLK			(),
+	.SAXIGP1ARADDR			(),
+	.SAXIGP1ARBURST			(),
+	.SAXIGP1ARCACHE			(),
+	.SAXIGP1ARID			(),
+	.SAXIGP1ARLEN			(),
+	.SAXIGP1ARLOCK			(),
+	.SAXIGP1ARPROT			(),
+	.SAXIGP1ARQOS			(),
+	.SAXIGP1ARSIZE			(),
+	.SAXIGP1ARVALID			(),
+	.SAXIGP1AWADDR			(),
+	.SAXIGP1AWBURST			(),
+	.SAXIGP1AWCACHE			(),
+	.SAXIGP1AWID			(),
+	.SAXIGP1AWLEN			(),
+	.SAXIGP1AWLOCK			(),
+	.SAXIGP1AWPROT			(),
+	.SAXIGP1AWQOS			(),
+	.SAXIGP1AWSIZE			(),
+	.SAXIGP1AWVALID			(),
+	.SAXIGP1BREADY			(),
+	.SAXIGP1RREADY			(),
+	.SAXIGP1WDATA			(),
+	.SAXIGP1WID			(),
+	.SAXIGP1WLAST			(),
+	.SAXIGP1WSTRB			(),
+	.SAXIGP1WVALID			(),
+	.SAXIHP0ACLK			(),
+	.SAXIHP0ARADDR			(),
+	.SAXIHP0ARBURST			(),
+	.SAXIHP0ARCACHE			(),
+	.SAXIHP0ARID			(),
+	.SAXIHP0ARLEN			(),
+	.SAXIHP0ARLOCK			(),
+	.SAXIHP0ARPROT			(),
+	.SAXIHP0ARQOS			(),
+	.SAXIHP0ARSIZE			(),
+	.SAXIHP0ARVALID			(),
+	.SAXIHP0AWADDR			(),
+	.SAXIHP0AWBURST			(),
+	.SAXIHP0AWCACHE			(),
+	.SAXIHP0AWID			(),
+	.SAXIHP0AWLEN			(),
+	.SAXIHP0AWLOCK			(),
+	.SAXIHP0AWPROT			(),
+	.SAXIHP0AWQOS			(),
+	.SAXIHP0AWSIZE			(),
+	.SAXIHP0AWVALID			(),
+	.SAXIHP0BREADY			(),
+	.SAXIHP0RDISSUECAP1EN		(),
+	.SAXIHP0RREADY			(),
+	.SAXIHP0WDATA			(),
+	.SAXIHP0WID			(),
+	.SAXIHP0WLAST			(),
+	.SAXIHP0WRISSUECAP1EN		(),
+	.SAXIHP0WSTRB			(),
+	.SAXIHP0WVALID			(),
+	.SAXIHP1ACLK			(),
+	.SAXIHP1ARADDR			(),
+	.SAXIHP1ARBURST			(),
+	.SAXIHP1ARCACHE			(),
+	.SAXIHP1ARID			(),
+	.SAXIHP1ARLEN			(),
+	.SAXIHP1ARLOCK			(),
+	.SAXIHP1ARPROT			(),
+	.SAXIHP1ARQOS			(),
+	.SAXIHP1ARSIZE			(),
+	.SAXIHP1ARVALID			(),
+	.SAXIHP1AWADDR			(),
+	.SAXIHP1AWBURST			(),
+	.SAXIHP1AWCACHE			(),
+	.SAXIHP1AWID			(),
+	.SAXIHP1AWLEN			(),
+	.SAXIHP1AWLOCK			(),
+	.SAXIHP1AWPROT			(),
+	.SAXIHP1AWQOS			(),
+	.SAXIHP1AWSIZE			(),
+	.SAXIHP1AWVALID			(),
+	.SAXIHP1BREADY			(),
+	.SAXIHP1RDISSUECAP1EN		(),
+	.SAXIHP1RREADY			(),
+	.SAXIHP1WDATA			(),
+	.SAXIHP1WID			(),
+	.SAXIHP1WLAST			(),
+	.SAXIHP1WRISSUECAP1EN		(),
+	.SAXIHP1WSTRB			(),
+	.SAXIHP1WVALID			(),
+	.SAXIHP2ACLK			(),
+	.SAXIHP2ARADDR			(),
+	.SAXIHP2ARBURST			(),
+	.SAXIHP2ARCACHE			(),
+	.SAXIHP2ARID			(),
+	.SAXIHP2ARLEN			(),
+	.SAXIHP2ARLOCK			(),
+	.SAXIHP2ARPROT			(),
+	.SAXIHP2ARQOS			(),
+	.SAXIHP2ARSIZE			(),
+	.SAXIHP2ARVALID			(),
+	.SAXIHP2AWADDR			(),
+	.SAXIHP2AWBURST			(),
+	.SAXIHP2AWCACHE			(),
+	.SAXIHP2AWID			(),
+	.SAXIHP2AWLEN			(),
+	.SAXIHP2AWLOCK			(),
+	.SAXIHP2AWPROT			(),
+	.SAXIHP2AWQOS			(),
+	.SAXIHP2AWSIZE			(),
+	.SAXIHP2AWVALID			(),
+	.SAXIHP2BREADY			(),
+	.SAXIHP2RDISSUECAP1EN		(),
+	.SAXIHP2RREADY			(),
+	.SAXIHP2WDATA			(),
+	.SAXIHP2WID			(),
+	.SAXIHP2WLAST			(),
+	.SAXIHP2WRISSUECAP1EN		(),
+	.SAXIHP2WSTRB			(),
+	.SAXIHP2WVALID			(),
+	.SAXIHP3ACLK			(),
+	.SAXIHP3ARADDR			(),
+	.SAXIHP3ARBURST			(),
+	.SAXIHP3ARCACHE			(),
+	.SAXIHP3ARID			(),
+	.SAXIHP3ARLEN			(),
+	.SAXIHP3ARLOCK			(),
+	.SAXIHP3ARPROT			(),
+	.SAXIHP3ARQOS			(),
+	.SAXIHP3ARSIZE			(),
+	.SAXIHP3ARVALID			(),
+	.SAXIHP3AWADDR			(),
+	.SAXIHP3AWBURST			(),
+	.SAXIHP3AWCACHE			(),
+	.SAXIHP3AWID			(),
+	.SAXIHP3AWLEN			(),
+	.SAXIHP3AWLOCK			(),
+	.SAXIHP3AWPROT			(),
+	.SAXIHP3AWQOS			(),
+	.SAXIHP3AWSIZE			(),
+	.SAXIHP3AWVALID			(),
+	.SAXIHP3BREADY			(),
+	.SAXIHP3RDISSUECAP1EN		(),
+	.SAXIHP3RREADY			(),
+	.SAXIHP3WDATA			(),
+	.SAXIHP3WID			(),
+	.SAXIHP3WLAST			(),
+	.SAXIHP3WRISSUECAP1EN		(),
+	.SAXIHP3WSTRB			(),
+	.SAXIHP3WVALID			()
+	);
+    ''' % {
+                'dut': 'site_name',
+                'dout': isone
+            })
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()

fuzzers/007-timing/README.md

@@ -174,24 +174,32 @@ At a high level, the above learnings gave this process:
   - Group delays map onto the group pivot variable, typically setting other elements to 0 (if the processed set is not the one used to create the pivots they may be non-zero)
 
 
-## TODO
+## TODO, suggestions
 
-Milestone 1 (MVP)
-* DONE
-* Provide any process corner with at least some of the fabric
-
-Milestone 2
-* Provide all four fabric corners
-* Simple makefile based flow
-* Cleanup/separate fabric input targets
-
-Milestone 3
-* Create site delay model
-
-Final
-* Investigate ZERO
-* Investigate virtual switchboxes
-* Compare our vs Xilinx output on random designs
+Includes
+* Consider removing rref
+  - Intended to understand what can't be solved, maybe not useful in production
+* Need more coverage
+  - Consider instrumenting all fuzzers to output data to feed into timing anlayzer
+  - Justification: we need a lot of weird cases, we have code that does that in the other fuzzers
+* Tune performance parameters
+  - Can we improve quality of results?
+  - Do we have a good enough quality checker? (solve_qor.py)
+  - Compare our vs Xilinx output on random designs
+  - Does the solve take too long? What could speed it up?
+* Investigate min corner
+  - Tends to solve towards 0, making this not useful
+  - Low priority: most designs just close timing with setup time
+* Investigate characterizing full RC timing model
+* Can we split pivot delays among elements instead of entirely into pivot?
+* Consider breaking out timing analyzer into its own project / library so it can be re-used on other projects
+* Review "--massage". Does this help?
+* Review computed site delays vs published Xilinx numbers (DC and AC Switching Characteristics)
+* Fabric delay models are RC, but are the site delay models RC as well or maybe just linear?
+* Can we create antenna nets to get simpler solves?
+* Can we get tcl timing analyzer to analyze a partial route?
+   - Option says you should be able to do this
+   - I could not actually get it to work
 
 
 ### Improve test cases
@@ -206,7 +214,7 @@ At a minimum these should be moved to their own directory.
 Background: there are a number of speed models with the name ZERO in them.
 These generally seem to be zero delay, although needs more investigation.
 
-Example: see virtual switchbox item below
+Example: see pseudo pip item below
 
 The timing models will probably significantly improve if these are removed.
 In the past I was removing them, but decided to keep them in for now in the spirit of being more conservative.

fuzzers/010-clb-lutinit/README.md

@@ -0,0 +1,7 @@
+# clb-lutinit Fuzzer
+
+## NLUT.INIT
+
+Sites: CLBL[LM]_[LR].SLICE[LM]_X[01] (all CLB)
+
+Sets the LUT6 INIT property

fuzzers/011-clb-ffconfig/README.md

@@ -0,0 +1,110 @@
+# clb-ffconfig Fuzzer
+
+Documents FF configuration.
+
+Note Vivado GUI is misleading in some cases where it shows configuration per FF, but its actually per SLICE
+
+## Primitive pin map
+
+|  Element | CE | CK | D | SR  | Q |
+|----------|----|----|---|-----|---|
+| FDRE     | CE | C  | D | R   | Q |
+| FDPE     | CE | C  | D | PRE | Q |
+| FDSE     | CE | C  | D | S   | Q |
+| FDCE     | CE | C  | D | CLR | Q |
+| LDPE     | GE | G  | D | PRE | Q |
+| LDCE     | GE | G  | D | CLR | Q |
+
+
+## Primitive bit map
+
+| Prim | FFSYNC | LATCH | ZRST |
+|------|--------|-------|------|
+|FDPE  |        |       |      |
+|FDSE  | X      |       |      |
+|FDRE  | X      |       | X    |
+|FDCE  |        |       | X    |
+|LDCE  |        | X     | X    |
+|LDPE  |        | X     |      |
+
+
+### FFSYNC
+
+Configures whether a storage element is synchronous or asynchronous.
+
+Scope: entire site (not individual FFs)
+
+| FFSYNC | Reset        | Applicable prims          | 
+|--------|--------------|---------------------------|
+|0       | Synchronous  | FDPE, FDCE, LDCE, LDPE    |
+|1       | Asynchronous | FDSE, FDRE                |
+
+
+### LATCH
+
+Configures latch vs FF behavior for the CLB
+
+| LATCH | Description | Primitives |
+|-------|-------------|------------|
+|0      | All storage elements in the CLB are FF's  | FDPE, FDSE, FDRE, FDCE    |
+|1      | LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used  | LDCE, LDPE    |
+
+
+### N*FF.ZRST
+
+Configures stored value when reset is asserted
+
+| Prim                  |ZRST|On reset|
+|-----------------------|----|-----   |
+|FDRE, FDCE, and LDCE   | 0  | 1      |
+|FDRE, FDCE, and LDCE   | 1  | 0      |
+|FDPE, FDSE, and LDPE   | 0  | 0      |
+|FDPE, FDSE, and LDPE   | 1  | 1      |
+
+
+## N*FF.ZINI
+
+Sets GSR FF or latch value
+
+| LATCH | ZINI | Set to |
+|-------|------|--------|
+| FF    | 0    | 1      |
+| FF    | 1    | 0      |
+| LATCH | 0    | 0      |
+| LATCH | 1    | 1      |
+
+
+## CEUSEDMUX
+
+Configures ability to drive clock enable (CE) or always enable clock
+
+| CEUSEDMUX | Description             |
+|-----------|-------------------------|
+| 0         | always on (CE=1)        |
+| 1         | controlled (CE=mywire)  |
+
+
+## SRUSEDMUX
+
+Configures ability to reset FF after GSR
+
+| SRUSEDMUX | Description           |
+|-----------|-----------------------|
+| 0         | never reset (R=0)     |
+| 1         | controlled (R=mywire) |
+
+TODO: how used when SR?
+
+## CLKINV
+
+Configures whether to invert the clock going into a slice.
+
+Scope: entire site (not individual FFs)
+
+| LATCH | CLKINV | Description    |
+|-------|--------|----------------|
+| FF    | 0      | normal clock   |
+| FF    | 1      | invert clock   |
+| LATCH | 0      | invert clock   |
+| LATCH | 1      | normal clock   |
+

fuzzers/011-ffconfig/README.md

@@ -1,61 +0,0 @@
-# FFConfig Fuzzer
-
-Documents the following:  
-- FF clock inversion  
-- FF primitive mapping  
-- FF initialization value  
-
-Clock inversion is per slice (as BEL CLKINV)  
-Vivado GUI is misleading as it often shows it per FF, which is not actually true  
-
-|      |FFSYNC|LATCH|ZRST |
-|------|------|-----|-----|
-|Sample| 00_48|30_32|30_12|
-|FDPE  |      |     |     |
-|FDSE  |   X  |     |     |
-|FDRE  |   X  |     |  X  |
-|FDCE  |      |     |  X  |
-|LDCE  |      |  X  |  X  |
-|LDPE  |      |  X  |     |
-
-
-```
-CLB.SLICE_X0.A5FF.ZINIT 31_06
-CLB.SLICE_X0.A5FF.ZRESET 01_07
-CLB.SLICE_X0.AFF.ZINIT 31_03
-CLB.SLICE_X0.AFF.ZRESET 30_12
-CLB.SLICE_X0.B5FF.ZINIT 31_22
-CLB.SLICE_X0.B5FF.ZRESET 01_19
-CLB.SLICE_X0.BFF.ZINIT 31_28
-CLB.SLICE_X0.BFF.ZRESET 30_30
-CLB.SLICE_X0.C5FF.ZINIT 31_41
-CLB.SLICE_X0.C5FF.ZRESET 01_47
-CLB.SLICE_X0.CFF.ZINIT 31_33
-CLB.SLICE_X0.CFF.ZRESET 30_33
-CLB.SLICE_X0.CLKINV 01_51
-CLB.SLICE_X0.D5FF.ZINIT 31_51
-CLB.SLICE_X0.D5FF.ZRESET 01_55
-CLB.SLICE_X0.DFF.ZINIT 31_58
-CLB.SLICE_X0.DFF.ZRESET 30_50
-CLB.SLICE_X0.FFSYNC 00_48
-CLB.SLICE_X0.LATCH 30_32
-CLB.SLICE_X1.A5FF.ZINIT 31_05
-CLB.SLICE_X1.A5FF.ZRESET 01_03
-CLB.SLICE_X1.AFF.ZINIT 31_04
-CLB.SLICE_X1.AFF.ZRESET 31_15
-CLB.SLICE_X1.B5FF.ZINIT 31_23
-CLB.SLICE_X1.B5FF.ZRESET 00_16
-CLB.SLICE_X1.BFF.ZINIT 31_29
-CLB.SLICE_X1.BFF.ZRESET 31_30
-CLB.SLICE_X1.C5FF.ZINIT 31_42
-CLB.SLICE_X1.C5FF.ZRESET 00_44
-CLB.SLICE_X1.CFF.ZINIT 31_34
-CLB.SLICE_X1.CFF.ZRESET 30_34
-CLB.SLICE_X1.CLKINV 00_52
-CLB.SLICE_X1.D5FF.ZINIT 31_52
-CLB.SLICE_X1.D5FF.ZRESET 00_56
-CLB.SLICE_X1.DFF.ZINIT 31_59
-CLB.SLICE_X1.DFF.ZRESET 31_50
-CLB.SLICE_X1.FFSYNC 01_31
-CLB.SLICE_X1.LATCH 31_32
-```

fuzzers/012-clb-n5ffmux/README.md

@@ -0,0 +1,11 @@
+# clb-n5ffmux Fuzzer
+
+## N5FFMUX
+
+The A5FFMUX family of CLB muxes feed the D input of A5FF family of FFs
+
+| N5FFMUX  | N5FFMUX.D       | 
+|--------|-----------------|
+| IN_A   | N5LUT.O5        |
+| IN_B   | NX              |
+

fuzzers/012-clbn5ffmux/README.md

@@ -1,18 +0,0 @@
-# CLBn5FFMUX Fuzzer
-
-## Purpose
-Document A5FFMUX family of CLB muxes
-
-## Algorithm
-5FFMUX  
-Inputs can come from either the LUT6_2 NO5 output or the CLB NX input  
-To perturb the CLB the smallest, want LUT6 always instantiated  
-However, some routing congestion that would require putting FFs in bypass  
-(which turns out is actually okay, but didn't realize that at the time)  
-Decided instead ot instantiate LUT8, but not use the output  
-Turns out this is okay and won't optimize things away  
-So then, the 5FF D input is switched between the O5 output and an external CLB input  
-
-## Outcome
-Bits are one hot encoded per mux position
-

fuzzers/013-clb-ncy0/README.md

@@ -0,0 +1,11 @@
+# clb-ncy0 Fuzzer
+
+## CARRY4.NCY0
+
+The ACY0 family of CLB muxes feeds the CARRY4.DI0 family
+
+| NCY0  | CARRY4.DIN       | 
+|--------|------------------|
+| 0      | NX               |
+| 1      | O5               |
+

fuzzers/013-clb-ncy0/top.py

@@ -60,7 +60,6 @@ module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
     parameter N=-1;
 
     wire [3:0] o;
-    assign dout[0] = o[1];
     wire o6, o5;
     reg [3:0] s;
 
@@ -84,6 +83,15 @@ module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
 
 	(* LOC=LOC, KEEP, DONT_TOUCH *)
     CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
+
+	(* LOC=LOC, BEL=\"AFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce1(.D(o[0]), .C(clk), .CE(), .R(), .Q());
+	(* LOC=LOC, BEL=\"BFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce2(.D(o[1]), .C(clk), .CE(), .R(), .Q());
+	(* LOC=LOC, BEL=\"CFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce3(.D(o[2]), .C(clk), .CE(), .R(), .Q());
+	(* LOC=LOC, BEL=\"DFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce4(.D(o[3]), .C(clk), .CE(), .R(), .Q());
 endmodule
 
 module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
@@ -92,7 +100,6 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
     parameter N=-1;
 
     wire [3:0] o;
-    assign dout[0] = o[1];
     wire o6, o5;
     reg [3:0] s;
     reg [3:0] di;
@@ -120,5 +127,14 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
 
 	(* LOC=LOC, KEEP, DONT_TOUCH *)
     CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
+
+	(* LOC=LOC, BEL=\"AFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce1(.D(o[0]), .C(clk), .CE(), .R(), .Q());
+	(* LOC=LOC, BEL=\"BFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce2(.D(o[1]), .C(clk), .CE(), .R(), .Q());
+	(* LOC=LOC, BEL=\"CFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce3(.D(o[2]), .C(clk), .CE(), .R(), .Q());
+	(* LOC=LOC, BEL=\"DFF\", KEEP, DONT_TOUCH *)
+    FDRE fdce4(.D(o[3]), .C(clk), .CE(), .R(), .Q());
 endmodule
 ''')

fuzzers/013-clbncy0/README.md

@@ -1,8 +0,0 @@
-# CLBnCY0 Fuzzer
-
-## Purpose
-Document ACY0 family of CLB muxes
-
-## Algorithm
-
-## Outcome

fuzzers/014-clb-ffsrcemux/README.md

@@ -0,0 +1,23 @@
+# clb-ffsrcemux Fuzzer
+
+## CEUSEDMUX
+
+Configures whether clock enable (CE) is used or clock always on
+
+| CEUSEDMUX  | CE               | 
+|------------|------------------|
+| 0          | Always on        |
+| 1          | Controlled       |
+
+
+### SRUSEDMUX
+
+Configures whether FF can be reset or simply uses D value
+
+| SRUSEDMUX  | Resettable?      | 
+|------------|------------------|
+| 0          | No               |
+| 1          | Controlled       |
+
+XXX: How used when SR?
+

fuzzers/014-ffsrcemux/README.md

@@ -1,23 +0,0 @@
-# FFSRCEMUX Fuzzer
-
-## Purpose
-Document CEUSEDMUX, SRUSEDMUX muxes
-
-## Algorithm
-
-## Results
-
-### CEUSEDMUX: whether clock enable (CE) is used or clock always on
-0: always on  
-1: controlled  
-CLB.SLICE_X0.CEUSEDMUX 00_39  
-CLB.SLICE_X1.CEUSEDMUX <0 candidates>  
-
-
-### SRUSEDMUX: whether FF can be reset or simply uses D value
-(How used when SR?)  
-0: never reset  
-1: controlled  
-CLB.SLICE_X0.SRUSEDMUX 00_35  
-CLB.SLICE_X1.SRUSEDMUX <0 candidates>  
-

fuzzers/015-clb-nffmux/README.md

@@ -0,0 +1,8 @@
+# clb-nffmux Fuzzer
+
+## NFFMUX
+
+Configures the AFFMUX family of CLB muxes which feed the D input of the AFF series of FFs.
+
+Availible selections varies by A/B/C/D, see db for details.
+

fuzzers/015-clbnffmux/README.md

@@ -1,41 +0,0 @@
-# CLBnFFMUX Fuzzer
-
-## Purpose  
-Document nFFMUX family of CLB muxes  
-## Algorithm  
-  
-## Outcome
-```
-CLB.SLICE_X0.AFFMUX.B0 30_00  
-CLB.SLICE_X0.AFFMUX.B1 30_01  
-CLB.SLICE_X0.AFFMUX.B2 30_02  
-CLB.SLICE_X0.AFFMUX.B3 30_03  
-CLB.SLICE_X0.BFFMUX.B0 30_27  
-CLB.SLICE_X0.BFFMUX.B1 30_26  
-CLB.SLICE_X0.BFFMUX.B2 30_25  
-CLB.SLICE_X0.BFFMUX.B3 30_24  
-CLB.SLICE_X0.CFFMUX.B0 30_35  
-CLB.SLICE_X0.CFFMUX.B1 30_36  
-CLB.SLICE_X0.CFFMUX.B2 30_37  
-CLB.SLICE_X0.CFFMUX.B3 30_38  
-CLB.SLICE_X0.DFFMUX.B0 30_62  
-CLB.SLICE_X0.DFFMUX.B1 30_61  
-CLB.SLICE_X0.DFFMUX.B2 30_60  
-CLB.SLICE_X0.DFFMUX.B3 30_59  
-CLB.SLICE_X1.AFFMUX.B0 31_00  
-CLB.SLICE_X1.AFFMUX.B1 31_01  
-CLB.SLICE_X1.AFFMUX.B2 31_02  
-CLB.SLICE_X1.AFFMUX.B3 30_04  
-CLB.SLICE_X1.BFFMUX.B0 31_25  
-CLB.SLICE_X1.BFFMUX.B1 31_27  
-CLB.SLICE_X1.BFFMUX.B2 31_26  
-CLB.SLICE_X1.BFFMUX.B3 31_24  
-CLB.SLICE_X1.CFFMUX.B0 31_35  
-CLB.SLICE_X1.CFFMUX.B1 31_38  
-CLB.SLICE_X1.CFFMUX.B2 31_37  
-CLB.SLICE_X1.CFFMUX.B3 31_36  
-CLB.SLICE_X1.DFFMUX.B0 30_58  
-CLB.SLICE_X1.DFFMUX.B1 31_61  
-CLB.SLICE_X1.DFFMUX.B2 31_62  
-CLB.SLICE_X1.DFFMUX.B3 31_60  
-```

fuzzers/016-clb-noutmux/README.md

@@ -0,0 +1,8 @@
+# clb-noutmux Fuzzer
+
+## [A-D]FFMUX
+
+Configures the AOUTMUX family of CLB muxes which feed the AMUX family of CLB outputs
+
+Availible selections varies by A/B/C/D, see db for details.
+

fuzzers/016-clbnoutmux/README.md

@@ -1,52 +0,0 @@
-# CLBnOUTMUX Fuzzer
-
-## Purpose  
-Document nOUTMUX family of CLB muxes  
-## Algorithm  
-  
-## Outcome  
-```
-CLB.SLICE_X0.AOUTMUX.B0 30_11  
-CLB.SLICE_X0.AOUTMUX.B1 30_08  
-CLB.SLICE_X0.AOUTMUX.B2 30_06  
-CLB.SLICE_X0.AOUTMUX.B3 30_07  
-CLB.SLICE_X0.BOUTMUX.B0 30_20  
-CLB.SLICE_X0.BOUTMUX.B1 30_21  
-CLB.SLICE_X0.BOUTMUX.B2 30_22  
-CLB.SLICE_X0.BOUTMUX.B3 30_23  
-CLB.SLICE_X0.COUTMUX.B0 30_45  
-CLB.SLICE_X0.COUTMUX.B1 30_44  
-CLB.SLICE_X0.COUTMUX.B2 30_40  
-CLB.SLICE_X0.COUTMUX.B3 30_43  
-CLB.SLICE_X0.DOUTMUX.B0 30_56  
-CLB.SLICE_X0.DOUTMUX.B1 30_51  
-CLB.SLICE_X0.DOUTMUX.B2 30_52  
-CLB.SLICE_X0.DOUTMUX.B3 30_57  
-CLB.SLICE_X1.AOUTMUX.B0 31_09  
-CLB.SLICE_X1.AOUTMUX.B1 31_07  
-CLB.SLICE_X1.AOUTMUX.B2 31_10  
-CLB.SLICE_X1.AOUTMUX.B3 30_05  
-CLB.SLICE_X1.BOUTMUX.B0 31_20  
-CLB.SLICE_X1.BOUTMUX.B1 30_28  
-CLB.SLICE_X1.BOUTMUX.B2 31_21  
-CLB.SLICE_X1.BOUTMUX.B3 30_29  
-CLB.SLICE_X1.COUTMUX.B0 31_43  
-CLB.SLICE_X1.COUTMUX.B1 30_42  
-CLB.SLICE_X1.COUTMUX.B2 31_40  
-CLB.SLICE_X1.COUTMUX.B3 30_41  
-CLB.SLICE_X1.DOUTMUX.B0 31_56  
-CLB.SLICE_X1.DOUTMUX.B1 30_53  
-CLB.SLICE_X1.DOUTMUX.B2 31_57  
-CLB.SLICE_X1.DOUTMUX.B3 31_53  
-```
-From manual O6 testing
-```
-30_11   X0 AOUTMUX O6  
-30_20   X0 BOUTMUX O6  
-30_45   X0 COUTMUX O6  
-30_56   X0 DOUTMUX O6  
-31_09   X1 AOUTMUX O6  
-31_20   X1 BOUTMUX O6  
-31_43   X1 COUTMUX O6  
-31_56   X1 DOUTMUX O6  
-```

fuzzers/017-clb-precyinit/README.md

@@ -0,0 +1,13 @@
+# clb-precyinit Fuzzer
+
+## PRECYINIT
+
+Configures the PRECYINIT mux which provides CARRY4's first carry chain input
+
+| PRECYINIT  | Value                           | 
+|------------|---------------------------------|
+| C0         | Logic 0                         |
+| C1         | Logic 1                         |
+| AX         | AX CLB input                    |
+| CIN        | Carry in from adjacent CLB COUT |
+

fuzzers/017-clbprecyinit/README.md

@@ -1,19 +0,0 @@
-# CLBPRECYINIT Fuzzer
-
-## Purpose
-Document PRECYINIT mux
-
-## Algorithm
-
-## Outcome
-
-```
-CLB.SLICE_X0.PRECYINIT.0 <0 candidates>
-CLB.SLICE_X0.PRECYINIT.1 00_12
-CLB.SLICE_X0.PRECYINIT.AX 30_14
-CLB.SLICE_X0.PRECYINIT.CIN 30_13
-CLB.SLICE_X1.PRECYINIT.0 <0 candidates>
-CLB.SLICE_X1.PRECYINIT.1 01_11
-CLB.SLICE_X1.PRECYINIT.AX 31_13
-CLB.SLICE_X1.PRECYINIT.CIN 31_12
-```

fuzzers/018-clb-ram/README.md

@@ -0,0 +1,50 @@
+# clb-ram Fuzzer
+
+| Primitive  | RAM | SMALL | SRL |
+|------------|-----|-------|-----|
+| LUT6       |     |       |     |
+| SRL16E     |     | X     | X   |
+| SRLC32E    |     |       | X   |
+| RAM32X1S   | X   | X     |     |
+| RAM64X1S   | X   |       |     |
+| RAM32M     | X   | X     |     |
+| RAM32X1D   | X   | X     |     |
+| RAM64M     | X   |       |     |
+| RAM64X1D   | X   |       |     |
+| RAM128X1D  | X   |       |     |
+| RAM256X1S  | X   |       |     |
+| RAM128X1S  | X   |       |     |
+
+
+## NLUT.RAM
+
+Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.
+
+
+## NLUT.SMALL
+
+Seems to be set on smaller primitives.
+
+
+## NLUT.SRL
+
+Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E
+
+
+## WA7USED
+
+Set to 1 to propagate CLB's CX input to WA7
+
+
+## WA8USED
+
+Set to 1 to propagate CLB's BX input to WA8
+
+
+## WEMUX.CE
+
+| WEMUX.CE  | CLB RAM write enable | 
+|-----------|----------------------|
+| 0         | CLB WE input         |
+| 1         | CLB CE input         |
+