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ffconfig readme: import wiki
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
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John McMaster
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# FFConfig Fuzzer
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Documents the following:
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- FF clock inversion
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- FF primitive mapping
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- FF initialization value
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Tags for CLB tiles use a dot-separated hierarchy for their tag names. For example the tag `CLBLL_L.SLICEL_X0.ALUT.INIT[00]` documents the bit position of the LSB LUT init bit for the ALUT for the slice with even X coordinate within a `CLBLL_L` tile. (There are 4 LUTs in a slice: ALUT, BLUT, CLUT, and DLUT. And there are two slices in a CLB tile: One with an even X coordinate using the `SLICEL_X0` namespace for tags, and one with an odd X coordinate using the `SLICEL_X1` namespace for tags.)
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Clock inversion is per slice (as BEL CLKINV)
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Vivado GUI is misleading as it often shows it per FF, which is not actually true
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Also note mapping between FF/latch library elements and CLB FF's:
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| |FFSYNC|LATCH|ZRST |
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|------|------|-----|-----|
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|Sample| 00_48|30_32|30_12|
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|FDPE | | | |
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|FDSE | X | | |
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|FDRE | X | | X |
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|FDCE | | | X |
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|LDCE | | X | X |
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|LDPE | | X | |
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| Element | CE | CK | D | SR | Q |
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| ------------- | ------------- | ------------- | ------------- | ------------- | ------------- |
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| FDRE | CE | C | D | R | Q |
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| FDPE | CE | C | D | PRE | Q |
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| FDSE | CE | C | D | S | Q |
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| FDCE | CE | C | D | CLR | Q |
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| LDPE | GE | G | D | PRE | Q |
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| LDCE | GE | G | D | CLR | Q |
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And required configuration (as noted below):
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| Element | FFSYNC | LATCH | ZRST |
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| ------------- | ------------- | ------------- | ------------- |
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| FDPE | | | |
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| FDSE | 1 | | |
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| FDRE | 1 | | 1 |
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| FDCE | | | 1 |
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| LDCE | | 1 | 1 |
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| LDPE | | 1 | |
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```
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CLB.SLICE_X0.A5FF.ZINIT 31_06
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CLB.SLICE_X0.A5FF.ZRESET 01_07
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CLB.SLICE_X0.AFF.ZINIT 31_03
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CLB.SLICE_X0.AFF.ZRESET 30_12
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CLB.SLICE_X0.B5FF.ZINIT 31_22
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CLB.SLICE_X0.B5FF.ZRESET 01_19
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CLB.SLICE_X0.BFF.ZINIT 31_28
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CLB.SLICE_X0.BFF.ZRESET 30_30
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CLB.SLICE_X0.C5FF.ZINIT 31_41
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CLB.SLICE_X0.C5FF.ZRESET 01_47
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CLB.SLICE_X0.CFF.ZINIT 31_33
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CLB.SLICE_X0.CFF.ZRESET 30_33
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CLB.SLICE_X0.CLKINV 01_51
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CLB.SLICE_X0.D5FF.ZINIT 31_51
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CLB.SLICE_X0.D5FF.ZRESET 01_55
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CLB.SLICE_X0.DFF.ZINIT 31_58
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CLB.SLICE_X0.DFF.ZRESET 30_50
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CLB.SLICE_X0.FFSYNC 00_48
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CLB.SLICE_X0.LATCH 30_32
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CLB.SLICE_X1.A5FF.ZINIT 31_05
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CLB.SLICE_X1.A5FF.ZRESET 01_03
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CLB.SLICE_X1.AFF.ZINIT 31_04
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CLB.SLICE_X1.AFF.ZRESET 31_15
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CLB.SLICE_X1.B5FF.ZINIT 31_23
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CLB.SLICE_X1.B5FF.ZRESET 00_16
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CLB.SLICE_X1.BFF.ZINIT 31_29
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CLB.SLICE_X1.BFF.ZRESET 31_30
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CLB.SLICE_X1.C5FF.ZINIT 31_42
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CLB.SLICE_X1.C5FF.ZRESET 00_44
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CLB.SLICE_X1.CFF.ZINIT 31_34
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CLB.SLICE_X1.CFF.ZRESET 30_34
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CLB.SLICE_X1.CLKINV 00_52
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CLB.SLICE_X1.D5FF.ZINIT 31_52
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CLB.SLICE_X1.D5FF.ZRESET 00_56
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CLB.SLICE_X1.DFF.ZINIT 31_59
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CLB.SLICE_X1.DFF.ZRESET 31_50
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CLB.SLICE_X1.FFSYNC 01_31
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CLB.SLICE_X1.LATCH 31_32
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```
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## CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]*FF.ZINI
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Sets GSR FF or latch value
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FF
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* 0: reset / initialize to 1
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* 1: reset / initialize to 0
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Latch
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* 0: reset / initialize to 0
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* 1: reset / initialize to 1
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## CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]*FF.ZRST
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Set when reset signal should set storage element to 0. Specifically:
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* 0: FDRE, FDCE, and LDCE primitives
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* 1: FDPE, FDSE, and LDPE primitives
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## CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]LUT.INIT
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TBD
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## CLBL[LM]_[LR].SLICE[LM]_X[01].FFSYNC
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Unlike most bits, shared between all CLB FFs
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* 0: synchronous reset, specifically FDPE, FDCE, LDCE, and LDPE primitives
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* 1: asynchronous reset, specifically FDSE and FDRE primitives
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## CLBL[LM]_[LR].SLICE[LM]_X[01].LATCH
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Controls latch vs FF behavior for the CLB
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* 0: all storage elements in the CLB are FF's
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* 1: LUT6 storage elements are latches (LDCE or LDPE). LUT5 storage elements cannot be used
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## CLBL[LM]_[LR].SLICE[LM]_X[01].CEUSEDMUX
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Configure ability to drive clock enable (CE) or always enable clock
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* 0: always on (CE=1)
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* 1: controlled (CE=mywire)
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## CLBL[LM]_[LR].SLICE[LM]_X[01].SRUSEDMUX
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Configure ability to reset FF after GSR
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* 0: never reset (R=0)
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* 1: controlled (R=mywire)
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TODO: how used when SR?
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## CLBL[LM]_[LR].SLICE[LM]_X[01].CLKINV
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Whether to invert the clock going into a slice.
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FF:
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* 0: normal clock
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* 1: invert clock
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Latch:
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* 0: invert clock
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* 1: normal clock
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That is, for example, FDSE_1 will have the bit set, but LDCE_1 will have the bit clear.
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Note: clock cannot be inverted at individual FF's
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