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20 Commits

Author SHA1 Message Date
Dr Jonathan Richard Robert Kimmitt a8de0afdb3 virtex7: HP-bank glue codified end-to-end + open-flow validation 
The open-flow (Yosys → nextpnr-xilinx → FASM → bitstream) now produces
silicon-functional bits on VC707 xc7vx485tffg1761-2 for:
  - rst_to_led (IBUF↔OBUF passthrough)
  - counter_skewfree (button-clocked 8b counter, general routing)
  - counter_sw_bufr (button → BUFR → 8b counter)
  - counter_bufr  (200 MHz LVDS sysclk → IBUFDS → BUFR → 8b counter)
  - counter_2bufg (2× BUFGCTRL on the same source)
  - vc707_telegraph (125 MHz crystal → IBUFDS_GTE2 → BUFG → UART smoke test)
  - vc707_picosoc  (picorv32 + simpleuart + BRAM @ 125 MHz; UART prints
                    'PicoSoC alive on VC707 @ 125 MHz' on /dev/ttyUSB0)

Highlights of this drop:

utils/fasm2frames.py (+223 net):
  - Bank-glue auto-injection for HP-bank IOB18 — IBUF/OBUF (Y0+Y1) +
    IBUFDS differential pair. Fires off the FASM-level direction
    heuristic (.IN/.IN_ONLY/IBUFDISABLE for IBUF, .DRIVE. for OBUF,
    .IN_DIFF for IBUFDS; .SLEW. is unreliable as a marker — gets emitted
    on default-state IOBs too).
  - INT_L_X32Y49 DCI cascade / bank-active markers when any LIOB18_X81
    Y1 OBUF is present.
  - PUDC_B emission rewritten for HP-bank IOSTANDARDs (10 features
    cover Y0 + Y1 default-state; all 9 historic 'PUDC_B glue' bits
    flow naturally from the existing IOSTANDARD segbits).
  - HCLK_L per-BUFRCLK-channel 'active' marker — currently codified
    for BUFRCLK3 (the channel exercised by counter_sw_bufr).
  - GFAN T-tie root glue — INT_L_X62Y(N+10).GFAN_TIE_ROOT_GLUE when
    INT_L_X62Y(N).GFAN0.GND_WIRE appears (OBUF.T → GND routing).
  - PUDC_B tile excluded from the bank-glue walk (its IN features are
    virtual; injecting OBUF_HP_BANK_GLUE on it produces spurious bits).

utils/utils.tcl (+47):
  - write_pip_txtdata bulk-fetch — replaces per-net foreach pip with
    bulk get_pips + bulk get_property IS_DIRECTIONAL + cached
    dst_wire_to_num_pips. ~4× speed-up on xc7vx485t (per-spec time on
    041-clk-hrow-pips / 045-hclk-cmt-pips drops from ~1.5 h to ~25 min).

utils/mergedb.sh (+15):
  - LIOI / LIOI_TBYTESRC / LIOI_TBYTETERM / LIOB18 / mask_liob18 sed
    rewrites for the L-side IOI/IOB18 tiles on HP-only parts (xc7vx485t
    uses left-side IOB18 too; upstream kintex7 mergedb only knew the
    right side).

11 fuzzers patched for virtex7 readiness:
  - 030-iob18 Makefile: split DB target for virtex7 (HP-only); the BUFR
    HP-bank results come from the actual fuzzer rather than HR-side sed.
  - 037-iob18-pips: L-side mirror tiles (LIOI / LIOI_TBYTESRC /
    LIOI_TBYTETERM) added to segdata glob; *_SING tiles excluded;
    EXCLUDE_RE updated for L-side prefixes.
  - 039-hclk-config: split virtex7 vs kintex7 (HCLK_IOI vs HCLK_IOI3);
    XRAY_IOSTANDARD env var; IOB18M/IOB33M alternation.
  - 047a-hclk-idelayctrl-pips: accepts both HCLK_IOI and HCLK_IOI3.
  - 041, 045, 034, 034b, 043, 044, 046: removed local
    write_pip_txtdata override that shadowed the patched utils.tcl
    bulk-fetch (was re-introducing the slow per-net Tcl path).

README.md (+86):
  - 'Virtex-7 Port Status (virtex7-support branch)' section —
    achievements, goals, work-in-progress, constraints.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
 2026-05-29 10:13:53 +01:00
Alessandro Comodi 0219727e9c cells_data: add clock information on ports.json 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 13:47:38 +01:00
Tomasz Michalak c66f4f4aa1 Add license headers to tcl files 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Karol Gugala 64b39ffa29 utils.tcl: add get_tile_types function 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-04-28 18:53:06 -07:00
Keith Rothman 457c0cde6f Make generic generate_top for tilegrid. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-12 16:43:02 -08:00
Keith Rothman 8e8cf174de Refactor INT fuzzers. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-04 17:45:05 -08:00
John McMaster b8840ae9ff rempips: try a few times to solve on failures 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-12-19 15:43:04 -08:00
John McMaster 54dcdf1f2e tcl: reformat existing code 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-12-05 16:52:56 -08:00
John McMaster 9971c143bd route_via: loop check 
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
 2018-12-05 16:08:24 -08:00
Clifford Wolf 9f9c348bfd Add roi_tiles TCL helper function, remove XRAY_HCLK_[LR] 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2017-12-24 19:39:23 +01:00
Clifford Wolf 2801c7f77f Add fuzzers/057-bipips 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf e51535ddbf Add 051-intpips2 fuzzer 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf c8188315f7 Add lvb_long_mux minitest 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf 2bfd460bca Add nodes_wires_list minitests 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf 316824542c Add tile_wire_pairs utility function 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf f2214a4917 Improve/fix 013-intpips 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf 919888dc9e Add randplace_pblock TCL function 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf 61c51d6a15 Add segprint.py, use in switchboxes minitest 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf 1ce90e7f21 Add routing test to switchboxes minitest 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00
Clifford Wolf 6f88afe92a Add utils.tcl, minor edits to switchboxes minitests 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
 2017-12-20 22:46:39 +01:00