mirror of https://github.com/openXC7/prjxray.git
Add fuzzers/057-bipips
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf
Tim 'mithro' Ansell
parent
a0f08cf3a2
commit
2801c7f77f
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@ -22,7 +22,7 @@ source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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@ -22,7 +22,7 @@ source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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@ -22,7 +22,7 @@ source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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@ -22,7 +22,7 @@ source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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@ -22,7 +22,7 @@ source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping and PIPs for tile $tile ($tile_type) to $filename."
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puts "Dumping PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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@ -0,0 +1,13 @@
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/filtered_seg_int_l.segbits
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/filtered_seg_int_r.segbits
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/pattern_l.txt
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/pattern_r.txt
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/bipiplist.dcp
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/bipiplist/
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/bipips_int_l.txt
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/bipips_int_r.txt
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/seg_int_l.segbits
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/seg_int_r.segbits
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/specimen_[0-9][0-9][0-9]/
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/todo.txt
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/vivado*
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@ -0,0 +1,29 @@
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N := 10
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_l.segbits $(addsuffix /segdata_clbl[lm]_l.txt,$(SPECIMENS))
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${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_r.segbits $(addsuffix /segdata_clbl[lm]_r.txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} int_l seg_int_l.segbits
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${XRAY_MERGEDB} int_r seg_int_r.segbits
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${XRAY_DBFIXUP}
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$(SPECIMENS_OK): todo.txt
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bash generate.sh $(subst /OK,,$@)
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touch $@
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todo.txt:
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vivado -mode batch -source bipiplist.tcl
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python3 maketodo.py | sort -R | head -n5 > todo.txt
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clean:
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rm -rf .Xil/ .cache/ vivado* todo.txt
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rm -rf bipiplist/ bipiplist.dcp bipips_int_[lr].txt
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rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits
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.PHONY: database pushdb clean
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@ -0,0 +1,40 @@
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create_project -force -part $::env(XRAY_PART) bipiplist bipiplist
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force bipiplist.dcp
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source ../../utils/utils.tcl
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proc print_tile_pips {tile_type filename} {
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set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0]
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puts "Dumping bidirectional PIPs for tile $tile ($tile_type) to $filename."
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set fp [open $filename w]
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foreach pip [lsort [get_pips -filter {!IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] {
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set src [get_wires -uphill -of_objects $pip]
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set dst [get_wires -downhill -of_objects $pip]
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if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} {
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puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]"
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puts $fp "$tile_type.[regsub {.*/} $src ""].[regsub {.*/} $dst ""]"
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}
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}
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close $fp
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}
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print_tile_pips INT_L bipips_int_l.txt
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print_tile_pips INT_R bipips_int_r.txt
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@ -0,0 +1,49 @@
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#!/usr/bin/env python3
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import sys, os, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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tiledata = dict()
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pipdata = set()
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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ab, dst, src = line.split()
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tile, dst = dst.split("/")
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_, src = src.split("/")
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if tile not in tiledata:
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tiledata[tile] = {
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"pips": set(),
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"nodes": set(),
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}
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if ab == "A":
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tiledata[tile]["pips"].add((dst, src))
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pipdata.add((dst, src))
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else:
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tiledata[tile]["nodes"].add(src)
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tiledata[tile]["nodes"].add(dst)
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for tile, pips_nodes in tiledata.items():
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pips = pips_nodes["pips"]
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nodes = pips_nodes["nodes"]
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for dst, src in pipdata:
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if (dst, src) in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in nodes and src not in nodes:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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def bitfilter(frame_idx, bit_idx):
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assert os.getenv("XRAY_DATABASE") == "artix7"
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return frame_idx in [0, 1]
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -0,0 +1,11 @@
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#!/bin/bash
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source ${XRAY_GENHEADER}
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while ! vivado -mode batch -source ../generate.tcl; do
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rm -rf design*
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done
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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python3 ../generate.py
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@ -0,0 +1,78 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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# write_checkpoint -force design.dcp
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source ../../../utils/utils.tcl
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set fp [open "../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
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set fp [open "design.txt" w]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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puts "== $idx: $line"
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
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puts "PIP Tile: $tile"
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set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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puts "LUT Tile (Site): $other_tile ($driver_site)"
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set_property -dict "LOC $driver_site BEL A6LUT" $mylut
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set mynet [create_net mynet_$idx]
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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route_via $mynet "$tile/$src_wire $tile/$dst_wire"
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if {[get_pips -filter "NAME == \"${tile}/${tile_type}.${src_wire}<<->>${dst_wire}\" || NAME == \"${tile}/${tile_type}.${dst_wire}<<->>${src_wire}\"" -of_objects [get_nets $mynet]] != ""} {
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puts $fp "A $tile/$dst_wire $tile/$src_wire"
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}
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}
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route_design
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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puts $fp "B [get_wires -of_objects $pip]"
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}
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}
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close $fp
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,21 @@
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#!/usr/bin/env python3
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import os, re
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def maketodo(pipfile, dbfile):
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todos = set()
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with open(pipfile, "r") as f:
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for line in f:
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line = line.split()
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todos.add(line[0])
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with open(dbfile, "r") as f:
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for line in f:
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line = line.split()
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if line[0] in todos:
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todos.remove(line[0])
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for line in todos:
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print(line)
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maketodo("bipips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
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maketodo("bipips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")))
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@ -0,0 +1,3 @@
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module top (input i, output o);
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assign o = i;
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endmodule
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@ -18,6 +18,7 @@ proc route_via {net nodes} {
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puts " $from_node -> $to_node: $route"
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set fixed_route [concat $fixed_route [lrange $route 1 end]]
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}
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set_property -quiet FIXED_ROUTE $fixed_route $net
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}
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set_property -quiet FIXED_ROUTE $fixed_route $net
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