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tcl: reformat existing code 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-12-05 16:52:20 -08:00
parent c7aacd521b
commit 54dcdf1f2e
79 changed files with 902 additions and 973 deletions
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1
experiments/clbpips/generate.tcl
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@ -40,4 +40,3 @@ proc write_txtdata {filename} {
write_bitstream -force design.bit
write_txtdata design.txt

1
experiments/gndvcc/generate.tcl
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@ -84,4 +84,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt

1
experiments/gndvcc/piplist.tcl
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@ -36,4 +36,3 @@ proc print_tile_pips {tile_type filename} {
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

1
experiments/pipsroute/generate.tcl
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@ -80,4 +80,3 @@ for {set i 100} {$i < 200} {incr i} {
write_bitstream -quiet -force design_$i.bit
write_txtdata design_$i.txt
}

1
experiments/pipsroute/piplist.tcl
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@ -36,4 +36,3 @@ proc print_tile_pips {tile_type filename} {
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

1
fuzzers/005-tilegrid/generate_bram.tcl
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@ -53,4 +53,3 @@ proc run {} {
}
run

1
fuzzers/005-tilegrid/generate_clb.tcl
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@ -59,4 +59,3 @@ proc run {} {
}
run

1
fuzzers/005-tilegrid/generate_iob.tcl
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@ -40,4 +40,3 @@ proc run {} {
}
run

1
fuzzers/005-tilegrid/generate_tiles.tcl
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@ -38,4 +38,3 @@ proc run {} {
}
run

1
fuzzers/005-tilegrid/util.tcl
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@ -167,4 +167,3 @@ proc make_project_roi { roi_var } {
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
}

1
fuzzers/007-timing/minitest/test_cell_opins.tcl
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@ -27,4 +27,3 @@ set TIME_taken [expr [clock clicks -milliseconds] - $TIME_start]
puts "Took ms: $TIME_taken"
puts "Result: $opins_zero / $nnets zero"
puts "Result: $opins_multi / $nnets multi"

1
fuzzers/007-timing/minitest/test_unique/generate.tcl
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@ -93,4 +93,3 @@ proc wires_all {} {
build_design
pips_all
wires_all

1
fuzzers/007-timing/projects/oneblinkw/generate.tcl
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@ -43,4 +43,3 @@ proc build_design {} {
build_design
write_info4

1
fuzzers/007-timing/projects/picorv32/generate.tcl
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@ -44,4 +44,3 @@ proc build_design {} {
build_design
write_info4

1
fuzzers/007-timing/projects/placelut/generate.tcl
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@ -43,4 +43,3 @@ proc build_design {} {
build_design
write_info4

1
fuzzers/007-timing/projects/placelut_fb/generate.tcl
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@ -43,4 +43,3 @@ proc build_design {} {
build_design
write_info4

1
fuzzers/007-timing/projects/placelut_ff_fb/generate.tcl
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@ -43,4 +43,3 @@ proc build_design {} {
build_design
write_info4

1
fuzzers/007-timing/projects/project.tcl
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@ -219,4 +219,3 @@ proc write_info4 {} {
# for debugging
# source ../project.tcl
# write_info4

1
fuzzers/007-timing/speed/generate.tcl
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@ -170,4 +170,3 @@ proc nodes_unique_cc {} {
build_design_full
speed_models2
nodes_unique_cc

1
fuzzers/007-timing/timgrid/generate.tcl
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@ -116,4 +116,3 @@ proc write_data {} {
build_project
write_data

1
fuzzers/010-lutinit/generate.tcl
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@ -87,4 +87,3 @@ foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
write_bitstream -force design_2.bit
write_txtdata design_2.txt

1
fuzzers/011-ffconfig/generate.tcl
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@ -62,4 +62,3 @@ foreach ff $ffs {
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
}
close $fp

1
fuzzers/012-clbn5ffmux/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/013-clbncy0/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/014-ffsrcemux/generate.tcl
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@ -56,4 +56,3 @@ foreach ff $ffs {
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
}
close $fp

1
fuzzers/015-clbnffmux/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/016-clbnoutmux/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/017-clbprecyinit/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/018-clbram/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/019-ndi1mux/generate.tcl
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@ -24,4 +24,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/025-bram-config/generate.tcl
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@ -23,4 +23,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/025-bram-config/minitest/runme.tcl
View File

@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
# BRAM SDP WEA check, to make test slightly easier to write
set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
write_bitstream -force design.bit

1
fuzzers/026-bram-data/generate.tcl
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@ -22,4 +22,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/026-bram-data/minitest/runme.tcl
View File

@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
# BRAM SDP WEA check, to make test slightly easier to write
set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}]
write_bitstream -force design.bit

1
fuzzers/050-intpips/generate.tcl
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@ -47,4 +47,3 @@ proc write_txtdata {filename} {
write_bitstream -force design.bit
write_txtdata design.txt

1
fuzzers/051-imuxlout/generate.tcl
View File

@ -88,4 +88,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt

1
fuzzers/052-clkin/generate.tcl
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@ -84,4 +84,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt

1
fuzzers/053-ctrlin/generate.tcl
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@ -84,4 +84,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt

1
fuzzers/054-gfan/generate.tcl
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@ -94,4 +94,3 @@ proc run {} {
}
run

1
fuzzers/055-gnd/generate.tcl
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@ -85,4 +85,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt

1
fuzzers/056-rempips/generate.tcl
View File

@ -84,4 +84,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
write_txtdata design.txt

1
fuzzers/057-bipips/bipiplist.tcl
View File

@ -37,4 +37,3 @@ proc print_tile_pips {tile_type filename} {
print_tile_pips INT_L bipips_int_l.txt
print_tile_pips INT_R bipips_int_r.txt

1
fuzzers/057-bipips/generate.tcl
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@ -76,4 +76,3 @@ close $fp
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
fuzzers/058-hclkpips/generate.tcl
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@ -40,4 +40,3 @@ for {set i 0} {$i < [llength $pips]} {incr i} {
puts $fp "$tile $pip"
close $fp
}

1
fuzzers/071-ppips/generate.tcl
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@ -67,4 +67,3 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R INT_L INT_R} {
write_clb_ppips_db "ppips_[string tolower $tile_type].txt" $tile
}
}

1
fuzzers/100-dsp-mskpat/generate.tcl
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@ -68,4 +68,3 @@ for {set i 10} {$i < 30} {incr i} {
write_bitstream -force design_${i}.bit
write_txtdata design_${i}.txt
}

1
fuzzers/piplist.tcl
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@ -36,4 +36,3 @@ proc print_tile_pips {tile_type filename} {
print_tile_pips INT_L pips_int_l.txt
print_tile_pips INT_R pips_int_r.txt

1
gridinfo/logicframes.tcl
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@ -14,4 +14,3 @@ foreach site $sites {
set_property INIT 64'h8000000000000001 [get_cells lut]
write_bitstream -force logicframes_${site}_1.bit
}

1
gridinfo/tiledata.tcl
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@ -13,4 +13,3 @@ foreach site [get_sites] {
puts "--tiledata-- SITEPROP $site $prop [get_property $prop $site]"
}
}

1
minitests/carry_cin_cyinit/runme.tcl
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@ -19,4 +19,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
minitests/clbconfigs/runme.tcl
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@ -23,4 +23,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
minitests/clkbuf/runme.tcl
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@ -50,4 +50,3 @@ foreach it {
write_checkpoint -force design_$id.dcp
write_bitstream -force design_$id.bit
}

1
minitests/eccbits/runme.tcl
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@ -47,4 +47,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
minitests/fixedpnr/runme.tcl
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@ -43,4 +43,3 @@ foreach variant {fdse fdce fdce_inv fdpe ldce ldpe} {
close_project
}

1
minitests/iob/DRIVE.tcl
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@ -6,4 +6,3 @@ source "$::env(SRC_DIR)/template.tcl"
set prop DRIVE
set port [get_ports do]
source "$::env(SRC_DIR)/sweep.tcl"

1
minitests/iob/IOSTANDARD.tcl
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@ -3,4 +3,3 @@ source "$::env(SRC_DIR)/template.tcl"
set prop IOSTANDARD
set port [get_ports do]
source "$::env(SRC_DIR)/sweep.tcl"

1
minitests/iob/PULLTYPE.tcl
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@ -12,4 +12,3 @@ foreach {val} $vals {
write_checkpoint -force design_$val.dcp
write_bitstream -force design_$val.bit
}

1
minitests/iob/SLEW.tcl
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@ -5,4 +5,3 @@ source "$::env(SRC_DIR)/template.tcl"
set prop SLEW
set port [get_ports do]
source "$::env(SRC_DIR)/sweep.tcl"

1
minitests/iob/runme.tcl
View File

@ -28,4 +28,3 @@ write_checkpoint -force design.dcp
# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]
write_bitstream -force design.bit

1
minitests/iob/sweep.tcl
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@ -19,4 +19,3 @@ foreach {val} $vals {
# Only write checkpoints for acceptable bitstreams
write_checkpoint -force design_$val.dcp
}

1
minitests/iob/template.tcl
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@ -23,4 +23,3 @@ write_checkpoint -force design.dcp
# set_property -dict "PACKAGE_PIN D19 IOSTANDARD LVCMOS33" $port
# set_property PULLTYPE PULLUP $port
# set_property PULLTYPE PULLDOWN $port

1
minitests/lvb_long_mux/runme.tcl
View File

@ -62,4 +62,3 @@ route_via o_OBUF {
route_design
write_checkpoint -force design_b.dcp
write_bitstream -force design_b.bit

1
minitests/nodes_wires_list/runme.tcl
View File

@ -27,4 +27,3 @@ foreach node [lsort [get_nodes -of_objects [pblock_tiles roi]]] {
if {$wires != $node} {puts $fp $wires}
}
close $fp

1
minitests/partial_reconfig_flow/roi_synthesize.tcl
View File

@ -1,4 +1,3 @@
read_verilog [lindex $argv 0]
synth_design -mode out_of_context -top roi -part $::env(XRAY_PART)
write_checkpoint -force [lindex $argv 1]

1
minitests/picorv32-v/runme.tcl
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@ -23,4 +23,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
minitests/picorv32-y/runme.tcl
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@ -29,4 +29,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

1
minitests/roi_harness/runme.tcl
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@ -482,4 +482,3 @@ if {$fixed_xdc eq ""} {
write_checkpoint -force design.dcp
#set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
write_bitstream -force design.bit

1
minitests/switchboxes/pips.tcl
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@ -60,4 +60,3 @@ proc tile_pip_report {fd tile_name} {
tile_pip_report [open "pips_clbll.txt" w] CLBLL_L_X12Y119
tile_pip_report [open "pips_int.txt" w] INT_L_X12Y119

1
minitests/switchboxes/routes.tcl
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@ -10,4 +10,3 @@ route_design
write_checkpoint -force routes.dcp
write_bitstream -force routes.bit

1
minitests/switchboxes/runme.tcl
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@ -23,4 +23,3 @@ write_bitstream -force design.bit
source ../../utils/utils.tcl
source pips.tcl
source routes.tcl

1
minitests/tiles_wires_pips/runme.tcl
View File

@ -38,4 +38,3 @@ proc print_tile_info {tile} {
foreach tile [lsort [get_tiles]] {
print_tile_info $tile
}

1
minitests/util/runme.tcl
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@ -22,4 +22,3 @@ route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

2
utils/environment.sh
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@ -28,4 +28,6 @@ export XRAY_FASM2FRAMES="python3 ${XRAY_UTILS_DIR}/fasm2frames.py"
export XRAY_BITTOOL="${XRAY_TOOLS_DIR}/bittool"
export XRAY_BLOCKWIDTH="python3 ${XRAY_UTILS_DIR}/blockwidth.py"
export XRAY_PARSEDB="python3 ${XRAY_UTILS_DIR}/parsedb.py"
export XRAY_REFORMAT_TCL="${XRAY_UTILS_DIR}/reformat.tcl"
export XRAY_TCL_REFORMAT="${XRAY_UTILS_DIR}/tcl-reformat.sh"

1
utils/utils.tcl
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@ -106,4 +106,3 @@ proc lintersect {lst1 lst2} {
proc putl {lst} {
foreach line $lst {puts $line}
}