mirror of https://github.com/openXC7/prjxray.git
30 lines
848 B
Tcl
30 lines
848 B
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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source ../../utils/utils.tcl
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set fp [open "nodes_wires_list.txt" w]
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foreach node [lsort [get_nodes -of_objects [pblock_tiles roi]]] {
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set wires [lsort [get_wires -of_objects $node]]
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if {$wires != $node} {puts $fp $wires}
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}
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close $fp
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