mirror of https://github.com/openXC7/prjxray.git
31 lines
1.1 KiB
Tcl
31 lines
1.1 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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#read_verilog $::env(SRC_DIR)/$::env(PROJECT).v
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read_verilog $::env(TOP_V)
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synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT)
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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# set_property roi/dut
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design]
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write_bitstream -force design.bit
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