mirror of https://github.com/openXC7/prjxray.git
22 lines
768 B
Tcl
22 lines
768 B
Tcl
create_project -force -part $::env(XRAY_PART) design design
|
|
|
|
read_verilog top.v
|
|
synth_design -top top
|
|
|
|
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports ci]
|
|
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports cyinit]
|
|
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports s0]
|
|
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports o0]
|
|
|
|
set_property LOC SLICE_X17Y119 [get_cells carry4_inst]
|
|
|
|
set_property CFGBVS VCCO [current_design]
|
|
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
|
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
|
|
|
|
place_design
|
|
route_design
|
|
|
|
write_checkpoint -force design.dcp
|
|
write_bitstream -force design.bit
|