mirror of https://github.com/openXC7/prjxray.git
62 lines
1.9 KiB
Tcl
62 lines
1.9 KiB
Tcl
source "$::env(FUZDIR)/util.tcl"
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proc group_lut_cols { lut_bels } {
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column)
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set lut_columns ""
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foreach lut $lut_bels {
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regexp "SLICE_X([0-9]+)Y([0-9]+)/" $lut match slice_x slice_y
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# Only even SLICEs should be used as column bases.
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if { $slice_x % 2 != 0 } {
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continue
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}
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# 50 per column => 0, 50, 100, 150, etc
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# ex: SLICE_X2Y50/A6LUT
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# Only take one of the CLBs within a slice
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set y_column [expr ($slice_y / 50) * 50]
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dict append lut_columns "X${slice_x}Y${y_column}" "$lut "
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}
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return $lut_columns
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}
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proc loc_luts {} {
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set lut_bels [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set lut_columns [group_lut_cols $lut_bels]
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return [loc_dut_col_bels $lut_columns {roi/luts[} {].lut}]
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}
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proc write_clbs { selected_luts } {
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puts "write_brams: [llength $selected_luts] LUTs"
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puts ""
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# Toggle one bit in each selected LUT to generate base addresses
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for {set i 0} {$i < [llength $selected_luts]} {incr i} {
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puts ""
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set cell [get_cells roi/luts[$i].lut]
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puts "LUT $cell"
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set orig_init [get_property INIT $cell]
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# Flip a bit by changing MSB 0 => 1
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set new_init [regsub "h8" $orig_init "h0"]
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puts "INIT $orig_init => $new_init"
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set_property INIT $new_init $cell
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set site [get_sites -of_objects [lindex $selected_luts $i]]
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write_bitstream -force design_$site.bit
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set_property INIT $orig_init $cell
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}
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}
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proc run {} {
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make_project
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set selected_luts [loc_luts]
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puts "Selected LUTs: [llength $selected_luts]"
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_clbs $selected_luts
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}
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run
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