mirror of https://github.com/openXC7/prjxray.git
43 lines
1.3 KiB
Tcl
43 lines
1.3 KiB
Tcl
create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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write_checkpoint -force design.dcp
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source ../../../utils/utils.tcl
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if [regexp "_001$" [pwd]] {set tile [lindex [filter [roi_tiles] {TILE_TYPE == HCLK_L}] 0]}
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if [regexp "_002$" [pwd]] {set tile [lindex [filter [roi_tiles] {TILE_TYPE == HCLK_R}] 0]}
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set net [get_nets o_OBUF]
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set pips [get_pips -of_objects $tile]
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for {set i 0} {$i < [llength $pips]} {incr i} {
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set pip [lindex $pips $i]
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set_property IS_ROUTE_FIXED 0 $net
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route_design -unroute -net $net
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set n1 [get_nodes -uphill -of_objects $pip]
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set n2 [get_nodes -downhill -of_objects $pip]
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route_via $net "$n1 $n2"
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write_checkpoint -force design_$i.dcp
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write_bitstream -force design_$i.bit
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set fp [open "design_$i.txt" w]
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puts $fp "$tile $pip"
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close $fp
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}
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