e8eab9a45b
Bump chip database
2026-03-18 13:13:58 +01:00
6572d46414
Allowing the assignment of TDO pin (IO_S3_B3) on the second die for A2 ( #18 )
...
* JTAG Pins also exist on 1B Die. Allow the S3 Bank to be assigned to the second Die
* Add attribute pins to class Bank, defining the list of allowed pins
* Potential fix for pull request finding
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
* Generate white list for WA Bank
---------
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
2026-03-18 13:13:11 +01:00
bc3df10ff3
Add alternate clock routes and CP pass through [sc-184] ( #17 )
...
* Add alternate clock routes
* Add pins for alternate signals
* Add more pips and placeholder for metadata
* Add data/mask for pips
* Add pips for testing
* fix CPE_CPLINES OUTx inputs
* resources
* Added rest of CP lines pips
* Change to block and resource
* Fix chip database error
* Timing data for CP lines
* Fix bitstream
* Bump database version
2026-02-25 08:11:36 +01:00
8f0b8a06f2
Extending for LUT permutation ( #14 )
2025-12-22 15:10:11 +01:00
81bb944e2b
Remove duplicated pips
2025-12-12 08:05:12 +01:00
1901f4b833
Bump chip database version
2025-11-10 12:00:22 +01:00
6f9f132d55
Make bridge pips not visible
2025-11-10 11:59:39 +01:00
632b223ce1
Add missing timings for IM
2025-11-10 11:59:31 +01:00
f081ba87cb
Bump version to 1.9
2025-10-17 11:56:29 +02:00
867835f7bb
Better naming for D2D and pass trough TES as on hardware
2025-10-07 13:11:27 +02:00
781780f017
Fix TES and RES
2025-10-07 12:24:43 +02:00
36f6b5eec4
Bump version to 1.8
2025-09-23 08:08:07 +02:00
dda08d7bcd
Use proper timing info
2025-09-12 10:02:38 +02:00
8dfe05b5c5
put back old delay values
2025-09-11 16:45:42 +02:00
5bae9cae91
del_dummy is default delay
2025-09-11 15:21:09 +02:00
5a03c49c49
sortout multidie connections
2025-09-11 15:07:57 +02:00
81bb1c5cb8
additional wires for IO and CLK for SB_BIG/SML
2025-09-11 14:58:21 +02:00
3aec20a773
use sam delay
2025-09-11 14:11:47 +02:00
eae068fa3e
fix
2025-09-11 11:49:06 +02:00
d4f1bea09d
convert some connections to pips
2025-09-11 10:34:34 +02:00
56c2bed294
Cleanup BRAM
2025-09-04 15:57:16 +02:00
f6654f83a7
bump chipdb
2025-09-02 14:04:37 +02:00
0747679717
Add bridge
2025-09-02 08:07:43 +02:00
d04286b39a
bump database version
2025-08-29 14:57:41 +02:00
b8c59f9f80
Cleanup
2025-08-29 14:47:59 +02:00
74265fd1b8
Split BRAMs into halfs
2025-08-28 15:09:49 +02:00
6ad315609d
Bump database version
2025-08-14 11:53:29 +02:00
10b52f37f1
Added IOSEL
2025-08-13 15:49:44 +02:00
0fb182de18
rename to match port names
2025-08-13 12:52:04 +02:00
7d94d89855
Fix direction
2025-08-13 12:51:33 +02:00
c89ea91209
Preps for MX8 support
2025-07-07 10:12:59 +02:00
a08f3ddba4
Added few more connections
2025-07-07 10:12:59 +02:00
37e6d93a30
Connect upper and lower L2T4
2025-07-07 10:12:59 +02:00
e7ca710859
small change in model
2025-07-07 10:12:59 +02:00
d68f6fb08b
Add CPE_COMP and CPE_CPLINES
2025-07-07 10:12:59 +02:00
2983a7f4ff
Bump database version
2025-07-07 10:12:59 +02:00
78ac740eee
Cleanup
2025-07-07 10:12:59 +02:00
aff4544421
Cleanups
2025-07-07 10:12:59 +02:00
c27ceac7a0
Added CPOUT and MUXOUT
2025-07-07 10:12:59 +02:00
4ba2a563a1
Update primitives z locations
2025-07-07 10:12:59 +02:00
497e5cc2a1
C_2D_IN flag
2025-07-07 10:12:59 +02:00
2bdf4065c0
Add comb to seq connection
2025-07-07 10:12:59 +02:00
1a1a3488f7
Improved model of CPE
2025-07-07 10:12:59 +02:00
ff2445f353
Add D2D support
2025-06-18 08:31:49 +02:00
08b35c4538
Add DDR pin information
2025-06-18 08:31:49 +02:00
2aa7ef65ba
Add in tile position
2025-06-18 08:31:49 +02:00
a0afc3aea3
Fixed wrong bank mapping
2025-06-18 08:31:49 +02:00
58a098407b
Bump version to 1.2
2025-06-18 08:31:49 +02:00
b5dda7196f
Add PAD connections so we do not loose that info
2025-06-18 08:31:49 +02:00
83785af4ea
GLBOUT and PLL fixes
2025-06-18 08:31:49 +02:00
Miodrag Milanovic
Hai Luong