Improved model of CPE
This commit is contained in:
Miodrag Milanovic
Miodrag Milanović
parent
ff2445f353
commit
1a1a3488f7
194
gatemate/die.py
194
gatemate/die.py
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@ -244,43 +244,72 @@ class TileInfo:
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prim_index : int
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PRIMITIVES_PINS = {
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"CPE_HALF_U": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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"CPE_LT_U": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_FF_U": [
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Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("DOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_RAMIO_U": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_LT_L": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_FF_L": [
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Pin("DIN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("DOUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_RAMIO_L": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("I" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_LT_FULL": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN5" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN6" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN7" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("IN8" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("OUT1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("OUT2" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"CPE_HALF_L": [
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Pin("RAM_I" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN2" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN3" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("IN4" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("CLK" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("EN" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("SR" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("OUT" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("RAM_O" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE_L", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE_B", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE_B", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE_T", True),
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"CPE_LINES": [
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Pin("CINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINX" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY1" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("CINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("PINY2" ,PinType.INPUT, "CPE_WIRE", True),
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Pin("COUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTX" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY1" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("COUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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Pin("POUTY2" ,PinType.OUTPUT, "CPE_WIRE", True),
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],
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"GPIO" : [
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@ -1337,8 +1366,14 @@ def get_groups_for_type(type):
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def get_primitives_for_type(type):
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primitives = []
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if "CPE" in type:
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primitives.append(Primitive("CPE_HALF_U","CPE_HALF_U",0))
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primitives.append(Primitive("CPE_HALF_L","CPE_HALF_L",1))
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primitives.append(Primitive("CPE_LT_U","CPE_LT_U",0))
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primitives.append(Primitive("CPE_LT_L","CPE_LT_L",1))
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primitives.append(Primitive("CPE_FF_U","CPE_FF_U",2))
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primitives.append(Primitive("CPE_FF_L","CPE_FF_L",3))
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primitives.append(Primitive("CPE_RAMIO_U","CPE_RAMIO_U",4))
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primitives.append(Primitive("CPE_RAMIO_L","CPE_RAMIO_L",5))
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primitives.append(Primitive("CPE_LINES","CPE_LINES",6))
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primitives.append(Primitive("CPE_LT_FULL","CPE_LT_FULL",7))
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if "RAM" in type:
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primitives.append(Primitive("RAM","RAM",4))
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if "SERDES" in type:
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@ -2324,10 +2359,10 @@ def get_pins_constraint(type_name, prim_name, prim_type):
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return val
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def get_pin_connection_name(prim, pin):
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if prim.type == "CPE_HALF_U":
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if prim.type == "CPE_LT_U":
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match pin.name:
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case "OUT":
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return "CPE.OUT2"
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return "CPE.COMBOUT2_int"
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case "IN1":
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return "CPE.IN1_int"
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case "IN2":
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@ -2336,16 +2371,32 @@ def get_pin_connection_name(prim, pin):
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return "CPE.IN3_int"
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case "IN4":
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return "CPE.IN4_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_FF_U":
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match pin.name:
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case "DIN":
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return "CPE.DIN2_int"
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case "DOUT":
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return "CPE.DOUT2_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_RAMIO_U":
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match pin.name:
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case "OUT":
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return "CPE.OUT2"
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case "RAM_O":
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return "CPE.RAM_O2"
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case "RAM_I":
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return "CPE.RAM_I2"
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case "I":
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return "CPE.OUT2_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_HALF_L":
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elif prim.type == "CPE_LT_L":
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match pin.name:
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case "OUT":
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return "CPE.OUT1"
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return "CPE.COMBOUT1_int"
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case "IN1":
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return "CPE.IN5_int"
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case "IN2":
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@ -2354,10 +2405,54 @@ def get_pin_connection_name(prim, pin):
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return "CPE.IN7_int"
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case "IN4":
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return "CPE.IN8_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_LT_FULL":
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match pin.name:
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case "OUT1":
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return "CPE.COMBOUT1_int"
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case "OUT2":
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return "CPE.COMBOUT2_int"
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case "IN1":
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return "CPE.IN1_int"
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case "IN2":
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return "CPE.IN2_int"
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case "IN3":
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return "CPE.IN3_int"
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case "IN4":
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return "CPE.IN4_int"
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case "IN5":
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return "CPE.IN5_int"
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case "IN6":
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return "CPE.IN6_int"
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case "IN7":
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return "CPE.IN7_int"
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case "IN8":
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return "CPE.IN8_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_FF_L":
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match pin.name:
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case "DIN":
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return "CPE.DIN1_int"
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case "DOUT":
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return "CPE.DOUT1_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_RAMIO_L":
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match pin.name:
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case "OUT":
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return "CPE.OUT1"
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case "RAM_O":
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return "CPE.RAM_O1"
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case "RAM_I":
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return "CPE.RAM_I1"
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case "I":
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return "CPE.OUT1_int"
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case _:
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return f"CPE.{pin.name}"
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elif prim.type == "CPE_LINES":
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match pin.name:
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case _:
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return f"CPE.{pin.name}"
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return f"{prim.name}.{pin.name}"
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@ -2391,6 +2486,14 @@ def get_endpoints_for_type(type):
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create_wire("CPE.IN6_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN7_int", type="CPE_WIRE_INT")
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create_wire("CPE.IN8_int", type="CPE_WIRE_INT")
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create_wire("CPE.OUT1_int", type="CPE_WIRE_INT")
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create_wire("CPE.OUT2_int", type="CPE_WIRE_INT")
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create_wire("CPE.COMBOUT1_int", type="CPE_WIRE_INT")
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create_wire("CPE.COMBOUT2_int", type="CPE_WIRE_INT")
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create_wire("CPE.DIN1_int", type="CPE_WIRE_INT")
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create_wire("CPE.DIN2_int", type="CPE_WIRE_INT")
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create_wire("CPE.DOUT1_int", type="CPE_WIRE_INT")
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create_wire("CPE.DOUT2_int", type="CPE_WIRE_INT")
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create_wire("CPE.CLK" , type="CPE_WIRE_L")
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create_wire("CPE.EN" , type="CPE_WIRE_L")
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create_wire("CPE.SR" , type="CPE_WIRE_L")
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@ -2574,6 +2677,15 @@ def get_mux_connections_for_type(type):
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if "OM" in type and p>=9:
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for i in range(4):
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create_mux(f"OM.P{plane}.D{i}", f"OM.P{plane}.Y", 2, i, True, f"OM.P{plane}")
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create_mux("CPE.DOUT1_int", "CPE.OUT1_int", 2, 0, False, "CPE.C_O1")
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create_mux("CPE.COMBOUT1_int", "CPE.OUT1_int", 2, 3, False, "CPE.C_O1")
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create_mux("CPE.DOUT2_int", "CPE.OUT2_int", 2, 0, False, "CPE.C_O2")
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create_mux("CPE.COMBOUT2_int", "CPE.OUT2_int", 2, 3, False, "CPE.C_O2")
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# Virtual connections
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create_mux("CPE.OUT1_int", "CPE.OUT1", 1, 0, False, visible=False)
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create_mux("CPE.OUT2_int", "CPE.OUT2", 1, 0, False, visible=False)
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if "SB_BIG" in type:
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# SB_BIG
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