Add DDR pin information
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2aa7ef65ba
commit
08b35c4538
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@ -18,7 +18,7 @@
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import die
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import os
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from die import Die
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from die import Die, Location
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from dataclasses import dataclass
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from typing import List, Dict
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from timing import decompress_timing
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@ -34,6 +34,7 @@ class Pad:
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function : str
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bank : int
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flags : int
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ddr : Location
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@dataclass
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class Bank:
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@ -135,6 +136,7 @@ class Chip:
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for p in ["A","B"]:
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for num in range(9):
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d = self.dies[bank.die]
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ddr = d.ddr_i[bank.bank]
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loc = d.io_pad_names[bank.bank][p][num]
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pad_name = f"IO_{name}_{p}{num}"
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flags = 0
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@ -142,7 +144,7 @@ class Chip:
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if bank.bank == "W2" and p == "A" and num in [5,6,7,8]:
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flags = 8-num+1 # will be 1-4 for different clock sources
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if pad_name not in not_exist:
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pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"GPIO","",self.get_bank_number(bank.bank),flags))
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pads.append(Pad(loc.x + d.offset_x,loc.y + d.offset_y,pad_name,"GPIO","",self.get_bank_number(bank.bank),flags,ddr))
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return pads
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CCGM1_DEVICES = {
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@ -225,6 +225,7 @@ class MUX:
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class Location:
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x : int
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y : int
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z : int
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@dataclass(eq=True, order=True)
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class Connection:
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@ -2862,6 +2863,7 @@ class Die:
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self.gpio_to_loc = dict()
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self.conn = dict()
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self.rev_conn = dict()
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self.ddr_i = dict()
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for y in range(-2, max_row()+1):
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for x in range(-2, max_col()+1):
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if is_gpio(x,y):
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@ -2872,8 +2874,8 @@ class Die:
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self.io_pad_names[io.bank][io.port] = dict()
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if io.num not in self.io_pad_names[io.bank][io.port]:
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self.io_pad_names[io.bank][io.port][io.num] = dict()
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self.gpio_to_loc[f"GPIO_{io.bank}_{io.port}[{io.num}]"] = Location(x, y)
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self.io_pad_names[io.bank][io.port][io.num] = Location(x, y)
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self.gpio_to_loc[f"GPIO_{io.bank}_{io.port}[{io.num}]"] = Location(x, y, 0)
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self.io_pad_names[io.bank][io.port][io.num] = Location(x, y, 0)
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def create_conn(self, src_x,src_y, src, dst_x, dst_y, dst, delay=""):
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key_val = f"{src_x + self.offset_x}/{src_y + self.offset_y}/{src}"
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@ -3250,6 +3252,7 @@ class Die:
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for num in range(0,9):
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loc = self.io_pad_names[bank][port][num]
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self.create_conn(x, y , f"CPE.RAM_O{out}", loc.x, loc.y, "GPIO.DDR")
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self.ddr_i[bank] = Location(x+self.offset_x,y+self.offset_y,2-out)
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def misc_connections(self):
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self.create_ram_io_conn("CFG_CTRL", "CFG_CTRL", CTRL_X_POS, CTRL_Y_POS)
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